1 /* 2 * ata_piix.c - Intel PATA/SATA controllers 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * 9 * Copyright 2003-2005 Red Hat Inc 10 * Copyright 2003-2005 Jeff Garzik 11 * 12 * 13 * Copyright header from piix.c: 14 * 15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 17 * Copyright (C) 2003 Red Hat Inc 18 * 19 * 20 * This program is free software; you can redistribute it and/or modify 21 * it under the terms of the GNU General Public License as published by 22 * the Free Software Foundation; either version 2, or (at your option) 23 * any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; see the file COPYING. If not, write to 32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 33 * 34 * 35 * libata documentation is available via 'make {ps|pdf}docs', 36 * as Documentation/DocBook/libata.* 37 * 38 * Hardware documentation available at http://developer.intel.com/ 39 * 40 * Documentation 41 * Publically available from Intel web site. Errata documentation 42 * is also publically available. As an aide to anyone hacking on this 43 * driver the list of errata that are relevant is below, going back to 44 * PIIX4. Older device documentation is now a bit tricky to find. 45 * 46 * The chipsets all follow very much the same design. The orginal Triton 47 * series chipsets do _not_ support independant device timings, but this 48 * is fixed in Triton II. With the odd mobile exception the chips then 49 * change little except in gaining more modes until SATA arrives. This 50 * driver supports only the chips with independant timing (that is those 51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix 52 * for the early chip drivers. 53 * 54 * Errata of note: 55 * 56 * Unfixable 57 * PIIX4 errata #9 - Only on ultra obscure hw 58 * ICH3 errata #13 - Not observed to affect real hw 59 * by Intel 60 * 61 * Things we must deal with 62 * PIIX4 errata #10 - BM IDE hang with non UDMA 63 * (must stop/start dma to recover) 64 * 440MX errata #15 - As PIIX4 errata #10 65 * PIIX4 errata #15 - Must not read control registers 66 * during a PIO transfer 67 * 440MX errata #13 - As PIIX4 errata #15 68 * ICH2 errata #21 - DMA mode 0 doesn't work right 69 * ICH0/1 errata #55 - As ICH2 errata #21 70 * ICH2 spec c #9 - Extra operations needed to handle 71 * drive hotswap [NOT YET SUPPORTED] 72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary 73 * and must be dword aligned 74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 75 * ICH7 errata #16 - MWDMA1 timings are incorrect 76 * 77 * Should have been BIOS fixed: 78 * 450NX: errata #19 - DMA hangs on old 450NX 79 * 450NX: errata #20 - DMA hangs on old 450NX 80 * 450NX: errata #25 - Corruption with DMA on old 450NX 81 * ICH3 errata #15 - IDE deadlock under high load 82 * (BIOS must set dev 31 fn 0 bit 23) 83 * ICH3 errata #18 - Don't use native mode 84 */ 85 86 #include <linux/kernel.h> 87 #include <linux/module.h> 88 #include <linux/pci.h> 89 #include <linux/init.h> 90 #include <linux/blkdev.h> 91 #include <linux/delay.h> 92 #include <linux/device.h> 93 #include <scsi/scsi_host.h> 94 #include <linux/libata.h> 95 #include <linux/dmi.h> 96 97 #define DRV_NAME "ata_piix" 98 #define DRV_VERSION "2.13" 99 100 enum { 101 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 102 ICH5_PMR = 0x90, /* port mapping register */ 103 ICH5_PCS = 0x92, /* port control and status */ 104 PIIX_SIDPR_BAR = 5, 105 PIIX_SIDPR_LEN = 16, 106 PIIX_SIDPR_IDX = 0, 107 PIIX_SIDPR_DATA = 4, 108 109 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ 110 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ 111 112 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, 113 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, 114 115 PIIX_80C_PRI = (1 << 5) | (1 << 4), 116 PIIX_80C_SEC = (1 << 7) | (1 << 6), 117 118 /* constants for mapping table */ 119 P0 = 0, /* port 0 */ 120 P1 = 1, /* port 1 */ 121 P2 = 2, /* port 2 */ 122 P3 = 3, /* port 3 */ 123 IDE = -1, /* IDE */ 124 NA = -2, /* not avaliable */ 125 RV = -3, /* reserved */ 126 127 PIIX_AHCI_DEVICE = 6, 128 129 /* host->flags bits */ 130 PIIX_HOST_BROKEN_SUSPEND = (1 << 24), 131 }; 132 133 enum piix_controller_ids { 134 /* controller IDs */ 135 piix_pata_mwdma, /* PIIX3 MWDMA only */ 136 piix_pata_33, /* PIIX4 at 33Mhz */ 137 ich_pata_33, /* ICH up to UDMA 33 only */ 138 ich_pata_66, /* ICH up to 66 Mhz */ 139 ich_pata_100, /* ICH up to UDMA 100 */ 140 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/ 141 ich5_sata, 142 ich6_sata, 143 ich6m_sata, 144 ich8_sata, 145 ich8_2port_sata, 146 ich8m_apple_sata, /* locks up on second port enable */ 147 tolapai_sata, 148 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ 149 }; 150 151 struct piix_map_db { 152 const u32 mask; 153 const u16 port_enable; 154 const int map[][4]; 155 }; 156 157 struct piix_host_priv { 158 const int *map; 159 u32 saved_iocfg; 160 void __iomem *sidpr; 161 }; 162 163 static int piix_init_one(struct pci_dev *pdev, 164 const struct pci_device_id *ent); 165 static void piix_remove_one(struct pci_dev *pdev); 166 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline); 167 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); 168 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); 169 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); 170 static int ich_pata_cable_detect(struct ata_port *ap); 171 static u8 piix_vmw_bmdma_status(struct ata_port *ap); 172 static int piix_sidpr_scr_read(struct ata_link *link, 173 unsigned int reg, u32 *val); 174 static int piix_sidpr_scr_write(struct ata_link *link, 175 unsigned int reg, u32 val); 176 #ifdef CONFIG_PM 177 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 178 static int piix_pci_device_resume(struct pci_dev *pdev); 179 #endif 180 181 static unsigned int in_module_init = 1; 182 183 static const struct pci_device_id piix_pci_tbl[] = { 184 /* Intel PIIX3 for the 430HX etc */ 185 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, 186 /* VMware ICH4 */ 187 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw }, 188 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ 189 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ 190 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 191 /* Intel PIIX4 */ 192 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 193 /* Intel PIIX4 */ 194 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 195 /* Intel PIIX */ 196 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 197 /* Intel ICH (i810, i815, i840) UDMA 66*/ 198 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, 199 /* Intel ICH0 : UDMA 33*/ 200 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, 201 /* Intel ICH2M */ 202 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 203 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ 204 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 205 /* Intel ICH3M */ 206 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 207 /* Intel ICH3 (E7500/1) UDMA 100 */ 208 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 209 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ 210 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 211 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 212 /* Intel ICH5 */ 213 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 214 /* C-ICH (i810E2) */ 215 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 216 /* ESB (855GME/875P + 6300ESB) UDMA 100 */ 217 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 218 /* ICH6 (and 6) (i915) UDMA 100 */ 219 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 220 /* ICH7/7-R (i945, i975) UDMA 100*/ 221 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, 222 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, 223 /* ICH8 Mobile PATA Controller */ 224 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 225 226 /* SATA ports */ 227 228 /* 82801EB (ICH5) */ 229 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 230 /* 82801EB (ICH5) */ 231 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 232 /* 6300ESB (ICH5 variant with broken PCS present bits) */ 233 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 234 /* 6300ESB pretending RAID */ 235 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 236 /* 82801FB/FW (ICH6/ICH6W) */ 237 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 238 /* 82801FR/FRW (ICH6R/ICH6RW) */ 239 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 240 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented). 241 * Attach iff the controller is in IDE mode. */ 242 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 243 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata }, 244 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 245 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 246 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ 247 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata }, 248 /* Enterprise Southbridge 2 (631xESB/632xESB) */ 249 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 250 /* SATA Controller 1 IDE (ICH8) */ 251 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 252 /* SATA Controller 2 IDE (ICH8) */ 253 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 254 /* Mobile SATA Controller IDE (ICH8M), Apple */ 255 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, 256 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata }, 257 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata }, 258 /* Mobile SATA Controller IDE (ICH8M) */ 259 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 260 /* SATA Controller IDE (ICH9) */ 261 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 262 /* SATA Controller IDE (ICH9) */ 263 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 264 /* SATA Controller IDE (ICH9) */ 265 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 266 /* SATA Controller IDE (ICH9M) */ 267 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 268 /* SATA Controller IDE (ICH9M) */ 269 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 270 /* SATA Controller IDE (ICH9M) */ 271 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 272 /* SATA Controller IDE (Tolapai) */ 273 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata }, 274 /* SATA Controller IDE (ICH10) */ 275 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 276 /* SATA Controller IDE (ICH10) */ 277 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 278 /* SATA Controller IDE (ICH10) */ 279 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 280 /* SATA Controller IDE (ICH10) */ 281 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 282 /* SATA Controller IDE (PCH) */ 283 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 284 /* SATA Controller IDE (PCH) */ 285 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 286 /* SATA Controller IDE (PCH) */ 287 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 288 /* SATA Controller IDE (PCH) */ 289 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 290 /* SATA Controller IDE (PCH) */ 291 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 292 /* SATA Controller IDE (PCH) */ 293 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 294 { } /* terminate list */ 295 }; 296 297 static struct pci_driver piix_pci_driver = { 298 .name = DRV_NAME, 299 .id_table = piix_pci_tbl, 300 .probe = piix_init_one, 301 .remove = piix_remove_one, 302 #ifdef CONFIG_PM 303 .suspend = piix_pci_device_suspend, 304 .resume = piix_pci_device_resume, 305 #endif 306 }; 307 308 static struct scsi_host_template piix_sht = { 309 ATA_BMDMA_SHT(DRV_NAME), 310 }; 311 312 static struct ata_port_operations piix_pata_ops = { 313 .inherits = &ata_bmdma32_port_ops, 314 .cable_detect = ata_cable_40wire, 315 .set_piomode = piix_set_piomode, 316 .set_dmamode = piix_set_dmamode, 317 .prereset = piix_pata_prereset, 318 }; 319 320 static struct ata_port_operations piix_vmw_ops = { 321 .inherits = &piix_pata_ops, 322 .bmdma_status = piix_vmw_bmdma_status, 323 }; 324 325 static struct ata_port_operations ich_pata_ops = { 326 .inherits = &piix_pata_ops, 327 .cable_detect = ich_pata_cable_detect, 328 .set_dmamode = ich_set_dmamode, 329 }; 330 331 static struct ata_port_operations piix_sata_ops = { 332 .inherits = &ata_bmdma_port_ops, 333 }; 334 335 static struct ata_port_operations piix_sidpr_sata_ops = { 336 .inherits = &piix_sata_ops, 337 .hardreset = sata_std_hardreset, 338 .scr_read = piix_sidpr_scr_read, 339 .scr_write = piix_sidpr_scr_write, 340 }; 341 342 static const struct piix_map_db ich5_map_db = { 343 .mask = 0x7, 344 .port_enable = 0x3, 345 .map = { 346 /* PM PS SM SS MAP */ 347 { P0, NA, P1, NA }, /* 000b */ 348 { P1, NA, P0, NA }, /* 001b */ 349 { RV, RV, RV, RV }, 350 { RV, RV, RV, RV }, 351 { P0, P1, IDE, IDE }, /* 100b */ 352 { P1, P0, IDE, IDE }, /* 101b */ 353 { IDE, IDE, P0, P1 }, /* 110b */ 354 { IDE, IDE, P1, P0 }, /* 111b */ 355 }, 356 }; 357 358 static const struct piix_map_db ich6_map_db = { 359 .mask = 0x3, 360 .port_enable = 0xf, 361 .map = { 362 /* PM PS SM SS MAP */ 363 { P0, P2, P1, P3 }, /* 00b */ 364 { IDE, IDE, P1, P3 }, /* 01b */ 365 { P0, P2, IDE, IDE }, /* 10b */ 366 { RV, RV, RV, RV }, 367 }, 368 }; 369 370 static const struct piix_map_db ich6m_map_db = { 371 .mask = 0x3, 372 .port_enable = 0x5, 373 374 /* Map 01b isn't specified in the doc but some notebooks use 375 * it anyway. MAP 01b have been spotted on both ICH6M and 376 * ICH7M. 377 */ 378 .map = { 379 /* PM PS SM SS MAP */ 380 { P0, P2, NA, NA }, /* 00b */ 381 { IDE, IDE, P1, P3 }, /* 01b */ 382 { P0, P2, IDE, IDE }, /* 10b */ 383 { RV, RV, RV, RV }, 384 }, 385 }; 386 387 static const struct piix_map_db ich8_map_db = { 388 .mask = 0x3, 389 .port_enable = 0xf, 390 .map = { 391 /* PM PS SM SS MAP */ 392 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ 393 { RV, RV, RV, RV }, 394 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ 395 { RV, RV, RV, RV }, 396 }, 397 }; 398 399 static const struct piix_map_db ich8_2port_map_db = { 400 .mask = 0x3, 401 .port_enable = 0x3, 402 .map = { 403 /* PM PS SM SS MAP */ 404 { P0, NA, P1, NA }, /* 00b */ 405 { RV, RV, RV, RV }, /* 01b */ 406 { RV, RV, RV, RV }, /* 10b */ 407 { RV, RV, RV, RV }, 408 }, 409 }; 410 411 static const struct piix_map_db ich8m_apple_map_db = { 412 .mask = 0x3, 413 .port_enable = 0x1, 414 .map = { 415 /* PM PS SM SS MAP */ 416 { P0, NA, NA, NA }, /* 00b */ 417 { RV, RV, RV, RV }, 418 { P0, P2, IDE, IDE }, /* 10b */ 419 { RV, RV, RV, RV }, 420 }, 421 }; 422 423 static const struct piix_map_db tolapai_map_db = { 424 .mask = 0x3, 425 .port_enable = 0x3, 426 .map = { 427 /* PM PS SM SS MAP */ 428 { P0, NA, P1, NA }, /* 00b */ 429 { RV, RV, RV, RV }, /* 01b */ 430 { RV, RV, RV, RV }, /* 10b */ 431 { RV, RV, RV, RV }, 432 }, 433 }; 434 435 static const struct piix_map_db *piix_map_db_table[] = { 436 [ich5_sata] = &ich5_map_db, 437 [ich6_sata] = &ich6_map_db, 438 [ich6m_sata] = &ich6m_map_db, 439 [ich8_sata] = &ich8_map_db, 440 [ich8_2port_sata] = &ich8_2port_map_db, 441 [ich8m_apple_sata] = &ich8m_apple_map_db, 442 [tolapai_sata] = &tolapai_map_db, 443 }; 444 445 static struct ata_port_info piix_port_info[] = { 446 [piix_pata_mwdma] = /* PIIX3 MWDMA only */ 447 { 448 .flags = PIIX_PATA_FLAGS, 449 .pio_mask = ATA_PIO4, 450 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 451 .port_ops = &piix_pata_ops, 452 }, 453 454 [piix_pata_33] = /* PIIX4 at 33MHz */ 455 { 456 .flags = PIIX_PATA_FLAGS, 457 .pio_mask = ATA_PIO4, 458 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 459 .udma_mask = ATA_UDMA2, 460 .port_ops = &piix_pata_ops, 461 }, 462 463 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ 464 { 465 .flags = PIIX_PATA_FLAGS, 466 .pio_mask = ATA_PIO4, 467 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */ 468 .udma_mask = ATA_UDMA2, 469 .port_ops = &ich_pata_ops, 470 }, 471 472 [ich_pata_66] = /* ICH controllers up to 66MHz */ 473 { 474 .flags = PIIX_PATA_FLAGS, 475 .pio_mask = ATA_PIO4, 476 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */ 477 .udma_mask = ATA_UDMA4, 478 .port_ops = &ich_pata_ops, 479 }, 480 481 [ich_pata_100] = 482 { 483 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 484 .pio_mask = ATA_PIO4, 485 .mwdma_mask = ATA_MWDMA12_ONLY, 486 .udma_mask = ATA_UDMA5, 487 .port_ops = &ich_pata_ops, 488 }, 489 490 [ich_pata_100_nomwdma1] = 491 { 492 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 493 .pio_mask = ATA_PIO4, 494 .mwdma_mask = ATA_MWDMA2_ONLY, 495 .udma_mask = ATA_UDMA5, 496 .port_ops = &ich_pata_ops, 497 }, 498 499 [ich5_sata] = 500 { 501 .flags = PIIX_SATA_FLAGS, 502 .pio_mask = ATA_PIO4, 503 .mwdma_mask = ATA_MWDMA2, 504 .udma_mask = ATA_UDMA6, 505 .port_ops = &piix_sata_ops, 506 }, 507 508 [ich6_sata] = 509 { 510 .flags = PIIX_SATA_FLAGS, 511 .pio_mask = ATA_PIO4, 512 .mwdma_mask = ATA_MWDMA2, 513 .udma_mask = ATA_UDMA6, 514 .port_ops = &piix_sata_ops, 515 }, 516 517 [ich6m_sata] = 518 { 519 .flags = PIIX_SATA_FLAGS, 520 .pio_mask = ATA_PIO4, 521 .mwdma_mask = ATA_MWDMA2, 522 .udma_mask = ATA_UDMA6, 523 .port_ops = &piix_sata_ops, 524 }, 525 526 [ich8_sata] = 527 { 528 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 529 .pio_mask = ATA_PIO4, 530 .mwdma_mask = ATA_MWDMA2, 531 .udma_mask = ATA_UDMA6, 532 .port_ops = &piix_sata_ops, 533 }, 534 535 [ich8_2port_sata] = 536 { 537 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 538 .pio_mask = ATA_PIO4, 539 .mwdma_mask = ATA_MWDMA2, 540 .udma_mask = ATA_UDMA6, 541 .port_ops = &piix_sata_ops, 542 }, 543 544 [tolapai_sata] = 545 { 546 .flags = PIIX_SATA_FLAGS, 547 .pio_mask = ATA_PIO4, 548 .mwdma_mask = ATA_MWDMA2, 549 .udma_mask = ATA_UDMA6, 550 .port_ops = &piix_sata_ops, 551 }, 552 553 [ich8m_apple_sata] = 554 { 555 .flags = PIIX_SATA_FLAGS, 556 .pio_mask = ATA_PIO4, 557 .mwdma_mask = ATA_MWDMA2, 558 .udma_mask = ATA_UDMA6, 559 .port_ops = &piix_sata_ops, 560 }, 561 562 [piix_pata_vmw] = 563 { 564 .flags = PIIX_PATA_FLAGS, 565 .pio_mask = ATA_PIO4, 566 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 567 .udma_mask = ATA_UDMA2, 568 .port_ops = &piix_vmw_ops, 569 }, 570 571 }; 572 573 static struct pci_bits piix_enable_bits[] = { 574 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 575 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 576 }; 577 578 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); 579 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); 580 MODULE_LICENSE("GPL"); 581 MODULE_DEVICE_TABLE(pci, piix_pci_tbl); 582 MODULE_VERSION(DRV_VERSION); 583 584 struct ich_laptop { 585 u16 device; 586 u16 subvendor; 587 u16 subdevice; 588 }; 589 590 /* 591 * List of laptops that use short cables rather than 80 wire 592 */ 593 594 static const struct ich_laptop ich_laptop[] = { 595 /* devid, subvendor, subdev */ 596 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ 597 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ 598 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ 599 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 600 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ 601 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */ 602 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ 603 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */ 604 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */ 605 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ 606 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */ 607 /* end marker */ 608 { 0, } 609 }; 610 611 /** 612 * ich_pata_cable_detect - Probe host controller cable detect info 613 * @ap: Port for which cable detect info is desired 614 * 615 * Read 80c cable indicator from ATA PCI device's PCI config 616 * register. This register is normally set by firmware (BIOS). 617 * 618 * LOCKING: 619 * None (inherited from caller). 620 */ 621 622 static int ich_pata_cable_detect(struct ata_port *ap) 623 { 624 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 625 struct piix_host_priv *hpriv = ap->host->private_data; 626 const struct ich_laptop *lap = &ich_laptop[0]; 627 u8 mask; 628 629 /* Check for specials - Acer Aspire 5602WLMi */ 630 while (lap->device) { 631 if (lap->device == pdev->device && 632 lap->subvendor == pdev->subsystem_vendor && 633 lap->subdevice == pdev->subsystem_device) 634 return ATA_CBL_PATA40_SHORT; 635 636 lap++; 637 } 638 639 /* check BIOS cable detect results */ 640 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; 641 if ((hpriv->saved_iocfg & mask) == 0) 642 return ATA_CBL_PATA40; 643 return ATA_CBL_PATA80; 644 } 645 646 /** 647 * piix_pata_prereset - prereset for PATA host controller 648 * @link: Target link 649 * @deadline: deadline jiffies for the operation 650 * 651 * LOCKING: 652 * None (inherited from caller). 653 */ 654 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) 655 { 656 struct ata_port *ap = link->ap; 657 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 658 659 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) 660 return -ENOENT; 661 return ata_sff_prereset(link, deadline); 662 } 663 664 /** 665 * piix_set_piomode - Initialize host controller PATA PIO timings 666 * @ap: Port whose timings we are configuring 667 * @adev: um 668 * 669 * Set PIO mode for device, in host controller PCI config space. 670 * 671 * LOCKING: 672 * None (inherited from caller). 673 */ 674 675 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) 676 { 677 unsigned int pio = adev->pio_mode - XFER_PIO_0; 678 struct pci_dev *dev = to_pci_dev(ap->host->dev); 679 unsigned int is_slave = (adev->devno != 0); 680 unsigned int master_port= ap->port_no ? 0x42 : 0x40; 681 unsigned int slave_port = 0x44; 682 u16 master_data; 683 u8 slave_data; 684 u8 udma_enable; 685 int control = 0; 686 687 /* 688 * See Intel Document 298600-004 for the timing programing rules 689 * for ICH controllers. 690 */ 691 692 static const /* ISP RTC */ 693 u8 timings[][2] = { { 0, 0 }, 694 { 0, 0 }, 695 { 1, 0 }, 696 { 2, 1 }, 697 { 2, 3 }, }; 698 699 if (pio >= 2) 700 control |= 1; /* TIME1 enable */ 701 if (ata_pio_need_iordy(adev)) 702 control |= 2; /* IE enable */ 703 704 /* Intel specifies that the PPE functionality is for disk only */ 705 if (adev->class == ATA_DEV_ATA) 706 control |= 4; /* PPE enable */ 707 708 /* PIO configuration clears DTE unconditionally. It will be 709 * programmed in set_dmamode which is guaranteed to be called 710 * after set_piomode if any DMA mode is available. 711 */ 712 pci_read_config_word(dev, master_port, &master_data); 713 if (is_slave) { 714 /* clear TIME1|IE1|PPE1|DTE1 */ 715 master_data &= 0xff0f; 716 /* Enable SITRE (separate slave timing register) */ 717 master_data |= 0x4000; 718 /* enable PPE1, IE1 and TIME1 as needed */ 719 master_data |= (control << 4); 720 pci_read_config_byte(dev, slave_port, &slave_data); 721 slave_data &= (ap->port_no ? 0x0f : 0xf0); 722 /* Load the timing nibble for this slave */ 723 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) 724 << (ap->port_no ? 4 : 0); 725 } else { 726 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ 727 master_data &= 0xccf0; 728 /* Enable PPE, IE and TIME as appropriate */ 729 master_data |= control; 730 /* load ISP and RCT */ 731 master_data |= 732 (timings[pio][0] << 12) | 733 (timings[pio][1] << 8); 734 } 735 pci_write_config_word(dev, master_port, master_data); 736 if (is_slave) 737 pci_write_config_byte(dev, slave_port, slave_data); 738 739 /* Ensure the UDMA bit is off - it will be turned back on if 740 UDMA is selected */ 741 742 if (ap->udma_mask) { 743 pci_read_config_byte(dev, 0x48, &udma_enable); 744 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); 745 pci_write_config_byte(dev, 0x48, udma_enable); 746 } 747 } 748 749 /** 750 * do_pata_set_dmamode - Initialize host controller PATA PIO timings 751 * @ap: Port whose timings we are configuring 752 * @adev: Drive in question 753 * @isich: set if the chip is an ICH device 754 * 755 * Set UDMA mode for device, in host controller PCI config space. 756 * 757 * LOCKING: 758 * None (inherited from caller). 759 */ 760 761 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) 762 { 763 struct pci_dev *dev = to_pci_dev(ap->host->dev); 764 u8 master_port = ap->port_no ? 0x42 : 0x40; 765 u16 master_data; 766 u8 speed = adev->dma_mode; 767 int devid = adev->devno + 2 * ap->port_no; 768 u8 udma_enable = 0; 769 770 static const /* ISP RTC */ 771 u8 timings[][2] = { { 0, 0 }, 772 { 0, 0 }, 773 { 1, 0 }, 774 { 2, 1 }, 775 { 2, 3 }, }; 776 777 pci_read_config_word(dev, master_port, &master_data); 778 if (ap->udma_mask) 779 pci_read_config_byte(dev, 0x48, &udma_enable); 780 781 if (speed >= XFER_UDMA_0) { 782 unsigned int udma = adev->dma_mode - XFER_UDMA_0; 783 u16 udma_timing; 784 u16 ideconf; 785 int u_clock, u_speed; 786 787 /* 788 * UDMA is handled by a combination of clock switching and 789 * selection of dividers 790 * 791 * Handy rule: Odd modes are UDMATIMx 01, even are 02 792 * except UDMA0 which is 00 793 */ 794 u_speed = min(2 - (udma & 1), udma); 795 if (udma == 5) 796 u_clock = 0x1000; /* 100Mhz */ 797 else if (udma > 2) 798 u_clock = 1; /* 66Mhz */ 799 else 800 u_clock = 0; /* 33Mhz */ 801 802 udma_enable |= (1 << devid); 803 804 /* Load the CT/RP selection */ 805 pci_read_config_word(dev, 0x4A, &udma_timing); 806 udma_timing &= ~(3 << (4 * devid)); 807 udma_timing |= u_speed << (4 * devid); 808 pci_write_config_word(dev, 0x4A, udma_timing); 809 810 if (isich) { 811 /* Select a 33/66/100Mhz clock */ 812 pci_read_config_word(dev, 0x54, &ideconf); 813 ideconf &= ~(0x1001 << devid); 814 ideconf |= u_clock << devid; 815 /* For ICH or later we should set bit 10 for better 816 performance (WR_PingPong_En) */ 817 pci_write_config_word(dev, 0x54, ideconf); 818 } 819 } else { 820 /* 821 * MWDMA is driven by the PIO timings. We must also enable 822 * IORDY unconditionally along with TIME1. PPE has already 823 * been set when the PIO timing was set. 824 */ 825 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; 826 unsigned int control; 827 u8 slave_data; 828 const unsigned int needed_pio[3] = { 829 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 830 }; 831 int pio = needed_pio[mwdma] - XFER_PIO_0; 832 833 control = 3; /* IORDY|TIME1 */ 834 835 /* If the drive MWDMA is faster than it can do PIO then 836 we must force PIO into PIO0 */ 837 838 if (adev->pio_mode < needed_pio[mwdma]) 839 /* Enable DMA timing only */ 840 control |= 8; /* PIO cycles in PIO0 */ 841 842 if (adev->devno) { /* Slave */ 843 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ 844 master_data |= control << 4; 845 pci_read_config_byte(dev, 0x44, &slave_data); 846 slave_data &= (ap->port_no ? 0x0f : 0xf0); 847 /* Load the matching timing */ 848 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); 849 pci_write_config_byte(dev, 0x44, slave_data); 850 } else { /* Master */ 851 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY 852 and master timing bits */ 853 master_data |= control; 854 master_data |= 855 (timings[pio][0] << 12) | 856 (timings[pio][1] << 8); 857 } 858 859 if (ap->udma_mask) { 860 udma_enable &= ~(1 << devid); 861 pci_write_config_word(dev, master_port, master_data); 862 } 863 } 864 /* Don't scribble on 0x48 if the controller does not support UDMA */ 865 if (ap->udma_mask) 866 pci_write_config_byte(dev, 0x48, udma_enable); 867 } 868 869 /** 870 * piix_set_dmamode - Initialize host controller PATA DMA timings 871 * @ap: Port whose timings we are configuring 872 * @adev: um 873 * 874 * Set MW/UDMA mode for device, in host controller PCI config space. 875 * 876 * LOCKING: 877 * None (inherited from caller). 878 */ 879 880 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) 881 { 882 do_pata_set_dmamode(ap, adev, 0); 883 } 884 885 /** 886 * ich_set_dmamode - Initialize host controller PATA DMA timings 887 * @ap: Port whose timings we are configuring 888 * @adev: um 889 * 890 * Set MW/UDMA mode for device, in host controller PCI config space. 891 * 892 * LOCKING: 893 * None (inherited from caller). 894 */ 895 896 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) 897 { 898 do_pata_set_dmamode(ap, adev, 1); 899 } 900 901 /* 902 * Serial ATA Index/Data Pair Superset Registers access 903 * 904 * Beginning from ICH8, there's a sane way to access SCRs using index 905 * and data register pair located at BAR5 which means that we have 906 * separate SCRs for master and slave. This is handled using libata 907 * slave_link facility. 908 */ 909 static const int piix_sidx_map[] = { 910 [SCR_STATUS] = 0, 911 [SCR_ERROR] = 2, 912 [SCR_CONTROL] = 1, 913 }; 914 915 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg) 916 { 917 struct ata_port *ap = link->ap; 918 struct piix_host_priv *hpriv = ap->host->private_data; 919 920 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg], 921 hpriv->sidpr + PIIX_SIDPR_IDX); 922 } 923 924 static int piix_sidpr_scr_read(struct ata_link *link, 925 unsigned int reg, u32 *val) 926 { 927 struct piix_host_priv *hpriv = link->ap->host->private_data; 928 929 if (reg >= ARRAY_SIZE(piix_sidx_map)) 930 return -EINVAL; 931 932 piix_sidpr_sel(link, reg); 933 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); 934 return 0; 935 } 936 937 static int piix_sidpr_scr_write(struct ata_link *link, 938 unsigned int reg, u32 val) 939 { 940 struct piix_host_priv *hpriv = link->ap->host->private_data; 941 942 if (reg >= ARRAY_SIZE(piix_sidx_map)) 943 return -EINVAL; 944 945 piix_sidpr_sel(link, reg); 946 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); 947 return 0; 948 } 949 950 #ifdef CONFIG_PM 951 static int piix_broken_suspend(void) 952 { 953 static const struct dmi_system_id sysids[] = { 954 { 955 .ident = "TECRA M3", 956 .matches = { 957 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 958 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), 959 }, 960 }, 961 { 962 .ident = "TECRA M3", 963 .matches = { 964 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 965 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), 966 }, 967 }, 968 { 969 .ident = "TECRA M4", 970 .matches = { 971 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 972 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), 973 }, 974 }, 975 { 976 .ident = "TECRA M4", 977 .matches = { 978 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 979 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"), 980 }, 981 }, 982 { 983 .ident = "TECRA M5", 984 .matches = { 985 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 986 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), 987 }, 988 }, 989 { 990 .ident = "TECRA M6", 991 .matches = { 992 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 993 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), 994 }, 995 }, 996 { 997 .ident = "TECRA M7", 998 .matches = { 999 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1000 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), 1001 }, 1002 }, 1003 { 1004 .ident = "TECRA A8", 1005 .matches = { 1006 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1007 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), 1008 }, 1009 }, 1010 { 1011 .ident = "Satellite R20", 1012 .matches = { 1013 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1014 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), 1015 }, 1016 }, 1017 { 1018 .ident = "Satellite R25", 1019 .matches = { 1020 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1021 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), 1022 }, 1023 }, 1024 { 1025 .ident = "Satellite U200", 1026 .matches = { 1027 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1028 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), 1029 }, 1030 }, 1031 { 1032 .ident = "Satellite U200", 1033 .matches = { 1034 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1035 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), 1036 }, 1037 }, 1038 { 1039 .ident = "Satellite Pro U200", 1040 .matches = { 1041 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1042 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), 1043 }, 1044 }, 1045 { 1046 .ident = "Satellite U205", 1047 .matches = { 1048 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1049 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), 1050 }, 1051 }, 1052 { 1053 .ident = "SATELLITE U205", 1054 .matches = { 1055 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1056 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), 1057 }, 1058 }, 1059 { 1060 .ident = "Portege M500", 1061 .matches = { 1062 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1063 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), 1064 }, 1065 }, 1066 { 1067 .ident = "VGN-BX297XP", 1068 .matches = { 1069 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"), 1070 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"), 1071 }, 1072 }, 1073 1074 { } /* terminate list */ 1075 }; 1076 static const char *oemstrs[] = { 1077 "Tecra M3,", 1078 }; 1079 int i; 1080 1081 if (dmi_check_system(sysids)) 1082 return 1; 1083 1084 for (i = 0; i < ARRAY_SIZE(oemstrs); i++) 1085 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) 1086 return 1; 1087 1088 /* TECRA M4 sometimes forgets its identify and reports bogus 1089 * DMI information. As the bogus information is a bit 1090 * generic, match as many entries as possible. This manual 1091 * matching is necessary because dmi_system_id.matches is 1092 * limited to four entries. 1093 */ 1094 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") && 1095 dmi_match(DMI_PRODUCT_NAME, "000000") && 1096 dmi_match(DMI_PRODUCT_VERSION, "000000") && 1097 dmi_match(DMI_PRODUCT_SERIAL, "000000") && 1098 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") && 1099 dmi_match(DMI_BOARD_NAME, "Portable PC") && 1100 dmi_match(DMI_BOARD_VERSION, "Version A0")) 1101 return 1; 1102 1103 return 0; 1104 } 1105 1106 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 1107 { 1108 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1109 unsigned long flags; 1110 int rc = 0; 1111 1112 rc = ata_host_suspend(host, mesg); 1113 if (rc) 1114 return rc; 1115 1116 /* Some braindamaged ACPI suspend implementations expect the 1117 * controller to be awake on entry; otherwise, it burns cpu 1118 * cycles and power trying to do something to the sleeping 1119 * beauty. 1120 */ 1121 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) { 1122 pci_save_state(pdev); 1123 1124 /* mark its power state as "unknown", since we don't 1125 * know if e.g. the BIOS will change its device state 1126 * when we suspend. 1127 */ 1128 if (pdev->current_state == PCI_D0) 1129 pdev->current_state = PCI_UNKNOWN; 1130 1131 /* tell resume that it's waking up from broken suspend */ 1132 spin_lock_irqsave(&host->lock, flags); 1133 host->flags |= PIIX_HOST_BROKEN_SUSPEND; 1134 spin_unlock_irqrestore(&host->lock, flags); 1135 } else 1136 ata_pci_device_do_suspend(pdev, mesg); 1137 1138 return 0; 1139 } 1140 1141 static int piix_pci_device_resume(struct pci_dev *pdev) 1142 { 1143 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1144 unsigned long flags; 1145 int rc; 1146 1147 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { 1148 spin_lock_irqsave(&host->lock, flags); 1149 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; 1150 spin_unlock_irqrestore(&host->lock, flags); 1151 1152 pci_set_power_state(pdev, PCI_D0); 1153 pci_restore_state(pdev); 1154 1155 /* PCI device wasn't disabled during suspend. Use 1156 * pci_reenable_device() to avoid affecting the enable 1157 * count. 1158 */ 1159 rc = pci_reenable_device(pdev); 1160 if (rc) 1161 dev_printk(KERN_ERR, &pdev->dev, "failed to enable " 1162 "device after resume (%d)\n", rc); 1163 } else 1164 rc = ata_pci_device_do_resume(pdev); 1165 1166 if (rc == 0) 1167 ata_host_resume(host); 1168 1169 return rc; 1170 } 1171 #endif 1172 1173 static u8 piix_vmw_bmdma_status(struct ata_port *ap) 1174 { 1175 return ata_bmdma_status(ap) & ~ATA_DMA_ERR; 1176 } 1177 1178 #define AHCI_PCI_BAR 5 1179 #define AHCI_GLOBAL_CTL 0x04 1180 #define AHCI_ENABLE (1 << 31) 1181 static int piix_disable_ahci(struct pci_dev *pdev) 1182 { 1183 void __iomem *mmio; 1184 u32 tmp; 1185 int rc = 0; 1186 1187 /* BUG: pci_enable_device has not yet been called. This 1188 * works because this device is usually set up by BIOS. 1189 */ 1190 1191 if (!pci_resource_start(pdev, AHCI_PCI_BAR) || 1192 !pci_resource_len(pdev, AHCI_PCI_BAR)) 1193 return 0; 1194 1195 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); 1196 if (!mmio) 1197 return -ENOMEM; 1198 1199 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1200 if (tmp & AHCI_ENABLE) { 1201 tmp &= ~AHCI_ENABLE; 1202 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); 1203 1204 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1205 if (tmp & AHCI_ENABLE) 1206 rc = -EIO; 1207 } 1208 1209 pci_iounmap(pdev, mmio); 1210 return rc; 1211 } 1212 1213 /** 1214 * piix_check_450nx_errata - Check for problem 450NX setup 1215 * @ata_dev: the PCI device to check 1216 * 1217 * Check for the present of 450NX errata #19 and errata #25. If 1218 * they are found return an error code so we can turn off DMA 1219 */ 1220 1221 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) 1222 { 1223 struct pci_dev *pdev = NULL; 1224 u16 cfg; 1225 int no_piix_dma = 0; 1226 1227 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { 1228 /* Look for 450NX PXB. Check for problem configurations 1229 A PCI quirk checks bit 6 already */ 1230 pci_read_config_word(pdev, 0x41, &cfg); 1231 /* Only on the original revision: IDE DMA can hang */ 1232 if (pdev->revision == 0x00) 1233 no_piix_dma = 1; 1234 /* On all revisions below 5 PXB bus lock must be disabled for IDE */ 1235 else if (cfg & (1<<14) && pdev->revision < 5) 1236 no_piix_dma = 2; 1237 } 1238 if (no_piix_dma) 1239 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); 1240 if (no_piix_dma == 2) 1241 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); 1242 return no_piix_dma; 1243 } 1244 1245 static void __devinit piix_init_pcs(struct ata_host *host, 1246 const struct piix_map_db *map_db) 1247 { 1248 struct pci_dev *pdev = to_pci_dev(host->dev); 1249 u16 pcs, new_pcs; 1250 1251 pci_read_config_word(pdev, ICH5_PCS, &pcs); 1252 1253 new_pcs = pcs | map_db->port_enable; 1254 1255 if (new_pcs != pcs) { 1256 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); 1257 pci_write_config_word(pdev, ICH5_PCS, new_pcs); 1258 msleep(150); 1259 } 1260 } 1261 1262 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev, 1263 struct ata_port_info *pinfo, 1264 const struct piix_map_db *map_db) 1265 { 1266 const int *map; 1267 int i, invalid_map = 0; 1268 u8 map_value; 1269 1270 pci_read_config_byte(pdev, ICH5_PMR, &map_value); 1271 1272 map = map_db->map[map_value & map_db->mask]; 1273 1274 dev_printk(KERN_INFO, &pdev->dev, "MAP ["); 1275 for (i = 0; i < 4; i++) { 1276 switch (map[i]) { 1277 case RV: 1278 invalid_map = 1; 1279 printk(" XX"); 1280 break; 1281 1282 case NA: 1283 printk(" --"); 1284 break; 1285 1286 case IDE: 1287 WARN_ON((i & 1) || map[i + 1] != IDE); 1288 pinfo[i / 2] = piix_port_info[ich_pata_100]; 1289 i++; 1290 printk(" IDE IDE"); 1291 break; 1292 1293 default: 1294 printk(" P%d", map[i]); 1295 if (i & 1) 1296 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; 1297 break; 1298 } 1299 } 1300 printk(" ]\n"); 1301 1302 if (invalid_map) 1303 dev_printk(KERN_ERR, &pdev->dev, 1304 "invalid MAP value %u\n", map_value); 1305 1306 return map; 1307 } 1308 1309 static bool piix_no_sidpr(struct ata_host *host) 1310 { 1311 struct pci_dev *pdev = to_pci_dev(host->dev); 1312 1313 /* 1314 * Samsung DB-P70 only has three ATA ports exposed and 1315 * curiously the unconnected first port reports link online 1316 * while not responding to SRST protocol causing excessive 1317 * detection delay. 1318 * 1319 * Unfortunately, the system doesn't carry enough DMI 1320 * information to identify the machine but does have subsystem 1321 * vendor and device set. As it's unclear whether the 1322 * subsystem vendor/device is used only for this specific 1323 * board, the port can't be disabled solely with the 1324 * information; however, turning off SIDPR access works around 1325 * the problem. Turn it off. 1326 * 1327 * This problem is reported in bnc#441240. 1328 * 1329 * https://bugzilla.novell.com/show_bug.cgi?id=441420 1330 */ 1331 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 && 1332 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG && 1333 pdev->subsystem_device == 0xb049) { 1334 dev_printk(KERN_WARNING, host->dev, 1335 "Samsung DB-P70 detected, disabling SIDPR\n"); 1336 return true; 1337 } 1338 1339 return false; 1340 } 1341 1342 static int __devinit piix_init_sidpr(struct ata_host *host) 1343 { 1344 struct pci_dev *pdev = to_pci_dev(host->dev); 1345 struct piix_host_priv *hpriv = host->private_data; 1346 struct ata_link *link0 = &host->ports[0]->link; 1347 u32 scontrol; 1348 int i, rc; 1349 1350 /* check for availability */ 1351 for (i = 0; i < 4; i++) 1352 if (hpriv->map[i] == IDE) 1353 return 0; 1354 1355 /* is it blacklisted? */ 1356 if (piix_no_sidpr(host)) 1357 return 0; 1358 1359 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) 1360 return 0; 1361 1362 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || 1363 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN) 1364 return 0; 1365 1366 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME)) 1367 return 0; 1368 1369 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; 1370 1371 /* SCR access via SIDPR doesn't work on some configurations. 1372 * Give it a test drive by inhibiting power save modes which 1373 * we'll do anyway. 1374 */ 1375 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); 1376 1377 /* if IPM is already 3, SCR access is probably working. Don't 1378 * un-inhibit power save modes as BIOS might have inhibited 1379 * them for a reason. 1380 */ 1381 if ((scontrol & 0xf00) != 0x300) { 1382 scontrol |= 0x300; 1383 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol); 1384 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); 1385 1386 if ((scontrol & 0xf00) != 0x300) { 1387 dev_printk(KERN_INFO, host->dev, "SCR access via " 1388 "SIDPR is available but doesn't work\n"); 1389 return 0; 1390 } 1391 } 1392 1393 /* okay, SCRs available, set ops and ask libata for slave_link */ 1394 for (i = 0; i < 2; i++) { 1395 struct ata_port *ap = host->ports[i]; 1396 1397 ap->ops = &piix_sidpr_sata_ops; 1398 1399 if (ap->flags & ATA_FLAG_SLAVE_POSS) { 1400 rc = ata_slave_link_init(ap); 1401 if (rc) 1402 return rc; 1403 } 1404 } 1405 1406 return 0; 1407 } 1408 1409 static void piix_iocfg_bit18_quirk(struct ata_host *host) 1410 { 1411 static const struct dmi_system_id sysids[] = { 1412 { 1413 /* Clevo M570U sets IOCFG bit 18 if the cdrom 1414 * isn't used to boot the system which 1415 * disables the channel. 1416 */ 1417 .ident = "M570U", 1418 .matches = { 1419 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), 1420 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), 1421 }, 1422 }, 1423 1424 { } /* terminate list */ 1425 }; 1426 struct pci_dev *pdev = to_pci_dev(host->dev); 1427 struct piix_host_priv *hpriv = host->private_data; 1428 1429 if (!dmi_check_system(sysids)) 1430 return; 1431 1432 /* The datasheet says that bit 18 is NOOP but certain systems 1433 * seem to use it to disable a channel. Clear the bit on the 1434 * affected systems. 1435 */ 1436 if (hpriv->saved_iocfg & (1 << 18)) { 1437 dev_printk(KERN_INFO, &pdev->dev, 1438 "applying IOCFG bit18 quirk\n"); 1439 pci_write_config_dword(pdev, PIIX_IOCFG, 1440 hpriv->saved_iocfg & ~(1 << 18)); 1441 } 1442 } 1443 1444 static bool piix_broken_system_poweroff(struct pci_dev *pdev) 1445 { 1446 static const struct dmi_system_id broken_systems[] = { 1447 { 1448 .ident = "HP Compaq 2510p", 1449 .matches = { 1450 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1451 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"), 1452 }, 1453 /* PCI slot number of the controller */ 1454 .driver_data = (void *)0x1FUL, 1455 }, 1456 { 1457 .ident = "HP Compaq nc6000", 1458 .matches = { 1459 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1460 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"), 1461 }, 1462 /* PCI slot number of the controller */ 1463 .driver_data = (void *)0x1FUL, 1464 }, 1465 1466 { } /* terminate list */ 1467 }; 1468 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1469 1470 if (dmi) { 1471 unsigned long slot = (unsigned long)dmi->driver_data; 1472 /* apply the quirk only to on-board controllers */ 1473 return slot == PCI_SLOT(pdev->devfn); 1474 } 1475 1476 return false; 1477 } 1478 1479 /** 1480 * piix_init_one - Register PIIX ATA PCI device with kernel services 1481 * @pdev: PCI device to register 1482 * @ent: Entry in piix_pci_tbl matching with @pdev 1483 * 1484 * Called from kernel PCI layer. We probe for combined mode (sigh), 1485 * and then hand over control to libata, for it to do the rest. 1486 * 1487 * LOCKING: 1488 * Inherited from PCI layer (may sleep). 1489 * 1490 * RETURNS: 1491 * Zero on success, or -ERRNO value. 1492 */ 1493 1494 static int __devinit piix_init_one(struct pci_dev *pdev, 1495 const struct pci_device_id *ent) 1496 { 1497 static int printed_version; 1498 struct device *dev = &pdev->dev; 1499 struct ata_port_info port_info[2]; 1500 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; 1501 unsigned long port_flags; 1502 struct ata_host *host; 1503 struct piix_host_priv *hpriv; 1504 int rc; 1505 1506 if (!printed_version++) 1507 dev_printk(KERN_DEBUG, &pdev->dev, 1508 "version " DRV_VERSION "\n"); 1509 1510 /* no hotplugging support for later devices (FIXME) */ 1511 if (!in_module_init && ent->driver_data >= ich5_sata) 1512 return -ENODEV; 1513 1514 if (piix_broken_system_poweroff(pdev)) { 1515 piix_port_info[ent->driver_data].flags |= 1516 ATA_FLAG_NO_POWEROFF_SPINDOWN | 1517 ATA_FLAG_NO_HIBERNATE_SPINDOWN; 1518 dev_info(&pdev->dev, "quirky BIOS, skipping spindown " 1519 "on poweroff and hibernation\n"); 1520 } 1521 1522 port_info[0] = piix_port_info[ent->driver_data]; 1523 port_info[1] = piix_port_info[ent->driver_data]; 1524 1525 port_flags = port_info[0].flags; 1526 1527 /* enable device and prepare host */ 1528 rc = pcim_enable_device(pdev); 1529 if (rc) 1530 return rc; 1531 1532 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1533 if (!hpriv) 1534 return -ENOMEM; 1535 1536 /* Save IOCFG, this will be used for cable detection, quirk 1537 * detection and restoration on detach. This is necessary 1538 * because some ACPI implementations mess up cable related 1539 * bits on _STM. Reported on kernel bz#11879. 1540 */ 1541 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg); 1542 1543 /* ICH6R may be driven by either ata_piix or ahci driver 1544 * regardless of BIOS configuration. Make sure AHCI mode is 1545 * off. 1546 */ 1547 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { 1548 rc = piix_disable_ahci(pdev); 1549 if (rc) 1550 return rc; 1551 } 1552 1553 /* SATA map init can change port_info, do it before prepping host */ 1554 if (port_flags & ATA_FLAG_SATA) 1555 hpriv->map = piix_init_sata_map(pdev, port_info, 1556 piix_map_db_table[ent->driver_data]); 1557 1558 rc = ata_pci_sff_prepare_host(pdev, ppi, &host); 1559 if (rc) 1560 return rc; 1561 host->private_data = hpriv; 1562 1563 /* initialize controller */ 1564 if (port_flags & ATA_FLAG_SATA) { 1565 piix_init_pcs(host, piix_map_db_table[ent->driver_data]); 1566 rc = piix_init_sidpr(host); 1567 if (rc) 1568 return rc; 1569 } 1570 1571 /* apply IOCFG bit18 quirk */ 1572 piix_iocfg_bit18_quirk(host); 1573 1574 /* On ICH5, some BIOSen disable the interrupt using the 1575 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. 1576 * On ICH6, this bit has the same effect, but only when 1577 * MSI is disabled (and it is disabled, as we don't use 1578 * message-signalled interrupts currently). 1579 */ 1580 if (port_flags & PIIX_FLAG_CHECKINTR) 1581 pci_intx(pdev, 1); 1582 1583 if (piix_check_450nx_errata(pdev)) { 1584 /* This writes into the master table but it does not 1585 really matter for this errata as we will apply it to 1586 all the PIIX devices on the board */ 1587 host->ports[0]->mwdma_mask = 0; 1588 host->ports[0]->udma_mask = 0; 1589 host->ports[1]->mwdma_mask = 0; 1590 host->ports[1]->udma_mask = 0; 1591 } 1592 host->flags |= ATA_HOST_PARALLEL_SCAN; 1593 1594 pci_set_master(pdev); 1595 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht); 1596 } 1597 1598 static void piix_remove_one(struct pci_dev *pdev) 1599 { 1600 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1601 struct piix_host_priv *hpriv = host->private_data; 1602 1603 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg); 1604 1605 ata_pci_remove_one(pdev); 1606 } 1607 1608 static int __init piix_init(void) 1609 { 1610 int rc; 1611 1612 DPRINTK("pci_register_driver\n"); 1613 rc = pci_register_driver(&piix_pci_driver); 1614 if (rc) 1615 return rc; 1616 1617 in_module_init = 0; 1618 1619 DPRINTK("done\n"); 1620 return 0; 1621 } 1622 1623 static void __exit piix_exit(void) 1624 { 1625 pci_unregister_driver(&piix_pci_driver); 1626 } 1627 1628 module_init(piix_init); 1629 module_exit(piix_exit); 1630