1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/ata/ahci_tegra.c 4 * 5 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 6 * 7 * Author: 8 * Mikko Perttunen <mperttunen@nvidia.com> 9 */ 10 11 #include <linux/ahci_platform.h> 12 #include <linux/errno.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/reset.h> 19 20 #include <soc/tegra/fuse.h> 21 #include <soc/tegra/pmc.h> 22 23 #include "ahci.h" 24 25 #define DRV_NAME "tegra-ahci" 26 27 #define SATA_CONFIGURATION_0 0x180 28 #define SATA_CONFIGURATION_0_EN_FPCI BIT(0) 29 #define SATA_CONFIGURATION_0_CLK_OVERRIDE BIT(31) 30 31 #define SCFG_OFFSET 0x1000 32 33 #define T_SATA0_CFG_1 0x04 34 #define T_SATA0_CFG_1_IO_SPACE BIT(0) 35 #define T_SATA0_CFG_1_MEMORY_SPACE BIT(1) 36 #define T_SATA0_CFG_1_BUS_MASTER BIT(2) 37 #define T_SATA0_CFG_1_SERR BIT(8) 38 39 #define T_SATA0_CFG_9 0x24 40 #define T_SATA0_CFG_9_BASE_ADDRESS 0x40020000 41 42 #define SATA_FPCI_BAR5 0x94 43 #define SATA_FPCI_BAR5_START_MASK (0xfffffff << 4) 44 #define SATA_FPCI_BAR5_START (0x0040020 << 4) 45 #define SATA_FPCI_BAR5_ACCESS_TYPE (0x1) 46 47 #define SATA_INTR_MASK 0x188 48 #define SATA_INTR_MASK_IP_INT_MASK BIT(16) 49 50 #define T_SATA0_CFG_35 0x94 51 #define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7ff << 2) 52 #define T_SATA0_CFG_35_IDP_INDEX (0x2a << 2) 53 54 #define T_SATA0_AHCI_IDP1 0x98 55 #define T_SATA0_AHCI_IDP1_DATA (0x400040) 56 57 #define T_SATA0_CFG_PHY_1 0x12c 58 #define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN BIT(23) 59 #define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22) 60 61 #define T_SATA0_NVOOB 0x114 62 #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24) 63 #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24) 64 #define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26) 65 #define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26) 66 67 #define T_SATA_CFG_PHY_0 0x120 68 #define T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD BIT(11) 69 #define T_SATA_CFG_PHY_0_MASK_SQUELCH BIT(24) 70 71 #define T_SATA0_CFG2NVOOB_2 0x134 72 #define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff << 18) 73 #define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18) 74 75 #define T_SATA0_AHCI_HBA_CAP_BKDR 0x300 76 #define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP BIT(13) 77 #define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP BIT(14) 78 #define T_SATA0_AHCI_HBA_CAP_BKDR_SALP BIT(26) 79 #define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM BIT(17) 80 #define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ BIT(30) 81 82 #define T_SATA0_BKDOOR_CC 0x4a4 83 #define T_SATA0_BKDOOR_CC_CLASS_CODE_MASK (0xffff << 16) 84 #define T_SATA0_BKDOOR_CC_CLASS_CODE (0x0106 << 16) 85 #define T_SATA0_BKDOOR_CC_PROG_IF_MASK (0xff << 8) 86 #define T_SATA0_BKDOOR_CC_PROG_IF (0x01 << 8) 87 88 #define T_SATA0_CFG_SATA 0x54c 89 #define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12) 90 91 #define T_SATA0_CFG_MISC 0x550 92 93 #define T_SATA0_INDEX 0x680 94 95 #define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690 96 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff 97 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0 98 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8) 99 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8 100 101 #define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694 102 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff 103 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0 104 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12) 105 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12 106 107 #define T_SATA0_CHX_PHY_CTRL2 0x69c 108 #define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23 109 110 #define T_SATA0_CHX_PHY_CTRL11 0x6d0 111 #define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16) 112 113 #define T_SATA0_CHX_PHY_CTRL17_0 0x6e8 114 #define T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1 0x55010000 115 #define T_SATA0_CHX_PHY_CTRL18_0 0x6ec 116 #define T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2 0x55010000 117 #define T_SATA0_CHX_PHY_CTRL20_0 0x6f4 118 #define T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1 0x1 119 #define T_SATA0_CHX_PHY_CTRL21_0 0x6f8 120 #define T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2 0x1 121 122 /* AUX Registers */ 123 #define SATA_AUX_MISC_CNTL_1_0 0x8 124 #define SATA_AUX_MISC_CNTL_1_0_DEVSLP_OVERRIDE BIT(17) 125 #define SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT BIT(13) 126 #define SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT BIT(15) 127 128 #define SATA_AUX_RX_STAT_INT_0 0xc 129 #define SATA_AUX_RX_STAT_INT_0_SATA_DEVSLP BIT(7) 130 131 #define SATA_AUX_SPARE_CFG0_0 0x18 132 #define SATA_AUX_SPARE_CFG0_0_MDAT_TIMER_AFTER_PG_VALID BIT(14) 133 134 #define FUSE_SATA_CALIB 0x124 135 #define FUSE_SATA_CALIB_MASK 0x3 136 137 struct sata_pad_calibration { 138 u8 gen1_tx_amp; 139 u8 gen1_tx_peak; 140 u8 gen2_tx_amp; 141 u8 gen2_tx_peak; 142 }; 143 144 static const struct sata_pad_calibration tegra124_pad_calibration[] = { 145 {0x18, 0x04, 0x18, 0x0a}, 146 {0x0e, 0x04, 0x14, 0x0a}, 147 {0x0e, 0x07, 0x1a, 0x0e}, 148 {0x14, 0x0e, 0x1a, 0x0e}, 149 }; 150 151 struct tegra_ahci_ops { 152 int (*init)(struct ahci_host_priv *hpriv); 153 }; 154 155 struct tegra_ahci_regs { 156 unsigned int nvoob_comma_cnt_mask; 157 unsigned int nvoob_comma_cnt_val; 158 }; 159 160 struct tegra_ahci_soc { 161 const char *const *supply_names; 162 u32 num_supplies; 163 bool supports_devslp; 164 bool has_sata_oob_rst; 165 const struct tegra_ahci_ops *ops; 166 const struct tegra_ahci_regs *regs; 167 }; 168 169 struct tegra_ahci_priv { 170 struct platform_device *pdev; 171 void __iomem *sata_regs; 172 void __iomem *sata_aux_regs; 173 struct reset_control *sata_rst; 174 struct reset_control *sata_oob_rst; 175 struct reset_control *sata_cold_rst; 176 /* Needs special handling, cannot use ahci_platform */ 177 struct clk *sata_clk; 178 struct tegra_pmc *pmc; 179 struct regulator_bulk_data *supplies; 180 const struct tegra_ahci_soc *soc; 181 }; 182 183 static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv) 184 { 185 struct tegra_ahci_priv *tegra = hpriv->plat_data; 186 u32 val; 187 188 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) { 189 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); 190 val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT; 191 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); 192 } 193 } 194 195 static int tegra124_ahci_init(struct ahci_host_priv *hpriv) 196 { 197 struct tegra_ahci_priv *tegra = hpriv->plat_data; 198 struct sata_pad_calibration calib; 199 int ret; 200 u32 val; 201 202 /* Pad calibration */ 203 ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val); 204 if (ret) 205 return ret; 206 207 calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK]; 208 209 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); 210 211 val = readl(tegra->sata_regs + 212 SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1); 213 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK; 214 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK; 215 val |= calib.gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT; 216 val |= calib.gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT; 217 writel(val, tegra->sata_regs + SCFG_OFFSET + 218 T_SATA0_CHX_PHY_CTRL1_GEN1); 219 220 val = readl(tegra->sata_regs + 221 SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2); 222 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK; 223 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK; 224 val |= calib.gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT; 225 val |= calib.gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT; 226 writel(val, tegra->sata_regs + SCFG_OFFSET + 227 T_SATA0_CHX_PHY_CTRL1_GEN2); 228 229 writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ, 230 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11); 231 writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1, 232 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2); 233 234 writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); 235 236 return 0; 237 } 238 239 static int tegra_ahci_power_on(struct ahci_host_priv *hpriv) 240 { 241 struct tegra_ahci_priv *tegra = hpriv->plat_data; 242 int ret; 243 244 ret = regulator_bulk_enable(tegra->soc->num_supplies, 245 tegra->supplies); 246 if (ret) 247 return ret; 248 249 if (!tegra->pdev->dev.pm_domain) { 250 ret = tegra_pmc_powergate_sequence_power_up(tegra->pmc, 251 TEGRA_POWERGATE_SATA, 252 tegra->sata_clk, 253 tegra->sata_rst); 254 if (ret) 255 goto disable_regulators; 256 } 257 258 reset_control_assert(tegra->sata_oob_rst); 259 reset_control_assert(tegra->sata_cold_rst); 260 261 ret = ahci_platform_enable_resources(hpriv); 262 if (ret) 263 goto disable_power; 264 265 reset_control_deassert(tegra->sata_cold_rst); 266 reset_control_deassert(tegra->sata_oob_rst); 267 268 return 0; 269 270 disable_power: 271 clk_disable_unprepare(tegra->sata_clk); 272 273 if (!tegra->pdev->dev.pm_domain) 274 tegra_pmc_powergate_power_off(tegra->pmc, TEGRA_POWERGATE_SATA); 275 276 disable_regulators: 277 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); 278 279 return ret; 280 } 281 282 static void tegra_ahci_power_off(struct ahci_host_priv *hpriv) 283 { 284 struct tegra_ahci_priv *tegra = hpriv->plat_data; 285 286 ahci_platform_disable_resources(hpriv); 287 288 reset_control_assert(tegra->sata_rst); 289 reset_control_assert(tegra->sata_oob_rst); 290 reset_control_assert(tegra->sata_cold_rst); 291 292 clk_disable_unprepare(tegra->sata_clk); 293 if (!tegra->pdev->dev.pm_domain) 294 tegra_pmc_powergate_power_off(tegra->pmc, TEGRA_POWERGATE_SATA); 295 296 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); 297 } 298 299 static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv) 300 { 301 struct tegra_ahci_priv *tegra = hpriv->plat_data; 302 int ret; 303 u32 val; 304 305 ret = tegra_ahci_power_on(hpriv); 306 if (ret) { 307 dev_err(&tegra->pdev->dev, 308 "failed to power on AHCI controller: %d\n", ret); 309 return ret; 310 } 311 312 /* 313 * Program the following SATA IPFS registers to allow SW accesses to 314 * SATA's MMIO register range. 315 */ 316 val = readl(tegra->sata_regs + SATA_FPCI_BAR5); 317 val &= ~(SATA_FPCI_BAR5_START_MASK | SATA_FPCI_BAR5_ACCESS_TYPE); 318 val |= SATA_FPCI_BAR5_START | SATA_FPCI_BAR5_ACCESS_TYPE; 319 writel(val, tegra->sata_regs + SATA_FPCI_BAR5); 320 321 /* Program the following SATA IPFS register to enable the SATA */ 322 val = readl(tegra->sata_regs + SATA_CONFIGURATION_0); 323 val |= SATA_CONFIGURATION_0_EN_FPCI; 324 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0); 325 326 /* Electrical settings for better link stability */ 327 val = T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1; 328 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17_0); 329 val = T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2; 330 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18_0); 331 val = T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1; 332 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20_0); 333 val = T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2; 334 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21_0); 335 336 /* For SQUELCH Filter & Gen3 drive getting detected as Gen1 drive */ 337 338 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0); 339 val |= T_SATA_CFG_PHY_0_MASK_SQUELCH; 340 val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD; 341 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0); 342 343 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB); 344 val &= ~(tegra->soc->regs->nvoob_comma_cnt_mask | 345 T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK | 346 T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK); 347 val |= (tegra->soc->regs->nvoob_comma_cnt_val | 348 T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH | 349 T_SATA0_NVOOB_SQUELCH_FILTER_MODE); 350 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB); 351 352 /* 353 * Change CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW from 83.3 ns to 58.8ns 354 */ 355 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2); 356 val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK; 357 val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW; 358 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2); 359 360 if (tegra->soc->ops && tegra->soc->ops->init) 361 tegra->soc->ops->init(hpriv); 362 363 /* 364 * Program the following SATA configuration registers to 365 * initialize SATA 366 */ 367 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1); 368 val |= (T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE | 369 T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR); 370 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1); 371 val = T_SATA0_CFG_9_BASE_ADDRESS; 372 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9); 373 374 /* Program Class Code and Programming interface for SATA */ 375 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); 376 val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN; 377 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); 378 379 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC); 380 val &= 381 ~(T_SATA0_BKDOOR_CC_CLASS_CODE_MASK | 382 T_SATA0_BKDOOR_CC_PROG_IF_MASK); 383 val |= T_SATA0_BKDOOR_CC_CLASS_CODE | T_SATA0_BKDOOR_CC_PROG_IF; 384 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC); 385 386 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); 387 val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN; 388 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); 389 390 /* Enabling LPM capabilities through Backdoor Programming */ 391 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR); 392 val |= (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP | 393 T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP | 394 T_SATA0_AHCI_HBA_CAP_BKDR_SALP | 395 T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM); 396 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR); 397 398 /* SATA Second Level Clock Gating configuration 399 * Enabling Gating of Tx/Rx clocks and driving Pad IDDQ and Lane 400 * IDDQ Signals 401 */ 402 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35); 403 val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK; 404 val |= T_SATA0_CFG_35_IDP_INDEX; 405 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35); 406 407 val = T_SATA0_AHCI_IDP1_DATA; 408 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1); 409 410 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1); 411 val |= (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN | 412 T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN); 413 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1); 414 415 /* Enabling IPFS Clock Gating */ 416 val = readl(tegra->sata_regs + SATA_CONFIGURATION_0); 417 val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE; 418 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0); 419 420 tegra_ahci_handle_quirks(hpriv); 421 422 /* Unmask SATA interrupts */ 423 424 val = readl(tegra->sata_regs + SATA_INTR_MASK); 425 val |= SATA_INTR_MASK_IP_INT_MASK; 426 writel(val, tegra->sata_regs + SATA_INTR_MASK); 427 428 return 0; 429 } 430 431 static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv) 432 { 433 tegra_ahci_power_off(hpriv); 434 } 435 436 static void tegra_ahci_host_stop(struct ata_host *host) 437 { 438 struct ahci_host_priv *hpriv = host->private_data; 439 440 tegra_ahci_controller_deinit(hpriv); 441 } 442 443 static struct ata_port_operations ahci_tegra_port_ops = { 444 .inherits = &ahci_ops, 445 .host_stop = tegra_ahci_host_stop, 446 }; 447 448 static const struct ata_port_info ahci_tegra_port_info = { 449 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 450 .pio_mask = ATA_PIO4, 451 .udma_mask = ATA_UDMA6, 452 .port_ops = &ahci_tegra_port_ops, 453 }; 454 455 static const char *const tegra124_supply_names[] = { 456 "avdd", "hvdd", "vddio", "target-5v", "target-12v" 457 }; 458 459 static const struct tegra_ahci_ops tegra124_ahci_ops = { 460 .init = tegra124_ahci_init, 461 }; 462 463 static const struct tegra_ahci_regs tegra124_ahci_regs = { 464 .nvoob_comma_cnt_mask = GENMASK(30, 28), 465 .nvoob_comma_cnt_val = (7 << 28), 466 }; 467 468 static const struct tegra_ahci_soc tegra124_ahci_soc = { 469 .supply_names = tegra124_supply_names, 470 .num_supplies = ARRAY_SIZE(tegra124_supply_names), 471 .supports_devslp = false, 472 .has_sata_oob_rst = true, 473 .ops = &tegra124_ahci_ops, 474 .regs = &tegra124_ahci_regs, 475 }; 476 477 static const struct tegra_ahci_soc tegra210_ahci_soc = { 478 .supports_devslp = false, 479 .has_sata_oob_rst = true, 480 .regs = &tegra124_ahci_regs, 481 }; 482 483 static const struct tegra_ahci_regs tegra186_ahci_regs = { 484 .nvoob_comma_cnt_mask = GENMASK(23, 16), 485 .nvoob_comma_cnt_val = (7 << 16), 486 }; 487 488 static const struct tegra_ahci_soc tegra186_ahci_soc = { 489 .supports_devslp = false, 490 .has_sata_oob_rst = false, 491 .regs = &tegra186_ahci_regs, 492 }; 493 494 static const struct of_device_id tegra_ahci_of_match[] = { 495 { 496 .compatible = "nvidia,tegra124-ahci", 497 .data = &tegra124_ahci_soc 498 }, 499 { 500 .compatible = "nvidia,tegra210-ahci", 501 .data = &tegra210_ahci_soc 502 }, 503 { 504 .compatible = "nvidia,tegra186-ahci", 505 .data = &tegra186_ahci_soc 506 }, 507 {} 508 }; 509 MODULE_DEVICE_TABLE(of, tegra_ahci_of_match); 510 511 static const struct scsi_host_template ahci_platform_sht = { 512 AHCI_SHT(DRV_NAME), 513 }; 514 515 static int tegra_ahci_probe(struct platform_device *pdev) 516 { 517 struct ahci_host_priv *hpriv; 518 struct tegra_ahci_priv *tegra; 519 struct resource *res; 520 int ret; 521 522 hpriv = ahci_platform_get_resources(pdev, 0); 523 if (IS_ERR(hpriv)) 524 return PTR_ERR(hpriv); 525 526 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); 527 if (!tegra) 528 return -ENOMEM; 529 530 hpriv->plat_data = tegra; 531 532 tegra->pdev = pdev; 533 tegra->soc = of_device_get_match_data(&pdev->dev); 534 535 tegra->sata_regs = devm_platform_ioremap_resource(pdev, 1); 536 if (IS_ERR(tegra->sata_regs)) 537 return PTR_ERR(tegra->sata_regs); 538 539 /* 540 * AUX registers is optional. 541 */ 542 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 543 if (res) { 544 tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res); 545 if (IS_ERR(tegra->sata_aux_regs)) 546 return PTR_ERR(tegra->sata_aux_regs); 547 } 548 549 tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata"); 550 if (IS_ERR(tegra->sata_rst)) { 551 dev_err(&pdev->dev, "Failed to get sata reset\n"); 552 return PTR_ERR(tegra->sata_rst); 553 } 554 555 if (tegra->soc->has_sata_oob_rst) { 556 tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, 557 "sata-oob"); 558 if (IS_ERR(tegra->sata_oob_rst)) { 559 dev_err(&pdev->dev, "Failed to get sata-oob reset\n"); 560 return PTR_ERR(tegra->sata_oob_rst); 561 } 562 } 563 564 tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold"); 565 if (IS_ERR(tegra->sata_cold_rst)) { 566 dev_err(&pdev->dev, "Failed to get sata-cold reset\n"); 567 return PTR_ERR(tegra->sata_cold_rst); 568 } 569 570 tegra->sata_clk = devm_clk_get(&pdev->dev, "sata"); 571 if (IS_ERR(tegra->sata_clk)) { 572 dev_err(&pdev->dev, "Failed to get sata clock\n"); 573 return PTR_ERR(tegra->sata_clk); 574 } 575 576 tegra->pmc = devm_tegra_pmc_get(&pdev->dev); 577 if (IS_ERR(tegra->pmc)) 578 return dev_err_probe(&pdev->dev, PTR_ERR(tegra->pmc), 579 "failed to get PMC\n"); 580 581 tegra->supplies = devm_kcalloc(&pdev->dev, 582 tegra->soc->num_supplies, 583 sizeof(*tegra->supplies), GFP_KERNEL); 584 if (!tegra->supplies) 585 return -ENOMEM; 586 587 regulator_bulk_set_supply_names(tegra->supplies, 588 tegra->soc->supply_names, 589 tegra->soc->num_supplies); 590 591 ret = devm_regulator_bulk_get(&pdev->dev, 592 tegra->soc->num_supplies, 593 tegra->supplies); 594 if (ret) { 595 dev_err(&pdev->dev, "Failed to get regulators\n"); 596 return ret; 597 } 598 599 ret = tegra_ahci_controller_init(hpriv); 600 if (ret) 601 return ret; 602 603 ret = ahci_platform_init_host(pdev, hpriv, &ahci_tegra_port_info, 604 &ahci_platform_sht); 605 if (ret) 606 goto deinit_controller; 607 608 return 0; 609 610 deinit_controller: 611 tegra_ahci_controller_deinit(hpriv); 612 613 return ret; 614 }; 615 616 static struct platform_driver tegra_ahci_driver = { 617 .probe = tegra_ahci_probe, 618 .remove = ata_platform_remove_one, 619 .driver = { 620 .name = DRV_NAME, 621 .of_match_table = tegra_ahci_of_match, 622 }, 623 /* LP0 suspend support not implemented */ 624 }; 625 module_platform_driver(tegra_ahci_driver); 626 627 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>"); 628 MODULE_DESCRIPTION("Tegra AHCI SATA driver"); 629 MODULE_LICENSE("GPL v2"); 630