1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Allwinner sunxi AHCI SATA platform driver 4 * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl> 5 * Copyright 2014 Hans de Goede <hdegoede@redhat.com> 6 * 7 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov 8 * Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>, 9 * Daniel Wang <danielwang@allwinnertech.com> 10 */ 11 12 #include <linux/ahci_platform.h> 13 #include <linux/clk.h> 14 #include <linux/errno.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include "ahci.h" 20 21 #define DRV_NAME "ahci-sunxi" 22 23 /* Insmod parameters */ 24 static bool enable_pmp; 25 module_param(enable_pmp, bool, 0); 26 MODULE_PARM_DESC(enable_pmp, 27 "Enable support for sata port multipliers, only use if you use a pmp!"); 28 29 #define AHCI_BISTAFR 0x00a0 30 #define AHCI_BISTCR 0x00a4 31 #define AHCI_BISTFCTR 0x00a8 32 #define AHCI_BISTSR 0x00ac 33 #define AHCI_BISTDECR 0x00b0 34 #define AHCI_DIAGNR0 0x00b4 35 #define AHCI_DIAGNR1 0x00b8 36 #define AHCI_OOBR 0x00bc 37 #define AHCI_PHYCS0R 0x00c0 38 #define AHCI_PHYCS1R 0x00c4 39 #define AHCI_PHYCS2R 0x00c8 40 #define AHCI_TIMER1MS 0x00e0 41 #define AHCI_GPARAM1R 0x00e8 42 #define AHCI_GPARAM2R 0x00ec 43 #define AHCI_PPARAMR 0x00f0 44 #define AHCI_TESTR 0x00f4 45 #define AHCI_VERSIONR 0x00f8 46 #define AHCI_IDR 0x00fc 47 #define AHCI_RWCR 0x00fc 48 #define AHCI_P0DMACR 0x0170 49 #define AHCI_P0PHYCR 0x0178 50 #define AHCI_P0PHYSR 0x017c 51 52 static void sunxi_clrbits(void __iomem *reg, u32 clr_val) 53 { 54 u32 reg_val; 55 56 reg_val = readl(reg); 57 reg_val &= ~(clr_val); 58 writel(reg_val, reg); 59 } 60 61 static void sunxi_setbits(void __iomem *reg, u32 set_val) 62 { 63 u32 reg_val; 64 65 reg_val = readl(reg); 66 reg_val |= set_val; 67 writel(reg_val, reg); 68 } 69 70 static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val) 71 { 72 u32 reg_val; 73 74 reg_val = readl(reg); 75 reg_val &= ~(clr_val); 76 reg_val |= set_val; 77 writel(reg_val, reg); 78 } 79 80 static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift) 81 { 82 return (readl(reg) >> shift) & mask; 83 } 84 85 static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) 86 { 87 u32 reg_val; 88 int timeout; 89 90 /* This magic is from the original code */ 91 writel(0, reg_base + AHCI_RWCR); 92 msleep(5); 93 94 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); 95 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, 96 (0x7 << 24), 97 (0x5 << 24) | BIT(23) | BIT(18)); 98 sunxi_clrsetbits(reg_base + AHCI_PHYCS1R, 99 (0x3 << 16) | (0x1f << 8) | (0x3 << 6), 100 (0x2 << 16) | (0x6 << 8) | (0x2 << 6)); 101 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); 102 sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); 103 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, 104 (0x7 << 20), (0x3 << 20)); 105 sunxi_clrsetbits(reg_base + AHCI_PHYCS2R, 106 (0x1f << 5), (0x19 << 5)); 107 msleep(5); 108 109 sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19)); 110 111 timeout = 250; /* Power up takes aprox 50 us */ 112 do { 113 reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28); 114 if (reg_val == 0x02) 115 break; 116 117 if (--timeout == 0) { 118 dev_err(dev, "PHY power up failed.\n"); 119 return -EIO; 120 } 121 udelay(1); 122 } while (1); 123 124 sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24)); 125 126 timeout = 100; /* Calibration takes aprox 10 us */ 127 do { 128 reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24); 129 if (reg_val == 0x00) 130 break; 131 132 if (--timeout == 0) { 133 dev_err(dev, "PHY calibration failed.\n"); 134 return -EIO; 135 } 136 udelay(1); 137 } while (1); 138 139 msleep(15); 140 141 writel(0x7, reg_base + AHCI_RWCR); 142 143 return 0; 144 } 145 146 static void ahci_sunxi_start_engine(struct ata_port *ap) 147 { 148 void __iomem *port_mmio = ahci_port_base(ap); 149 struct ahci_host_priv *hpriv = ap->host->private_data; 150 151 /* Setup DMA before DMA start 152 * 153 * NOTE: A similar SoC with SATA/AHCI by Texas Instruments documents 154 * this Vendor Specific Port (P0DMACR, aka PxDMACR) in its 155 * User's Guide document (TMS320C674x/OMAP-L1x Processor 156 * Serial ATA (SATA) Controller, Literature Number: SPRUGJ8C, 157 * March 2011, Chapter 4.33 Port DMA Control Register (P0DMACR), 158 * p.68, https://www.ti.com/lit/ug/sprugj8c/sprugj8c.pdf) 159 * as equivalent to the following struct: 160 * 161 * struct AHCI_P0DMACR_t 162 * { 163 * unsigned TXTS : 4; 164 * unsigned RXTS : 4; 165 * unsigned TXABL : 4; 166 * unsigned RXABL : 4; 167 * unsigned Reserved : 16; 168 * }; 169 * 170 * TXTS: Transmit Transaction Size (TX_TRANSACTION_SIZE). 171 * This field defines the DMA transaction size in DWORDs for 172 * transmit (system bus read, device write) operation. [...] 173 * 174 * RXTS: Receive Transaction Size (RX_TRANSACTION_SIZE). 175 * This field defines the Port DMA transaction size in DWORDs 176 * for receive (system bus write, device read) operation. [...] 177 * 178 * TXABL: Transmit Burst Limit. 179 * This field allows software to limit the VBUSP master read 180 * burst size. [...] 181 * 182 * RXABL: Receive Burst Limit. 183 * Allows software to limit the VBUSP master write burst 184 * size. [...] 185 * 186 * Reserved: Reserved. 187 * 188 * 189 * NOTE: According to the above document, the following alternative 190 * to the code below could perhaps be a better option 191 * (or preparation) for possible further improvements later: 192 * sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff, 193 * 0x00000033); 194 */ 195 sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff, 0x00004433); 196 197 /* Start DMA */ 198 sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START); 199 } 200 201 static const struct ata_port_info ahci_sunxi_port_info = { 202 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ | ATA_FLAG_NO_DIPM, 203 .pio_mask = ATA_PIO4, 204 .udma_mask = ATA_UDMA6, 205 .port_ops = &ahci_platform_ops, 206 }; 207 208 static const struct scsi_host_template ahci_platform_sht = { 209 AHCI_SHT(DRV_NAME), 210 }; 211 212 static int ahci_sunxi_probe(struct platform_device *pdev) 213 { 214 struct device *dev = &pdev->dev; 215 struct ahci_host_priv *hpriv; 216 int rc; 217 218 hpriv = ahci_platform_get_resources(pdev, AHCI_PLATFORM_GET_RESETS); 219 if (IS_ERR(hpriv)) 220 return PTR_ERR(hpriv); 221 222 hpriv->start_engine = ahci_sunxi_start_engine; 223 224 rc = ahci_platform_enable_resources(hpriv); 225 if (rc) 226 return rc; 227 228 rc = ahci_sunxi_phy_init(dev, hpriv->mmio); 229 if (rc) 230 goto disable_resources; 231 232 hpriv->flags = AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI | 233 AHCI_HFLAG_YES_NCQ; 234 235 /* 236 * The sunxi sata controller seems to be unable to successfully do a 237 * soft reset if no pmp is attached, so disable pmp use unless 238 * requested, otherwise directly attached disks do not work. 239 */ 240 if (!enable_pmp) 241 hpriv->flags |= AHCI_HFLAG_NO_PMP; 242 243 rc = ahci_platform_init_host(pdev, hpriv, &ahci_sunxi_port_info, 244 &ahci_platform_sht); 245 if (rc) 246 goto disable_resources; 247 248 return 0; 249 250 disable_resources: 251 ahci_platform_disable_resources(hpriv); 252 return rc; 253 } 254 255 #ifdef CONFIG_PM_SLEEP 256 static int ahci_sunxi_resume(struct device *dev) 257 { 258 struct ata_host *host = dev_get_drvdata(dev); 259 struct ahci_host_priv *hpriv = host->private_data; 260 int rc; 261 262 rc = ahci_platform_enable_resources(hpriv); 263 if (rc) 264 return rc; 265 266 rc = ahci_sunxi_phy_init(dev, hpriv->mmio); 267 if (rc) 268 goto disable_resources; 269 270 rc = ahci_platform_resume_host(dev); 271 if (rc) 272 goto disable_resources; 273 274 return 0; 275 276 disable_resources: 277 ahci_platform_disable_resources(hpriv); 278 return rc; 279 } 280 #endif 281 282 static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend, 283 ahci_sunxi_resume); 284 285 static const struct of_device_id ahci_sunxi_of_match[] = { 286 { .compatible = "allwinner,sun4i-a10-ahci", }, 287 { .compatible = "allwinner,sun8i-r40-ahci", }, 288 { /* sentinel */ } 289 }; 290 MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match); 291 292 static struct platform_driver ahci_sunxi_driver = { 293 .probe = ahci_sunxi_probe, 294 .remove = ata_platform_remove_one, 295 .driver = { 296 .name = DRV_NAME, 297 .of_match_table = ahci_sunxi_of_match, 298 .pm = &ahci_sunxi_pm_ops, 299 }, 300 }; 301 module_platform_driver(ahci_sunxi_driver); 302 303 MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA driver"); 304 MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>"); 305 MODULE_LICENSE("GPL"); 306