1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * copyright (c) 2013 Freescale Semiconductor, Inc. 4 * Freescale IMX AHCI SATA platform driver 5 * 6 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 #include <linux/ahci_platform.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/of_device.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 18 #include <linux/libata.h> 19 #include <linux/hwmon.h> 20 #include <linux/hwmon-sysfs.h> 21 #include <linux/thermal.h> 22 #include "ahci.h" 23 24 #define DRV_NAME "ahci-imx" 25 26 enum { 27 /* Timer 1-ms Register */ 28 IMX_TIMER1MS = 0x00e0, 29 /* Port0 PHY Control Register */ 30 IMX_P0PHYCR = 0x0178, 31 IMX_P0PHYCR_TEST_PDDQ = 1 << 20, 32 IMX_P0PHYCR_CR_READ = 1 << 19, 33 IMX_P0PHYCR_CR_WRITE = 1 << 18, 34 IMX_P0PHYCR_CR_CAP_DATA = 1 << 17, 35 IMX_P0PHYCR_CR_CAP_ADDR = 1 << 16, 36 /* Port0 PHY Status Register */ 37 IMX_P0PHYSR = 0x017c, 38 IMX_P0PHYSR_CR_ACK = 1 << 18, 39 IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0, 40 /* Lane0 Output Status Register */ 41 IMX_LANE0_OUT_STAT = 0x2003, 42 IMX_LANE0_OUT_STAT_RX_PLL_STATE = 1 << 1, 43 /* Clock Reset Register */ 44 IMX_CLOCK_RESET = 0x7f3f, 45 IMX_CLOCK_RESET_RESET = 1 << 0, 46 /* IMX8QM HSIO AHCI definitions */ 47 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET = 0x03, 48 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET = 0x09, 49 IMX8QM_SATA_PHY_IMPED_RATIO_85OHM = 0x6c, 50 IMX8QM_LPCG_PHYX2_OFFSET = 0x00000, 51 IMX8QM_CSR_PHYX2_OFFSET = 0x90000, 52 IMX8QM_CSR_PHYX1_OFFSET = 0xa0000, 53 IMX8QM_CSR_PHYX_STTS0_OFFSET = 0x4, 54 IMX8QM_CSR_PCIEA_OFFSET = 0xb0000, 55 IMX8QM_CSR_PCIEB_OFFSET = 0xc0000, 56 IMX8QM_CSR_SATA_OFFSET = 0xd0000, 57 IMX8QM_CSR_PCIE_CTRL2_OFFSET = 0x8, 58 IMX8QM_CSR_MISC_OFFSET = 0xe0000, 59 60 IMX8QM_LPCG_PHYX2_PCLK0_MASK = (0x3 << 16), 61 IMX8QM_LPCG_PHYX2_PCLK1_MASK = (0x3 << 20), 62 IMX8QM_PHY_APB_RSTN_0 = BIT(0), 63 IMX8QM_PHY_MODE_SATA = BIT(19), 64 IMX8QM_PHY_MODE_MASK = (0xf << 17), 65 IMX8QM_PHY_PIPE_RSTN_0 = BIT(24), 66 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0 = BIT(25), 67 IMX8QM_PHY_PIPE_RSTN_1 = BIT(26), 68 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1 = BIT(27), 69 IMX8QM_STTS0_LANE0_TX_PLL_LOCK = BIT(4), 70 IMX8QM_MISC_IOB_RXENA = BIT(0), 71 IMX8QM_MISC_IOB_TXENA = BIT(1), 72 IMX8QM_MISC_PHYX1_EPCS_SEL = BIT(12), 73 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 = BIT(24), 74 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 = BIT(25), 75 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 = BIT(28), 76 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0 = BIT(29), 77 IMX8QM_SATA_CTRL_RESET_N = BIT(12), 78 IMX8QM_SATA_CTRL_EPCS_PHYRESET_N = BIT(7), 79 IMX8QM_CTRL_BUTTON_RST_N = BIT(21), 80 IMX8QM_CTRL_POWER_UP_RST_N = BIT(23), 81 IMX8QM_CTRL_LTSSM_ENABLE = BIT(4), 82 }; 83 84 enum ahci_imx_type { 85 AHCI_IMX53, 86 AHCI_IMX6Q, 87 AHCI_IMX6QP, 88 AHCI_IMX8QM, 89 }; 90 91 struct imx_ahci_priv { 92 struct platform_device *ahci_pdev; 93 enum ahci_imx_type type; 94 struct clk *sata_clk; 95 struct clk *sata_ref_clk; 96 struct clk *ahb_clk; 97 struct clk *epcs_tx_clk; 98 struct clk *epcs_rx_clk; 99 struct clk *phy_apbclk; 100 struct clk *phy_pclk0; 101 struct clk *phy_pclk1; 102 void __iomem *phy_base; 103 struct gpio_desc *clkreq_gpiod; 104 struct regmap *gpr; 105 bool no_device; 106 bool first_time; 107 u32 phy_params; 108 u32 imped_ratio; 109 }; 110 111 static int ahci_imx_hotplug; 112 module_param_named(hotplug, ahci_imx_hotplug, int, 0644); 113 MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)"); 114 115 static void ahci_imx_host_stop(struct ata_host *host); 116 117 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert) 118 { 119 int timeout = 10; 120 u32 crval; 121 u32 srval; 122 123 /* Assert or deassert the bit */ 124 crval = readl(mmio + IMX_P0PHYCR); 125 if (assert) 126 crval |= bit; 127 else 128 crval &= ~bit; 129 writel(crval, mmio + IMX_P0PHYCR); 130 131 /* Wait for the cr_ack signal */ 132 do { 133 srval = readl(mmio + IMX_P0PHYSR); 134 if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK) 135 break; 136 usleep_range(100, 200); 137 } while (--timeout); 138 139 return timeout ? 0 : -ETIMEDOUT; 140 } 141 142 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio) 143 { 144 u32 crval = addr; 145 int ret; 146 147 /* Supply the address on cr_data_in */ 148 writel(crval, mmio + IMX_P0PHYCR); 149 150 /* Assert the cr_cap_addr signal */ 151 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true); 152 if (ret) 153 return ret; 154 155 /* Deassert cr_cap_addr */ 156 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false); 157 if (ret) 158 return ret; 159 160 return 0; 161 } 162 163 static int imx_phy_reg_write(u16 val, void __iomem *mmio) 164 { 165 u32 crval = val; 166 int ret; 167 168 /* Supply the data on cr_data_in */ 169 writel(crval, mmio + IMX_P0PHYCR); 170 171 /* Assert the cr_cap_data signal */ 172 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true); 173 if (ret) 174 return ret; 175 176 /* Deassert cr_cap_data */ 177 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false); 178 if (ret) 179 return ret; 180 181 if (val & IMX_CLOCK_RESET_RESET) { 182 /* 183 * In case we're resetting the phy, it's unable to acknowledge, 184 * so we return immediately here. 185 */ 186 crval |= IMX_P0PHYCR_CR_WRITE; 187 writel(crval, mmio + IMX_P0PHYCR); 188 goto out; 189 } 190 191 /* Assert the cr_write signal */ 192 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true); 193 if (ret) 194 return ret; 195 196 /* Deassert cr_write */ 197 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false); 198 if (ret) 199 return ret; 200 201 out: 202 return 0; 203 } 204 205 static int imx_phy_reg_read(u16 *val, void __iomem *mmio) 206 { 207 int ret; 208 209 /* Assert the cr_read signal */ 210 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true); 211 if (ret) 212 return ret; 213 214 /* Capture the data from cr_data_out[] */ 215 *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT; 216 217 /* Deassert cr_read */ 218 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false); 219 if (ret) 220 return ret; 221 222 return 0; 223 } 224 225 static int imx_sata_phy_reset(struct ahci_host_priv *hpriv) 226 { 227 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 228 void __iomem *mmio = hpriv->mmio; 229 int timeout = 10; 230 u16 val; 231 int ret; 232 233 if (imxpriv->type == AHCI_IMX6QP) { 234 /* 6qp adds the sata reset mechanism, use it for 6qp sata */ 235 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, 236 IMX6Q_GPR5_SATA_SW_PD, 0); 237 238 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, 239 IMX6Q_GPR5_SATA_SW_RST, 0); 240 udelay(50); 241 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, 242 IMX6Q_GPR5_SATA_SW_RST, 243 IMX6Q_GPR5_SATA_SW_RST); 244 return 0; 245 } 246 247 /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */ 248 ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio); 249 if (ret) 250 return ret; 251 ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio); 252 if (ret) 253 return ret; 254 255 /* Wait for PHY RX_PLL to be stable */ 256 do { 257 usleep_range(100, 200); 258 ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio); 259 if (ret) 260 return ret; 261 ret = imx_phy_reg_read(&val, mmio); 262 if (ret) 263 return ret; 264 if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE) 265 break; 266 } while (--timeout); 267 268 return timeout ? 0 : -ETIMEDOUT; 269 } 270 271 enum { 272 /* SATA PHY Register */ 273 SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT = 0x0001, 274 SATA_PHY_CR_CLOCK_DAC_CTL = 0x0008, 275 SATA_PHY_CR_CLOCK_RTUNE_CTL = 0x0009, 276 SATA_PHY_CR_CLOCK_ADC_OUT = 0x000A, 277 SATA_PHY_CR_CLOCK_MPLL_TST = 0x0017, 278 }; 279 280 static int read_adc_sum(void *dev, u16 rtune_ctl_reg, void __iomem * mmio) 281 { 282 u16 adc_out_reg, read_sum; 283 u32 index, read_attempt; 284 const u32 attempt_limit = 200; 285 286 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio); 287 imx_phy_reg_write(rtune_ctl_reg, mmio); 288 289 /* two dummy read */ 290 index = 0; 291 read_attempt = 0; 292 adc_out_reg = 0; 293 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_ADC_OUT, mmio); 294 while (index < 2) { 295 imx_phy_reg_read(&adc_out_reg, mmio); 296 /* check if valid */ 297 if (adc_out_reg & 0x400) 298 index++; 299 300 read_attempt++; 301 if (read_attempt > attempt_limit) { 302 dev_err(dev, "Read REG more than %d times!\n", 303 attempt_limit); 304 break; 305 } 306 } 307 308 index = 0; 309 read_attempt = 0; 310 read_sum = 0; 311 while (index < 80) { 312 imx_phy_reg_read(&adc_out_reg, mmio); 313 if (adc_out_reg & 0x400) { 314 read_sum = read_sum + (adc_out_reg & 0x3FF); 315 index++; 316 } 317 read_attempt++; 318 if (read_attempt > attempt_limit) { 319 dev_err(dev, "Read REG more than %d times!\n", 320 attempt_limit); 321 break; 322 } 323 } 324 325 /* Use the U32 to make 1000 precision */ 326 return (read_sum * 1000) / 80; 327 } 328 329 /* SATA AHCI temperature monitor */ 330 static int __sata_ahci_read_temperature(void *dev, int *temp) 331 { 332 u16 mpll_test_reg, rtune_ctl_reg, dac_ctl_reg, read_sum; 333 u32 str1, str2, str3, str4; 334 int m1, m2, a; 335 struct ahci_host_priv *hpriv = dev_get_drvdata(dev); 336 void __iomem *mmio = hpriv->mmio; 337 338 /* check rd-wr to reg */ 339 read_sum = 0; 340 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio); 341 imx_phy_reg_write(read_sum, mmio); 342 imx_phy_reg_read(&read_sum, mmio); 343 if ((read_sum & 0xffff) != 0) 344 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum); 345 346 imx_phy_reg_write(0x5A5A, mmio); 347 imx_phy_reg_read(&read_sum, mmio); 348 if ((read_sum & 0xffff) != 0x5A5A) 349 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum); 350 351 imx_phy_reg_write(0x1234, mmio); 352 imx_phy_reg_read(&read_sum, mmio); 353 if ((read_sum & 0xffff) != 0x1234) 354 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum); 355 356 /* start temperature test */ 357 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio); 358 imx_phy_reg_read(&mpll_test_reg, mmio); 359 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio); 360 imx_phy_reg_read(&rtune_ctl_reg, mmio); 361 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio); 362 imx_phy_reg_read(&dac_ctl_reg, mmio); 363 364 /* mpll_tst.meas_iv ([12:2]) */ 365 str1 = (mpll_test_reg >> 2) & 0x7FF; 366 /* rtune_ctl.mode ([1:0]) */ 367 str2 = (rtune_ctl_reg) & 0x3; 368 /* dac_ctl.dac_mode ([14:12]) */ 369 str3 = (dac_ctl_reg >> 12) & 0x7; 370 /* rtune_ctl.sel_atbp ([4]) */ 371 str4 = (rtune_ctl_reg >> 4); 372 373 /* Calculate the m1 */ 374 /* mpll_tst.meas_iv */ 375 mpll_test_reg = (mpll_test_reg & 0xE03) | (512) << 2; 376 /* rtune_ctl.mode */ 377 rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (1); 378 /* dac_ctl.dac_mode */ 379 dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (4) << 12; 380 /* rtune_ctl.sel_atbp */ 381 rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (0) << 4; 382 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio); 383 imx_phy_reg_write(mpll_test_reg, mmio); 384 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio); 385 imx_phy_reg_write(dac_ctl_reg, mmio); 386 m1 = read_adc_sum(dev, rtune_ctl_reg, mmio); 387 388 /* Calculate the m2 */ 389 /* rtune_ctl.sel_atbp */ 390 rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (1) << 4; 391 m2 = read_adc_sum(dev, rtune_ctl_reg, mmio); 392 393 /* restore the status */ 394 /* mpll_tst.meas_iv */ 395 mpll_test_reg = (mpll_test_reg & 0xE03) | (str1) << 2; 396 /* rtune_ctl.mode */ 397 rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (str2); 398 /* dac_ctl.dac_mode */ 399 dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (str3) << 12; 400 /* rtune_ctl.sel_atbp */ 401 rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (str4) << 4; 402 403 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio); 404 imx_phy_reg_write(mpll_test_reg, mmio); 405 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio); 406 imx_phy_reg_write(dac_ctl_reg, mmio); 407 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio); 408 imx_phy_reg_write(rtune_ctl_reg, mmio); 409 410 /* Compute temperature */ 411 if (!(m2 / 1000)) 412 m2 = 1000; 413 a = (m2 - m1) / (m2/1000); 414 *temp = ((-559) * a * a) / 1000 + (1379) * a + (-458000); 415 416 return 0; 417 } 418 419 static int sata_ahci_read_temperature(struct thermal_zone_device *tz, int *temp) 420 { 421 return __sata_ahci_read_temperature(tz->devdata, temp); 422 } 423 424 static ssize_t sata_ahci_show_temp(struct device *dev, 425 struct device_attribute *da, 426 char *buf) 427 { 428 unsigned int temp = 0; 429 int err; 430 431 err = __sata_ahci_read_temperature(dev, &temp); 432 if (err < 0) 433 return err; 434 435 return sprintf(buf, "%u\n", temp); 436 } 437 438 static const struct thermal_zone_device_ops fsl_sata_ahci_of_thermal_ops = { 439 .get_temp = sata_ahci_read_temperature, 440 }; 441 442 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, sata_ahci_show_temp, NULL, 0); 443 444 static struct attribute *fsl_sata_ahci_attrs[] = { 445 &sensor_dev_attr_temp1_input.dev_attr.attr, 446 NULL 447 }; 448 ATTRIBUTE_GROUPS(fsl_sata_ahci); 449 450 static int imx8_sata_enable(struct ahci_host_priv *hpriv) 451 { 452 u32 val, reg; 453 int i, ret; 454 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 455 struct device *dev = &imxpriv->ahci_pdev->dev; 456 457 /* configure the hsio for sata */ 458 ret = clk_prepare_enable(imxpriv->phy_pclk0); 459 if (ret < 0) { 460 dev_err(dev, "can't enable phy_pclk0.\n"); 461 return ret; 462 } 463 ret = clk_prepare_enable(imxpriv->phy_pclk1); 464 if (ret < 0) { 465 dev_err(dev, "can't enable phy_pclk1.\n"); 466 goto disable_phy_pclk0; 467 } 468 ret = clk_prepare_enable(imxpriv->epcs_tx_clk); 469 if (ret < 0) { 470 dev_err(dev, "can't enable epcs_tx_clk.\n"); 471 goto disable_phy_pclk1; 472 } 473 ret = clk_prepare_enable(imxpriv->epcs_rx_clk); 474 if (ret < 0) { 475 dev_err(dev, "can't enable epcs_rx_clk.\n"); 476 goto disable_epcs_tx_clk; 477 } 478 ret = clk_prepare_enable(imxpriv->phy_apbclk); 479 if (ret < 0) { 480 dev_err(dev, "can't enable phy_apbclk.\n"); 481 goto disable_epcs_rx_clk; 482 } 483 /* Configure PHYx2 PIPE_RSTN */ 484 regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET + 485 IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val); 486 if ((val & IMX8QM_CTRL_LTSSM_ENABLE) == 0) { 487 /* The link of the PCIEA of HSIO is down */ 488 regmap_update_bits(imxpriv->gpr, 489 IMX8QM_CSR_PHYX2_OFFSET, 490 IMX8QM_PHY_PIPE_RSTN_0 | 491 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0, 492 IMX8QM_PHY_PIPE_RSTN_0 | 493 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0); 494 } 495 regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEB_OFFSET + 496 IMX8QM_CSR_PCIE_CTRL2_OFFSET, ®); 497 if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) == 0) { 498 /* The link of the PCIEB of HSIO is down */ 499 regmap_update_bits(imxpriv->gpr, 500 IMX8QM_CSR_PHYX2_OFFSET, 501 IMX8QM_PHY_PIPE_RSTN_1 | 502 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1, 503 IMX8QM_PHY_PIPE_RSTN_1 | 504 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1); 505 } 506 if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) { 507 /* The links of both PCIA and PCIEB of HSIO are down */ 508 regmap_update_bits(imxpriv->gpr, 509 IMX8QM_LPCG_PHYX2_OFFSET, 510 IMX8QM_LPCG_PHYX2_PCLK0_MASK | 511 IMX8QM_LPCG_PHYX2_PCLK1_MASK, 512 0); 513 } 514 515 /* set PWR_RST and BT_RST of csr_pciea */ 516 val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET; 517 regmap_update_bits(imxpriv->gpr, 518 val, 519 IMX8QM_CTRL_BUTTON_RST_N, 520 IMX8QM_CTRL_BUTTON_RST_N); 521 regmap_update_bits(imxpriv->gpr, 522 val, 523 IMX8QM_CTRL_POWER_UP_RST_N, 524 IMX8QM_CTRL_POWER_UP_RST_N); 525 526 /* PHYX1_MODE to SATA */ 527 regmap_update_bits(imxpriv->gpr, 528 IMX8QM_CSR_PHYX1_OFFSET, 529 IMX8QM_PHY_MODE_MASK, 530 IMX8QM_PHY_MODE_SATA); 531 532 /* 533 * BIT0 RXENA 1, BIT1 TXENA 0 534 * BIT12 PHY_X1_EPCS_SEL 1. 535 */ 536 regmap_update_bits(imxpriv->gpr, 537 IMX8QM_CSR_MISC_OFFSET, 538 IMX8QM_MISC_IOB_RXENA, 539 IMX8QM_MISC_IOB_RXENA); 540 regmap_update_bits(imxpriv->gpr, 541 IMX8QM_CSR_MISC_OFFSET, 542 IMX8QM_MISC_IOB_TXENA, 543 0); 544 regmap_update_bits(imxpriv->gpr, 545 IMX8QM_CSR_MISC_OFFSET, 546 IMX8QM_MISC_PHYX1_EPCS_SEL, 547 IMX8QM_MISC_PHYX1_EPCS_SEL); 548 /* 549 * It is possible, for PCIe and SATA are sharing 550 * the same clock source, HPLL or external oscillator. 551 * When PCIe is in low power modes (L1.X or L2 etc), 552 * the clock source can be turned off. In this case, 553 * if this clock source is required to be toggling by 554 * SATA, then SATA functions will be abnormal. 555 * Set the override here to avoid it. 556 */ 557 regmap_update_bits(imxpriv->gpr, 558 IMX8QM_CSR_MISC_OFFSET, 559 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 | 560 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 | 561 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 | 562 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0, 563 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 | 564 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 | 565 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 | 566 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0); 567 568 /* clear PHY RST, then set it */ 569 regmap_update_bits(imxpriv->gpr, 570 IMX8QM_CSR_SATA_OFFSET, 571 IMX8QM_SATA_CTRL_EPCS_PHYRESET_N, 572 0); 573 574 regmap_update_bits(imxpriv->gpr, 575 IMX8QM_CSR_SATA_OFFSET, 576 IMX8QM_SATA_CTRL_EPCS_PHYRESET_N, 577 IMX8QM_SATA_CTRL_EPCS_PHYRESET_N); 578 579 /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */ 580 regmap_update_bits(imxpriv->gpr, 581 IMX8QM_CSR_SATA_OFFSET, 582 IMX8QM_SATA_CTRL_RESET_N, 583 IMX8QM_SATA_CTRL_RESET_N); 584 udelay(1); 585 regmap_update_bits(imxpriv->gpr, 586 IMX8QM_CSR_SATA_OFFSET, 587 IMX8QM_SATA_CTRL_RESET_N, 588 0); 589 regmap_update_bits(imxpriv->gpr, 590 IMX8QM_CSR_SATA_OFFSET, 591 IMX8QM_SATA_CTRL_RESET_N, 592 IMX8QM_SATA_CTRL_RESET_N); 593 594 /* APB reset */ 595 regmap_update_bits(imxpriv->gpr, 596 IMX8QM_CSR_PHYX1_OFFSET, 597 IMX8QM_PHY_APB_RSTN_0, 598 IMX8QM_PHY_APB_RSTN_0); 599 600 for (i = 0; i < 100; i++) { 601 reg = IMX8QM_CSR_PHYX1_OFFSET + 602 IMX8QM_CSR_PHYX_STTS0_OFFSET; 603 regmap_read(imxpriv->gpr, reg, &val); 604 val &= IMX8QM_STTS0_LANE0_TX_PLL_LOCK; 605 if (val == IMX8QM_STTS0_LANE0_TX_PLL_LOCK) 606 break; 607 udelay(1); 608 } 609 610 if (val != IMX8QM_STTS0_LANE0_TX_PLL_LOCK) { 611 dev_err(dev, "TX PLL of the PHY is not locked\n"); 612 ret = -ENODEV; 613 } else { 614 writeb(imxpriv->imped_ratio, imxpriv->phy_base + 615 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET); 616 writeb(imxpriv->imped_ratio, imxpriv->phy_base + 617 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET); 618 reg = readb(imxpriv->phy_base + 619 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET); 620 if (unlikely(reg != imxpriv->imped_ratio)) 621 dev_info(dev, "Can't set PHY RX impedance ratio.\n"); 622 reg = readb(imxpriv->phy_base + 623 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET); 624 if (unlikely(reg != imxpriv->imped_ratio)) 625 dev_info(dev, "Can't set PHY TX impedance ratio.\n"); 626 usleep_range(50, 100); 627 628 /* 629 * To reduce the power consumption, gate off 630 * the PHY clks 631 */ 632 clk_disable_unprepare(imxpriv->phy_apbclk); 633 clk_disable_unprepare(imxpriv->phy_pclk1); 634 clk_disable_unprepare(imxpriv->phy_pclk0); 635 return ret; 636 } 637 638 clk_disable_unprepare(imxpriv->phy_apbclk); 639 disable_epcs_rx_clk: 640 clk_disable_unprepare(imxpriv->epcs_rx_clk); 641 disable_epcs_tx_clk: 642 clk_disable_unprepare(imxpriv->epcs_tx_clk); 643 disable_phy_pclk1: 644 clk_disable_unprepare(imxpriv->phy_pclk1); 645 disable_phy_pclk0: 646 clk_disable_unprepare(imxpriv->phy_pclk0); 647 648 return ret; 649 } 650 651 static int imx_sata_enable(struct ahci_host_priv *hpriv) 652 { 653 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 654 struct device *dev = &imxpriv->ahci_pdev->dev; 655 int ret; 656 657 if (imxpriv->no_device) 658 return 0; 659 660 ret = ahci_platform_enable_regulators(hpriv); 661 if (ret) 662 return ret; 663 664 ret = clk_prepare_enable(imxpriv->sata_ref_clk); 665 if (ret < 0) 666 goto disable_regulator; 667 668 if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { 669 /* 670 * set PHY Paremeters, two steps to configure the GPR13, 671 * one write for rest of parameters, mask of first write 672 * is 0x07ffffff, and the other one write for setting 673 * the mpll_clk_en. 674 */ 675 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 676 IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK | 677 IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK | 678 IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK | 679 IMX6Q_GPR13_SATA_SPD_MODE_MASK | 680 IMX6Q_GPR13_SATA_MPLL_SS_EN | 681 IMX6Q_GPR13_SATA_TX_ATTEN_MASK | 682 IMX6Q_GPR13_SATA_TX_BOOST_MASK | 683 IMX6Q_GPR13_SATA_TX_LVL_MASK | 684 IMX6Q_GPR13_SATA_MPLL_CLK_EN | 685 IMX6Q_GPR13_SATA_TX_EDGE_RATE, 686 imxpriv->phy_params); 687 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 688 IMX6Q_GPR13_SATA_MPLL_CLK_EN, 689 IMX6Q_GPR13_SATA_MPLL_CLK_EN); 690 691 usleep_range(100, 200); 692 693 ret = imx_sata_phy_reset(hpriv); 694 if (ret) { 695 dev_err(dev, "failed to reset phy: %d\n", ret); 696 goto disable_clk; 697 } 698 } else if (imxpriv->type == AHCI_IMX8QM) { 699 ret = imx8_sata_enable(hpriv); 700 } 701 702 usleep_range(1000, 2000); 703 704 return 0; 705 706 disable_clk: 707 clk_disable_unprepare(imxpriv->sata_ref_clk); 708 disable_regulator: 709 ahci_platform_disable_regulators(hpriv); 710 711 return ret; 712 } 713 714 static void imx_sata_disable(struct ahci_host_priv *hpriv) 715 { 716 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 717 718 if (imxpriv->no_device) 719 return; 720 721 switch (imxpriv->type) { 722 case AHCI_IMX6QP: 723 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, 724 IMX6Q_GPR5_SATA_SW_PD, 725 IMX6Q_GPR5_SATA_SW_PD); 726 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 727 IMX6Q_GPR13_SATA_MPLL_CLK_EN, 728 !IMX6Q_GPR13_SATA_MPLL_CLK_EN); 729 break; 730 731 case AHCI_IMX6Q: 732 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 733 IMX6Q_GPR13_SATA_MPLL_CLK_EN, 734 !IMX6Q_GPR13_SATA_MPLL_CLK_EN); 735 break; 736 737 case AHCI_IMX8QM: 738 clk_disable_unprepare(imxpriv->epcs_rx_clk); 739 clk_disable_unprepare(imxpriv->epcs_tx_clk); 740 break; 741 742 default: 743 break; 744 } 745 746 clk_disable_unprepare(imxpriv->sata_ref_clk); 747 748 ahci_platform_disable_regulators(hpriv); 749 } 750 751 static void ahci_imx_error_handler(struct ata_port *ap) 752 { 753 u32 reg_val; 754 struct ata_device *dev; 755 struct ata_host *host = dev_get_drvdata(ap->dev); 756 struct ahci_host_priv *hpriv = host->private_data; 757 void __iomem *mmio = hpriv->mmio; 758 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 759 760 ahci_error_handler(ap); 761 762 if (!(imxpriv->first_time) || ahci_imx_hotplug) 763 return; 764 765 imxpriv->first_time = false; 766 767 ata_for_each_dev(dev, &ap->link, ENABLED) 768 return; 769 /* 770 * Disable link to save power. An imx ahci port can't be recovered 771 * without full reset once the pddq mode is enabled making it 772 * impossible to use as part of libata LPM. 773 */ 774 reg_val = readl(mmio + IMX_P0PHYCR); 775 writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR); 776 imx_sata_disable(hpriv); 777 imxpriv->no_device = true; 778 779 dev_info(ap->dev, "no device found, disabling link.\n"); 780 dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n"); 781 } 782 783 static int ahci_imx_softreset(struct ata_link *link, unsigned int *class, 784 unsigned long deadline) 785 { 786 struct ata_port *ap = link->ap; 787 struct ata_host *host = dev_get_drvdata(ap->dev); 788 struct ahci_host_priv *hpriv = host->private_data; 789 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 790 int ret; 791 792 if (imxpriv->type == AHCI_IMX53) 793 ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline); 794 else 795 ret = ahci_ops.softreset(link, class, deadline); 796 797 return ret; 798 } 799 800 static struct ata_port_operations ahci_imx_ops = { 801 .inherits = &ahci_ops, 802 .host_stop = ahci_imx_host_stop, 803 .error_handler = ahci_imx_error_handler, 804 .softreset = ahci_imx_softreset, 805 }; 806 807 static const struct ata_port_info ahci_imx_port_info = { 808 .flags = AHCI_FLAG_COMMON, 809 .pio_mask = ATA_PIO4, 810 .udma_mask = ATA_UDMA6, 811 .port_ops = &ahci_imx_ops, 812 }; 813 814 static const struct of_device_id imx_ahci_of_match[] = { 815 { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 }, 816 { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q }, 817 { .compatible = "fsl,imx6qp-ahci", .data = (void *)AHCI_IMX6QP }, 818 { .compatible = "fsl,imx8qm-ahci", .data = (void *)AHCI_IMX8QM }, 819 { /* sentinel */ } 820 }; 821 MODULE_DEVICE_TABLE(of, imx_ahci_of_match); 822 823 struct reg_value { 824 u32 of_value; 825 u32 reg_value; 826 }; 827 828 struct reg_property { 829 const char *name; 830 const struct reg_value *values; 831 size_t num_values; 832 u32 def_value; 833 u32 set_value; 834 }; 835 836 static const struct reg_value gpr13_tx_level[] = { 837 { 937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V }, 838 { 947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V }, 839 { 957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V }, 840 { 966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V }, 841 { 976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V }, 842 { 986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V }, 843 { 996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V }, 844 { 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V }, 845 { 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V }, 846 { 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V }, 847 { 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V }, 848 { 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V }, 849 { 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V }, 850 { 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V }, 851 { 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V }, 852 { 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V }, 853 { 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V }, 854 { 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V }, 855 { 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V }, 856 { 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V }, 857 { 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V }, 858 { 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V }, 859 { 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V }, 860 { 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V }, 861 { 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V }, 862 { 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V }, 863 { 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V }, 864 { 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V }, 865 { 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V }, 866 { 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V }, 867 { 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V }, 868 { 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V } 869 }; 870 871 static const struct reg_value gpr13_tx_boost[] = { 872 { 0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB }, 873 { 370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB }, 874 { 740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB }, 875 { 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB }, 876 { 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB }, 877 { 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB }, 878 { 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB }, 879 { 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB }, 880 { 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB }, 881 { 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB }, 882 { 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB }, 883 { 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB }, 884 { 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB }, 885 { 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB }, 886 { 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB }, 887 { 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB } 888 }; 889 890 static const struct reg_value gpr13_tx_atten[] = { 891 { 8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 }, 892 { 9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 }, 893 { 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 }, 894 { 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 }, 895 { 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 }, 896 { 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 }, 897 }; 898 899 static const struct reg_value gpr13_rx_eq[] = { 900 { 500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB }, 901 { 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB }, 902 { 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB }, 903 { 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB }, 904 { 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB }, 905 { 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB }, 906 { 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB }, 907 { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB }, 908 }; 909 910 static const struct reg_property gpr13_props[] = { 911 { 912 .name = "fsl,transmit-level-mV", 913 .values = gpr13_tx_level, 914 .num_values = ARRAY_SIZE(gpr13_tx_level), 915 .def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V, 916 }, { 917 .name = "fsl,transmit-boost-mdB", 918 .values = gpr13_tx_boost, 919 .num_values = ARRAY_SIZE(gpr13_tx_boost), 920 .def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB, 921 }, { 922 .name = "fsl,transmit-atten-16ths", 923 .values = gpr13_tx_atten, 924 .num_values = ARRAY_SIZE(gpr13_tx_atten), 925 .def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16, 926 }, { 927 .name = "fsl,receive-eq-mdB", 928 .values = gpr13_rx_eq, 929 .num_values = ARRAY_SIZE(gpr13_rx_eq), 930 .def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB, 931 }, { 932 .name = "fsl,no-spread-spectrum", 933 .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN, 934 .set_value = 0, 935 }, 936 }; 937 938 static u32 imx_ahci_parse_props(struct device *dev, 939 const struct reg_property *prop, size_t num) 940 { 941 struct device_node *np = dev->of_node; 942 u32 reg_value = 0; 943 int i, j; 944 945 for (i = 0; i < num; i++, prop++) { 946 u32 of_val; 947 948 if (prop->num_values == 0) { 949 if (of_property_read_bool(np, prop->name)) 950 reg_value |= prop->set_value; 951 else 952 reg_value |= prop->def_value; 953 continue; 954 } 955 956 if (of_property_read_u32(np, prop->name, &of_val)) { 957 dev_info(dev, "%s not specified, using %08x\n", 958 prop->name, prop->def_value); 959 reg_value |= prop->def_value; 960 continue; 961 } 962 963 for (j = 0; j < prop->num_values; j++) { 964 if (prop->values[j].of_value == of_val) { 965 dev_info(dev, "%s value %u, using %08x\n", 966 prop->name, of_val, prop->values[j].reg_value); 967 reg_value |= prop->values[j].reg_value; 968 break; 969 } 970 } 971 972 if (j == prop->num_values) { 973 dev_err(dev, "DT property %s is not a valid value\n", 974 prop->name); 975 reg_value |= prop->def_value; 976 } 977 } 978 979 return reg_value; 980 } 981 982 static struct scsi_host_template ahci_platform_sht = { 983 AHCI_SHT(DRV_NAME), 984 }; 985 986 static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv) 987 { 988 struct resource *phy_res; 989 struct platform_device *pdev = imxpriv->ahci_pdev; 990 struct device_node *np = dev->of_node; 991 992 if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio)) 993 imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM; 994 phy_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 995 if (phy_res) { 996 imxpriv->phy_base = devm_ioremap(dev, phy_res->start, 997 resource_size(phy_res)); 998 if (!imxpriv->phy_base) { 999 dev_err(dev, "error with ioremap\n"); 1000 return -ENOMEM; 1001 } 1002 } else { 1003 dev_err(dev, "missing *phy* reg region.\n"); 1004 return -ENOMEM; 1005 } 1006 imxpriv->gpr = 1007 syscon_regmap_lookup_by_phandle(np, "hsio"); 1008 if (IS_ERR(imxpriv->gpr)) { 1009 dev_err(dev, "unable to find gpr registers\n"); 1010 return PTR_ERR(imxpriv->gpr); 1011 } 1012 1013 imxpriv->epcs_tx_clk = devm_clk_get(dev, "epcs_tx"); 1014 if (IS_ERR(imxpriv->epcs_tx_clk)) { 1015 dev_err(dev, "can't get epcs_tx_clk clock.\n"); 1016 return PTR_ERR(imxpriv->epcs_tx_clk); 1017 } 1018 imxpriv->epcs_rx_clk = devm_clk_get(dev, "epcs_rx"); 1019 if (IS_ERR(imxpriv->epcs_rx_clk)) { 1020 dev_err(dev, "can't get epcs_rx_clk clock.\n"); 1021 return PTR_ERR(imxpriv->epcs_rx_clk); 1022 } 1023 imxpriv->phy_pclk0 = devm_clk_get(dev, "phy_pclk0"); 1024 if (IS_ERR(imxpriv->phy_pclk0)) { 1025 dev_err(dev, "can't get phy_pclk0 clock.\n"); 1026 return PTR_ERR(imxpriv->phy_pclk0); 1027 } 1028 imxpriv->phy_pclk1 = devm_clk_get(dev, "phy_pclk1"); 1029 if (IS_ERR(imxpriv->phy_pclk1)) { 1030 dev_err(dev, "can't get phy_pclk1 clock.\n"); 1031 return PTR_ERR(imxpriv->phy_pclk1); 1032 } 1033 imxpriv->phy_apbclk = devm_clk_get(dev, "phy_apbclk"); 1034 if (IS_ERR(imxpriv->phy_apbclk)) { 1035 dev_err(dev, "can't get phy_apbclk clock.\n"); 1036 return PTR_ERR(imxpriv->phy_apbclk); 1037 } 1038 1039 /* Fetch GPIO, then enable the external OSC */ 1040 imxpriv->clkreq_gpiod = devm_gpiod_get_optional(dev, "clkreq", 1041 GPIOD_OUT_LOW | GPIOD_FLAGS_BIT_NONEXCLUSIVE); 1042 if (IS_ERR(imxpriv->clkreq_gpiod)) 1043 return PTR_ERR(imxpriv->clkreq_gpiod); 1044 if (imxpriv->clkreq_gpiod) 1045 gpiod_set_consumer_name(imxpriv->clkreq_gpiod, "SATA CLKREQ"); 1046 1047 return 0; 1048 } 1049 1050 static int imx_ahci_probe(struct platform_device *pdev) 1051 { 1052 struct device *dev = &pdev->dev; 1053 const struct of_device_id *of_id; 1054 struct ahci_host_priv *hpriv; 1055 struct imx_ahci_priv *imxpriv; 1056 unsigned int reg_val; 1057 int ret; 1058 1059 of_id = of_match_device(imx_ahci_of_match, dev); 1060 if (!of_id) 1061 return -EINVAL; 1062 1063 imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL); 1064 if (!imxpriv) 1065 return -ENOMEM; 1066 1067 imxpriv->ahci_pdev = pdev; 1068 imxpriv->no_device = false; 1069 imxpriv->first_time = true; 1070 imxpriv->type = (unsigned long)of_id->data; 1071 1072 imxpriv->sata_clk = devm_clk_get(dev, "sata"); 1073 if (IS_ERR(imxpriv->sata_clk)) { 1074 dev_err(dev, "can't get sata clock.\n"); 1075 return PTR_ERR(imxpriv->sata_clk); 1076 } 1077 1078 imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref"); 1079 if (IS_ERR(imxpriv->sata_ref_clk)) { 1080 dev_err(dev, "can't get sata_ref clock.\n"); 1081 return PTR_ERR(imxpriv->sata_ref_clk); 1082 } 1083 1084 imxpriv->ahb_clk = devm_clk_get(dev, "ahb"); 1085 if (IS_ERR(imxpriv->ahb_clk)) { 1086 dev_err(dev, "can't get ahb clock.\n"); 1087 return PTR_ERR(imxpriv->ahb_clk); 1088 } 1089 1090 if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { 1091 u32 reg_value; 1092 1093 imxpriv->gpr = syscon_regmap_lookup_by_compatible( 1094 "fsl,imx6q-iomuxc-gpr"); 1095 if (IS_ERR(imxpriv->gpr)) { 1096 dev_err(dev, 1097 "failed to find fsl,imx6q-iomux-gpr regmap\n"); 1098 return PTR_ERR(imxpriv->gpr); 1099 } 1100 1101 reg_value = imx_ahci_parse_props(dev, gpr13_props, 1102 ARRAY_SIZE(gpr13_props)); 1103 1104 imxpriv->phy_params = 1105 IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M | 1106 IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F | 1107 IMX6Q_GPR13_SATA_SPD_MODE_3P0G | 1108 reg_value; 1109 } else if (imxpriv->type == AHCI_IMX8QM) { 1110 ret = imx8_sata_probe(dev, imxpriv); 1111 if (ret) 1112 return ret; 1113 } 1114 1115 hpriv = ahci_platform_get_resources(pdev, 0); 1116 if (IS_ERR(hpriv)) 1117 return PTR_ERR(hpriv); 1118 1119 hpriv->plat_data = imxpriv; 1120 1121 ret = clk_prepare_enable(imxpriv->sata_clk); 1122 if (ret) 1123 return ret; 1124 1125 if (imxpriv->type == AHCI_IMX53 && 1126 IS_ENABLED(CONFIG_HWMON)) { 1127 /* Add the temperature monitor */ 1128 struct device *hwmon_dev; 1129 1130 hwmon_dev = 1131 devm_hwmon_device_register_with_groups(dev, 1132 "sata_ahci", 1133 hpriv, 1134 fsl_sata_ahci_groups); 1135 if (IS_ERR(hwmon_dev)) { 1136 ret = PTR_ERR(hwmon_dev); 1137 goto disable_clk; 1138 } 1139 devm_thermal_of_zone_register(hwmon_dev, 0, hwmon_dev, 1140 &fsl_sata_ahci_of_thermal_ops); 1141 dev_info(dev, "%s: sensor 'sata_ahci'\n", dev_name(hwmon_dev)); 1142 } 1143 1144 ret = imx_sata_enable(hpriv); 1145 if (ret) 1146 goto disable_clk; 1147 1148 /* 1149 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL, 1150 * and IP vendor specific register IMX_TIMER1MS. 1151 * Configure CAP_SSS (support stagered spin up). 1152 * Implement the port0. 1153 * Get the ahb clock rate, and configure the TIMER1MS register. 1154 */ 1155 reg_val = readl(hpriv->mmio + HOST_CAP); 1156 if (!(reg_val & HOST_CAP_SSS)) { 1157 reg_val |= HOST_CAP_SSS; 1158 writel(reg_val, hpriv->mmio + HOST_CAP); 1159 } 1160 reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL); 1161 if (!(reg_val & 0x1)) { 1162 reg_val |= 0x1; 1163 writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL); 1164 } 1165 1166 reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000; 1167 writel(reg_val, hpriv->mmio + IMX_TIMER1MS); 1168 1169 ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 1170 &ahci_platform_sht); 1171 if (ret) 1172 goto disable_sata; 1173 1174 return 0; 1175 1176 disable_sata: 1177 imx_sata_disable(hpriv); 1178 disable_clk: 1179 clk_disable_unprepare(imxpriv->sata_clk); 1180 return ret; 1181 } 1182 1183 static void ahci_imx_host_stop(struct ata_host *host) 1184 { 1185 struct ahci_host_priv *hpriv = host->private_data; 1186 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 1187 1188 imx_sata_disable(hpriv); 1189 clk_disable_unprepare(imxpriv->sata_clk); 1190 } 1191 1192 #ifdef CONFIG_PM_SLEEP 1193 static int imx_ahci_suspend(struct device *dev) 1194 { 1195 struct ata_host *host = dev_get_drvdata(dev); 1196 struct ahci_host_priv *hpriv = host->private_data; 1197 int ret; 1198 1199 ret = ahci_platform_suspend_host(dev); 1200 if (ret) 1201 return ret; 1202 1203 imx_sata_disable(hpriv); 1204 1205 return 0; 1206 } 1207 1208 static int imx_ahci_resume(struct device *dev) 1209 { 1210 struct ata_host *host = dev_get_drvdata(dev); 1211 struct ahci_host_priv *hpriv = host->private_data; 1212 int ret; 1213 1214 ret = imx_sata_enable(hpriv); 1215 if (ret) 1216 return ret; 1217 1218 return ahci_platform_resume_host(dev); 1219 } 1220 #endif 1221 1222 static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume); 1223 1224 static struct platform_driver imx_ahci_driver = { 1225 .probe = imx_ahci_probe, 1226 .remove = ata_platform_remove_one, 1227 .driver = { 1228 .name = DRV_NAME, 1229 .of_match_table = imx_ahci_of_match, 1230 .pm = &ahci_imx_pm_ops, 1231 }, 1232 }; 1233 module_platform_driver(imx_ahci_driver); 1234 1235 MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver"); 1236 MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>"); 1237 MODULE_LICENSE("GPL"); 1238 MODULE_ALIAS("platform:" DRV_NAME); 1239