1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom SATA3 AHCI Controller Driver 4 * 5 * Copyright © 2009-2015 Broadcom Corporation 6 */ 7 8 #include <linux/ahci_platform.h> 9 #include <linux/compiler.h> 10 #include <linux/device.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/libata.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/reset.h> 20 #include <linux/string.h> 21 22 #include "ahci.h" 23 24 #define DRV_NAME "brcm-ahci" 25 26 #define SATA_TOP_CTRL_VERSION 0x0 27 #define SATA_TOP_CTRL_BUS_CTRL 0x4 28 #define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */ 29 #define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */ 30 #define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */ 31 #define PIODATA_ENDIAN_SHIFT 6 32 #define ENDIAN_SWAP_NONE 0 33 #define ENDIAN_SWAP_FULL 2 34 #define SATA_TOP_CTRL_TP_CTRL 0x8 35 #define SATA_TOP_CTRL_PHY_CTRL 0xc 36 #define SATA_TOP_CTRL_PHY_CTRL_1 0x0 37 #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14) 38 #define SATA_TOP_CTRL_PHY_CTRL_2 0x4 39 #define SATA_TOP_CTRL_2_SW_RST_MDIOREG BIT(0) 40 #define SATA_TOP_CTRL_2_SW_RST_OOB BIT(1) 41 #define SATA_TOP_CTRL_2_SW_RST_RX BIT(2) 42 #define SATA_TOP_CTRL_2_SW_RST_TX BIT(3) 43 #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14) 44 #define SATA_TOP_CTRL_PHY_OFFS 0x8 45 #define SATA_TOP_MAX_PHYS 2 46 47 #define SATA_FIRST_PORT_CTRL 0x700 48 #define SATA_NEXT_PORT_CTRL_OFFSET 0x80 49 #define SATA_PORT_PCTRL6(reg_base) (reg_base + 0x18) 50 51 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */ 52 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN) 53 #define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */ 54 #define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */ 55 #else 56 #define DATA_ENDIAN 0 57 #define MMIO_ENDIAN 0 58 #endif 59 60 #define BUS_CTRL_ENDIAN_CONF \ 61 ((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) | \ 62 (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) | \ 63 (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT)) 64 65 #define BUS_CTRL_ENDIAN_NSP_CONF \ 66 (0x02 << DMADATA_ENDIAN_SHIFT | 0x02 << DMADESC_ENDIAN_SHIFT) 67 68 #define BUS_CTRL_ENDIAN_CONF_MASK \ 69 (0x3 << MMIO_ENDIAN_SHIFT | 0x3 << DMADESC_ENDIAN_SHIFT | \ 70 0x3 << DMADATA_ENDIAN_SHIFT | 0x3 << PIODATA_ENDIAN_SHIFT) 71 72 enum brcm_ahci_version { 73 BRCM_SATA_BCM7425 = 1, 74 BRCM_SATA_BCM7445, 75 BRCM_SATA_NSP, 76 BRCM_SATA_BCM7216, 77 }; 78 79 enum brcm_ahci_quirks { 80 BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(0), 81 }; 82 83 struct brcm_ahci_priv { 84 struct device *dev; 85 void __iomem *top_ctrl; 86 u32 port_mask; 87 u32 quirks; 88 enum brcm_ahci_version version; 89 struct reset_control *rcdev; 90 }; 91 92 static inline u32 brcm_sata_readreg(void __iomem *addr) 93 { 94 /* 95 * MIPS endianness is configured by boot strap, which also reverses all 96 * bus endianness (i.e., big-endian CPU + big endian bus ==> native 97 * endian I/O). 98 * 99 * Other architectures (e.g., ARM) either do not support big endian, or 100 * else leave I/O in little endian mode. 101 */ 102 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 103 return __raw_readl(addr); 104 else 105 return readl_relaxed(addr); 106 } 107 108 static inline void brcm_sata_writereg(u32 val, void __iomem *addr) 109 { 110 /* See brcm_sata_readreg() comments */ 111 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 112 __raw_writel(val, addr); 113 else 114 writel_relaxed(val, addr); 115 } 116 117 static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv) 118 { 119 struct brcm_ahci_priv *priv = hpriv->plat_data; 120 u32 port_ctrl, host_caps; 121 int i; 122 123 /* Enable support for ALPM */ 124 host_caps = readl(hpriv->mmio + HOST_CAP); 125 if (!(host_caps & HOST_CAP_ALPM)) 126 hpriv->flags |= AHCI_HFLAG_YES_ALPM; 127 128 /* 129 * Adjust timeout to allow PLL sufficient time to lock while waking 130 * up from slumber mode. 131 */ 132 for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL; 133 i < SATA_TOP_MAX_PHYS; 134 i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) { 135 if (priv->port_mask & BIT(i)) 136 writel(0xff1003fc, 137 hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl)); 138 } 139 } 140 141 static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port) 142 { 143 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL + 144 (port * SATA_TOP_CTRL_PHY_OFFS); 145 void __iomem *p; 146 u32 reg; 147 148 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE) 149 return; 150 151 /* clear PHY_DEFAULT_POWER_STATE */ 152 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1; 153 reg = brcm_sata_readreg(p); 154 reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE; 155 brcm_sata_writereg(reg, p); 156 157 /* reset the PHY digital logic */ 158 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2; 159 reg = brcm_sata_readreg(p); 160 reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB | 161 SATA_TOP_CTRL_2_SW_RST_RX); 162 reg |= SATA_TOP_CTRL_2_SW_RST_TX; 163 brcm_sata_writereg(reg, p); 164 reg = brcm_sata_readreg(p); 165 reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET; 166 brcm_sata_writereg(reg, p); 167 reg = brcm_sata_readreg(p); 168 reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET; 169 brcm_sata_writereg(reg, p); 170 (void)brcm_sata_readreg(p); 171 } 172 173 static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port) 174 { 175 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL + 176 (port * SATA_TOP_CTRL_PHY_OFFS); 177 void __iomem *p; 178 u32 reg; 179 180 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE) 181 return; 182 183 /* power-off the PHY digital logic */ 184 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2; 185 reg = brcm_sata_readreg(p); 186 reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB | 187 SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX | 188 SATA_TOP_CTRL_2_PHY_GLOBAL_RESET); 189 brcm_sata_writereg(reg, p); 190 191 /* set PHY_DEFAULT_POWER_STATE */ 192 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1; 193 reg = brcm_sata_readreg(p); 194 reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE; 195 brcm_sata_writereg(reg, p); 196 } 197 198 static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv) 199 { 200 int i; 201 202 for (i = 0; i < SATA_TOP_MAX_PHYS; i++) 203 if (priv->port_mask & BIT(i)) 204 brcm_sata_phy_enable(priv, i); 205 } 206 207 static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv) 208 { 209 int i; 210 211 for (i = 0; i < SATA_TOP_MAX_PHYS; i++) 212 if (priv->port_mask & BIT(i)) 213 brcm_sata_phy_disable(priv, i); 214 } 215 216 static u32 brcm_ahci_get_portmask(struct ahci_host_priv *hpriv, 217 struct brcm_ahci_priv *priv) 218 { 219 u32 impl; 220 221 impl = readl(hpriv->mmio + HOST_PORTS_IMPL); 222 223 if (fls(impl) > SATA_TOP_MAX_PHYS) 224 dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n", 225 impl); 226 else if (!impl) 227 dev_info(priv->dev, "no ports found\n"); 228 229 return impl; 230 } 231 232 static void brcm_sata_init(struct brcm_ahci_priv *priv) 233 { 234 void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL; 235 u32 data; 236 237 /* Configure endianness */ 238 data = brcm_sata_readreg(ctrl); 239 data &= ~BUS_CTRL_ENDIAN_CONF_MASK; 240 if (priv->version == BRCM_SATA_NSP) 241 data |= BUS_CTRL_ENDIAN_NSP_CONF; 242 else 243 data |= BUS_CTRL_ENDIAN_CONF; 244 brcm_sata_writereg(data, ctrl); 245 } 246 247 static unsigned int brcm_ahci_read_id(struct ata_device *dev, 248 struct ata_taskfile *tf, u16 *id) 249 { 250 struct ata_port *ap = dev->link->ap; 251 struct ata_host *host = ap->host; 252 struct ahci_host_priv *hpriv = host->private_data; 253 struct brcm_ahci_priv *priv = hpriv->plat_data; 254 void __iomem *mmio = hpriv->mmio; 255 unsigned int err_mask; 256 unsigned long flags; 257 int i, rc; 258 u32 ctl; 259 260 /* Try to read the device ID and, if this fails, proceed with the 261 * recovery sequence below 262 */ 263 err_mask = ata_do_dev_read_id(dev, tf, id); 264 if (likely(!err_mask)) 265 return err_mask; 266 267 /* Disable host interrupts */ 268 spin_lock_irqsave(&host->lock, flags); 269 ctl = readl(mmio + HOST_CTL); 270 ctl &= ~HOST_IRQ_EN; 271 writel(ctl, mmio + HOST_CTL); 272 readl(mmio + HOST_CTL); /* flush */ 273 spin_unlock_irqrestore(&host->lock, flags); 274 275 /* Perform the SATA PHY reset sequence */ 276 brcm_sata_phy_disable(priv, ap->port_no); 277 278 /* Reset the SATA clock */ 279 ahci_platform_disable_clks(hpriv); 280 msleep(10); 281 282 ahci_platform_enable_clks(hpriv); 283 msleep(10); 284 285 /* Bring the PHY back on */ 286 brcm_sata_phy_enable(priv, ap->port_no); 287 288 /* Re-initialize and calibrate the PHY */ 289 for (i = 0; i < hpriv->nports; i++) { 290 rc = phy_init(hpriv->phys[i]); 291 if (rc) 292 goto disable_phys; 293 294 rc = phy_calibrate(hpriv->phys[i]); 295 if (rc) { 296 phy_exit(hpriv->phys[i]); 297 goto disable_phys; 298 } 299 } 300 301 /* Re-enable host interrupts */ 302 spin_lock_irqsave(&host->lock, flags); 303 ctl = readl(mmio + HOST_CTL); 304 ctl |= HOST_IRQ_EN; 305 writel(ctl, mmio + HOST_CTL); 306 readl(mmio + HOST_CTL); /* flush */ 307 spin_unlock_irqrestore(&host->lock, flags); 308 309 return ata_do_dev_read_id(dev, tf, id); 310 311 disable_phys: 312 while (--i >= 0) { 313 phy_power_off(hpriv->phys[i]); 314 phy_exit(hpriv->phys[i]); 315 } 316 317 return AC_ERR_OTHER; 318 } 319 320 static void brcm_ahci_host_stop(struct ata_host *host) 321 { 322 struct ahci_host_priv *hpriv = host->private_data; 323 324 ahci_platform_disable_resources(hpriv); 325 } 326 327 static struct ata_port_operations ahci_brcm_platform_ops = { 328 .inherits = &ahci_ops, 329 .host_stop = brcm_ahci_host_stop, 330 .read_id = brcm_ahci_read_id, 331 }; 332 333 static const struct ata_port_info ahci_brcm_port_info = { 334 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 335 .link_flags = ATA_LFLAG_NO_DB_DELAY, 336 .pio_mask = ATA_PIO4, 337 .udma_mask = ATA_UDMA6, 338 .port_ops = &ahci_brcm_platform_ops, 339 }; 340 341 static int brcm_ahci_suspend(struct device *dev) 342 { 343 struct ata_host *host = dev_get_drvdata(dev); 344 struct ahci_host_priv *hpriv = host->private_data; 345 struct brcm_ahci_priv *priv = hpriv->plat_data; 346 int ret; 347 348 brcm_sata_phys_disable(priv); 349 350 if (IS_ENABLED(CONFIG_PM_SLEEP)) 351 ret = ahci_platform_suspend(dev); 352 else 353 ret = 0; 354 355 if (priv->version != BRCM_SATA_BCM7216) 356 reset_control_assert(priv->rcdev); 357 358 return ret; 359 } 360 361 static int __maybe_unused brcm_ahci_resume(struct device *dev) 362 { 363 struct ata_host *host = dev_get_drvdata(dev); 364 struct ahci_host_priv *hpriv = host->private_data; 365 struct brcm_ahci_priv *priv = hpriv->plat_data; 366 int ret = 0; 367 368 if (priv->version == BRCM_SATA_BCM7216) 369 ret = reset_control_reset(priv->rcdev); 370 else 371 ret = reset_control_deassert(priv->rcdev); 372 if (ret) 373 return ret; 374 375 /* Make sure clocks are turned on before re-configuration */ 376 ret = ahci_platform_enable_clks(hpriv); 377 if (ret) 378 return ret; 379 380 brcm_sata_init(priv); 381 brcm_sata_phys_enable(priv); 382 brcm_sata_alpm_init(hpriv); 383 384 /* Since we had to enable clocks earlier on, we cannot use 385 * ahci_platform_resume() as-is since a second call to 386 * ahci_platform_enable_resources() would bump up the resources 387 * (regulators, clocks, PHYs) count artificially so we copy the part 388 * after ahci_platform_enable_resources(). 389 */ 390 ret = ahci_platform_enable_phys(hpriv); 391 if (ret) 392 goto out_disable_phys; 393 394 ret = ahci_platform_resume_host(dev); 395 if (ret) 396 goto out_disable_platform_phys; 397 398 /* We resumed so update PM runtime state */ 399 pm_runtime_disable(dev); 400 pm_runtime_set_active(dev); 401 pm_runtime_enable(dev); 402 403 return 0; 404 405 out_disable_platform_phys: 406 ahci_platform_disable_phys(hpriv); 407 out_disable_phys: 408 brcm_sata_phys_disable(priv); 409 ahci_platform_disable_clks(hpriv); 410 return ret; 411 } 412 413 static struct scsi_host_template ahci_platform_sht = { 414 AHCI_SHT(DRV_NAME), 415 }; 416 417 static const struct of_device_id ahci_of_match[] = { 418 {.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425}, 419 {.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445}, 420 {.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445}, 421 {.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP}, 422 {.compatible = "brcm,bcm7216-ahci", .data = (void *)BRCM_SATA_BCM7216}, 423 {}, 424 }; 425 MODULE_DEVICE_TABLE(of, ahci_of_match); 426 427 static int brcm_ahci_probe(struct platform_device *pdev) 428 { 429 const struct of_device_id *of_id; 430 struct device *dev = &pdev->dev; 431 const char *reset_name = NULL; 432 struct brcm_ahci_priv *priv; 433 struct ahci_host_priv *hpriv; 434 struct resource *res; 435 int ret; 436 437 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 438 if (!priv) 439 return -ENOMEM; 440 441 of_id = of_match_node(ahci_of_match, pdev->dev.of_node); 442 if (!of_id) 443 return -ENODEV; 444 445 priv->version = (enum brcm_ahci_version)of_id->data; 446 priv->dev = dev; 447 448 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl"); 449 priv->top_ctrl = devm_ioremap_resource(dev, res); 450 if (IS_ERR(priv->top_ctrl)) 451 return PTR_ERR(priv->top_ctrl); 452 453 /* Reset is optional depending on platform and named differently */ 454 if (priv->version == BRCM_SATA_BCM7216) 455 reset_name = "rescal"; 456 else 457 reset_name = "ahci"; 458 459 priv->rcdev = devm_reset_control_get_optional(&pdev->dev, reset_name); 460 if (IS_ERR(priv->rcdev)) 461 return PTR_ERR(priv->rcdev); 462 463 hpriv = ahci_platform_get_resources(pdev, 0); 464 if (IS_ERR(hpriv)) 465 return PTR_ERR(hpriv); 466 467 hpriv->plat_data = priv; 468 hpriv->flags = AHCI_HFLAG_WAKE_BEFORE_STOP | AHCI_HFLAG_NO_WRITE_TO_RO; 469 470 switch (priv->version) { 471 case BRCM_SATA_BCM7425: 472 hpriv->flags |= AHCI_HFLAG_DELAY_ENGINE; 473 /* fall through */ 474 case BRCM_SATA_NSP: 475 hpriv->flags |= AHCI_HFLAG_NO_NCQ; 476 priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE; 477 break; 478 default: 479 break; 480 } 481 482 if (priv->version == BRCM_SATA_BCM7216) 483 ret = reset_control_reset(priv->rcdev); 484 else 485 ret = reset_control_deassert(priv->rcdev); 486 if (ret) 487 return ret; 488 489 ret = ahci_platform_enable_clks(hpriv); 490 if (ret) 491 goto out_reset; 492 493 /* Must be first so as to configure endianness including that 494 * of the standard AHCI register space. 495 */ 496 brcm_sata_init(priv); 497 498 /* Initializes priv->port_mask which is used below */ 499 priv->port_mask = brcm_ahci_get_portmask(hpriv, priv); 500 if (!priv->port_mask) { 501 ret = -ENODEV; 502 goto out_disable_clks; 503 } 504 505 /* Must be done before ahci_platform_enable_phys() */ 506 brcm_sata_phys_enable(priv); 507 508 brcm_sata_alpm_init(hpriv); 509 510 ret = ahci_platform_enable_phys(hpriv); 511 if (ret) 512 goto out_disable_phys; 513 514 ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info, 515 &ahci_platform_sht); 516 if (ret) 517 goto out_disable_platform_phys; 518 519 dev_info(dev, "Broadcom AHCI SATA3 registered\n"); 520 521 return 0; 522 523 out_disable_platform_phys: 524 ahci_platform_disable_phys(hpriv); 525 out_disable_phys: 526 brcm_sata_phys_disable(priv); 527 out_disable_clks: 528 ahci_platform_disable_clks(hpriv); 529 out_reset: 530 if (priv->version != BRCM_SATA_BCM7216) 531 reset_control_assert(priv->rcdev); 532 return ret; 533 } 534 535 static int brcm_ahci_remove(struct platform_device *pdev) 536 { 537 struct ata_host *host = dev_get_drvdata(&pdev->dev); 538 struct ahci_host_priv *hpriv = host->private_data; 539 struct brcm_ahci_priv *priv = hpriv->plat_data; 540 int ret; 541 542 brcm_sata_phys_disable(priv); 543 544 ret = ata_platform_remove_one(pdev); 545 if (ret) 546 return ret; 547 548 return 0; 549 } 550 551 static void brcm_ahci_shutdown(struct platform_device *pdev) 552 { 553 int ret; 554 555 /* All resources releasing happens via devres, but our device, unlike a 556 * proper remove is not disappearing, therefore using 557 * brcm_ahci_suspend() here which does explicit power management is 558 * appropriate. 559 */ 560 ret = brcm_ahci_suspend(&pdev->dev); 561 if (ret) 562 dev_err(&pdev->dev, "failed to shutdown\n"); 563 } 564 565 static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume); 566 567 static struct platform_driver brcm_ahci_driver = { 568 .probe = brcm_ahci_probe, 569 .remove = brcm_ahci_remove, 570 .shutdown = brcm_ahci_shutdown, 571 .driver = { 572 .name = DRV_NAME, 573 .of_match_table = ahci_of_match, 574 .pm = &ahci_brcm_pm_ops, 575 }, 576 }; 577 module_platform_driver(brcm_ahci_driver); 578 579 MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver"); 580 MODULE_AUTHOR("Brian Norris"); 581 MODULE_LICENSE("GPL"); 582 MODULE_ALIAS("platform:sata-brcmstb"); 583