1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * ahci.h - Common AHCI SATA definitions and declarations 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19 #ifndef _AHCI_H 20 #define _AHCI_H 21 22 #include <linux/pci.h> 23 #include <linux/clk.h> 24 #include <linux/libata.h> 25 #include <linux/phy/phy.h> 26 #include <linux/regulator/consumer.h> 27 28 /* Enclosure Management Control */ 29 #define EM_CTRL_MSG_TYPE 0x000f0000 30 31 /* Enclosure Management LED Message Type */ 32 #define EM_MSG_LED_HBA_PORT 0x0000000f 33 #define EM_MSG_LED_PMP_SLOT 0x0000ff00 34 #define EM_MSG_LED_VALUE 0xffff0000 35 #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000 36 #define EM_MSG_LED_VALUE_OFF 0xfff80000 37 #define EM_MSG_LED_VALUE_ON 0x00010000 38 39 enum { 40 AHCI_MAX_PORTS = 32, 41 AHCI_MAX_SG = 168, /* hardware max is 64K */ 42 AHCI_DMA_BOUNDARY = 0xffffffff, 43 AHCI_MAX_CMDS = 32, 44 AHCI_CMD_SZ = 32, 45 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, 46 AHCI_RX_FIS_SZ = 256, 47 AHCI_CMD_TBL_CDB = 0x40, 48 AHCI_CMD_TBL_HDR_SZ = 0x80, 49 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), 50 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, 51 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + 52 AHCI_RX_FIS_SZ, 53 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ + 54 AHCI_CMD_TBL_AR_SZ + 55 (AHCI_RX_FIS_SZ * 16), 56 AHCI_IRQ_ON_SG = (1 << 31), 57 AHCI_CMD_ATAPI = (1 << 5), 58 AHCI_CMD_WRITE = (1 << 6), 59 AHCI_CMD_PREFETCH = (1 << 7), 60 AHCI_CMD_RESET = (1 << 8), 61 AHCI_CMD_CLR_BUSY = (1 << 10), 62 63 RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */ 64 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ 65 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ 66 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ 67 68 /* global controller registers */ 69 HOST_CAP = 0x00, /* host capabilities */ 70 HOST_CTL = 0x04, /* global host control */ 71 HOST_IRQ_STAT = 0x08, /* interrupt status */ 72 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ 73 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ 74 HOST_EM_LOC = 0x1c, /* Enclosure Management location */ 75 HOST_EM_CTL = 0x20, /* Enclosure Management Control */ 76 HOST_CAP2 = 0x24, /* host capabilities, extended */ 77 78 /* HOST_CTL bits */ 79 HOST_RESET = (1 << 0), /* reset controller; self-clear */ 80 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ 81 HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */ 82 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ 83 84 /* HOST_CAP bits */ 85 HOST_CAP_SXS = (1 << 5), /* Supports External SATA */ 86 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */ 87 HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */ 88 HOST_CAP_PART = (1 << 13), /* Partial state capable */ 89 HOST_CAP_SSC = (1 << 14), /* Slumber state capable */ 90 HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */ 91 HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */ 92 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ 93 HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */ 94 HOST_CAP_CLO = (1 << 24), /* Command List Override support */ 95 HOST_CAP_LED = (1 << 25), /* Supports activity LED */ 96 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ 97 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ 98 HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */ 99 HOST_CAP_SNTF = (1 << 29), /* SNotification register */ 100 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ 101 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ 102 103 /* HOST_CAP2 bits */ 104 HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */ 105 HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */ 106 HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */ 107 HOST_CAP2_SDS = (1 << 3), /* Support device sleep */ 108 HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */ 109 HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */ 110 111 /* registers for each SATA port */ 112 PORT_LST_ADDR = 0x00, /* command list DMA addr */ 113 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ 114 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ 115 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ 116 PORT_IRQ_STAT = 0x10, /* interrupt status */ 117 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ 118 PORT_CMD = 0x18, /* port command */ 119 PORT_TFDATA = 0x20, /* taskfile data */ 120 PORT_SIG = 0x24, /* device TF signature */ 121 PORT_CMD_ISSUE = 0x38, /* command issue */ 122 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ 123 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ 124 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ 125 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ 126 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ 127 PORT_FBS = 0x40, /* FIS-based Switching */ 128 PORT_DEVSLP = 0x44, /* device sleep */ 129 130 /* PORT_IRQ_{STAT,MASK} bits */ 131 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ 132 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ 133 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ 134 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ 135 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ 136 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ 137 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ 138 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ 139 140 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ 141 PORT_IRQ_DMPS = (1 << 7), /* mechanical presence status */ 142 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ 143 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ 144 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ 145 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ 146 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ 147 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ 148 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ 149 150 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | 151 PORT_IRQ_IF_ERR | 152 PORT_IRQ_CONNECT | 153 PORT_IRQ_PHYRDY | 154 PORT_IRQ_UNK_FIS | 155 PORT_IRQ_BAD_PMP, 156 PORT_IRQ_ERROR = PORT_IRQ_FREEZE | 157 PORT_IRQ_TF_ERR | 158 PORT_IRQ_HBUS_DATA_ERR, 159 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | 160 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | 161 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, 162 163 /* PORT_CMD bits */ 164 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ 165 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ 166 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ 167 PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ 168 PORT_CMD_ESP = (1 << 21), /* External Sata Port */ 169 PORT_CMD_CPD = (1 << 20), /* Cold Presence Detection */ 170 PORT_CMD_MPSP = (1 << 19), /* Mechanical Presence Switch */ 171 PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */ 172 PORT_CMD_PMP = (1 << 17), /* PMP attached */ 173 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ 174 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ 175 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ 176 PORT_CMD_CLO = (1 << 3), /* Command list override */ 177 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ 178 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ 179 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ 180 181 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ 182 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ 183 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ 184 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ 185 186 /* PORT_CMD capabilities mask */ 187 PORT_CMD_CAP = PORT_CMD_HPCP | PORT_CMD_MPSP | 188 PORT_CMD_CPD | PORT_CMD_ESP | PORT_CMD_FBSCP, 189 190 /* PORT_FBS bits */ 191 PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */ 192 PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */ 193 PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */ 194 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */ 195 PORT_FBS_SDE = (1 << 2), /* FBS single device error */ 196 PORT_FBS_DEC = (1 << 1), /* FBS device error clear */ 197 PORT_FBS_EN = (1 << 0), /* Enable FBS */ 198 199 /* PORT_DEVSLP bits */ 200 PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */ 201 PORT_DEVSLP_DM_MASK = (0xf << 25), /* DITO multiplier mask */ 202 PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */ 203 PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */ 204 PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */ 205 PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */ 206 PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */ 207 208 /* hpriv->flags bits */ 209 210 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) 211 212 AHCI_HFLAG_NO_NCQ = (1 << 0), 213 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ 214 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ 215 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ 216 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ 217 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ 218 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ 219 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ 220 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ 221 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */ 222 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as 223 link offline */ 224 AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */ 225 AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */ 226 AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */ 227 AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on 228 port start (wait until 229 error-handling stage) */ 230 AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */ 231 AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */ 232 233 #ifdef CONFIG_PCI_MSI 234 AHCI_HFLAG_MULTI_MSI = (1 << 20), /* per-port MSI(-X) */ 235 #else 236 /* compile out MSI infrastructure */ 237 AHCI_HFLAG_MULTI_MSI = 0, 238 #endif 239 AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22), /* wake before DMA stop */ 240 AHCI_HFLAG_YES_ALPM = (1 << 23), /* force ALPM cap on */ 241 AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read 242 only registers */ 243 AHCI_HFLAG_USE_LPM_POLICY = (1 << 25), /* chipset that should use 244 SATA_MOBILE_LPM_POLICY 245 as default lpm_policy */ 246 AHCI_HFLAG_SUSPEND_PHYS = (1 << 26), /* handle PHYs during 247 suspend/resume */ 248 AHCI_HFLAG_NO_SXS = (1 << 28), /* SXS not supported */ 249 250 /* ap->flags bits */ 251 252 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | 253 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN, 254 255 ICH_MAP = 0x90, /* ICH MAP register */ 256 PCS_6 = 0x92, /* 6 port PCS */ 257 PCS_7 = 0x94, /* 7+ port PCS (Denverton) */ 258 259 /* em constants */ 260 EM_MAX_SLOTS = 8, 261 EM_MAX_RETRY = 5, 262 263 /* em_ctl bits */ 264 EM_CTL_RST = (1 << 9), /* Reset */ 265 EM_CTL_TM = (1 << 8), /* Transmit Message */ 266 EM_CTL_MR = (1 << 0), /* Message Received */ 267 EM_CTL_ALHD = (1 << 26), /* Activity LED */ 268 EM_CTL_XMT = (1 << 25), /* Transmit Only */ 269 EM_CTL_SMB = (1 << 24), /* Single Message Buffer */ 270 EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */ 271 EM_CTL_SES = (1 << 18), /* SES-2 messages supported */ 272 EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */ 273 EM_CTL_LED = (1 << 16), /* LED messages supported */ 274 275 /* em message type */ 276 EM_MSG_TYPE_LED = (1 << 0), /* LED */ 277 EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */ 278 EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */ 279 EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */ 280 }; 281 282 struct ahci_cmd_hdr { 283 __le32 opts; 284 __le32 status; 285 __le32 tbl_addr; 286 __le32 tbl_addr_hi; 287 __le32 reserved[4]; 288 }; 289 290 struct ahci_sg { 291 __le32 addr; 292 __le32 addr_hi; 293 __le32 reserved; 294 __le32 flags_size; 295 }; 296 297 struct ahci_em_priv { 298 enum sw_activity blink_policy; 299 struct timer_list timer; 300 unsigned long saved_activity; 301 unsigned long activity; 302 unsigned long led_state; 303 struct ata_link *link; 304 }; 305 306 struct ahci_port_priv { 307 struct ata_link *active_link; 308 struct ahci_cmd_hdr *cmd_slot; 309 dma_addr_t cmd_slot_dma; 310 void *cmd_tbl; 311 dma_addr_t cmd_tbl_dma; 312 void *rx_fis; 313 dma_addr_t rx_fis_dma; 314 /* for NCQ spurious interrupt analysis */ 315 unsigned int ncq_saw_d2h:1; 316 unsigned int ncq_saw_dmas:1; 317 unsigned int ncq_saw_sdb:1; 318 spinlock_t lock; /* protects parent ata_port */ 319 u32 intr_mask; /* interrupts to enable */ 320 bool fbs_supported; /* set iff FBS is supported */ 321 bool fbs_enabled; /* set iff FBS is enabled */ 322 int fbs_last_dev; /* save FBS.DEV of last FIS */ 323 /* enclosure management info per PM slot */ 324 struct ahci_em_priv em_priv[EM_MAX_SLOTS]; 325 char *irq_desc; /* desc in /proc/interrupts */ 326 }; 327 328 struct ahci_host_priv { 329 /* Input fields */ 330 unsigned int flags; /* AHCI_HFLAG_* */ 331 u32 mask_port_map; /* mask out particular bits */ 332 333 void __iomem * mmio; /* bus-independent mem map */ 334 u32 cap; /* cap to use */ 335 u32 cap2; /* cap2 to use */ 336 u32 version; /* cached version */ 337 u32 port_map; /* port map to use */ 338 u32 saved_cap; /* saved initial cap */ 339 u32 saved_cap2; /* saved initial cap2 */ 340 u32 saved_port_map; /* saved initial port_map */ 341 u32 saved_port_cap[AHCI_MAX_PORTS]; /* saved port_cap */ 342 u32 em_loc; /* enclosure management location */ 343 u32 em_buf_sz; /* EM buffer size in byte */ 344 u32 em_msg_type; /* EM message type */ 345 u32 remapped_nvme; /* NVMe remapped device count */ 346 bool got_runtime_pm; /* Did we do pm_runtime_get? */ 347 unsigned int n_clks; 348 struct clk_bulk_data *clks; /* Optional */ 349 unsigned int f_rsts; 350 struct reset_control *rsts; /* Optional */ 351 struct regulator **target_pwrs; /* Optional */ 352 struct regulator *ahci_regulator;/* Optional */ 353 struct regulator *phy_regulator;/* Optional */ 354 /* 355 * If platform uses PHYs. There is a 1:1 relation between the port number and 356 * the PHY position in this array. 357 */ 358 struct phy **phys; 359 unsigned nports; /* Number of ports */ 360 void *plat_data; /* Other platform data */ 361 unsigned int irq; /* interrupt line */ 362 /* 363 * Optional ahci_start_engine override, if not set this gets set to the 364 * default ahci_start_engine during ahci_save_initial_config, this can 365 * be overridden anytime before the host is activated. 366 */ 367 void (*start_engine)(struct ata_port *ap); 368 /* 369 * Optional ahci_stop_engine override, if not set this gets set to the 370 * default ahci_stop_engine during ahci_save_initial_config, this can 371 * be overridden anytime before the host is activated. 372 */ 373 int (*stop_engine)(struct ata_port *ap); 374 375 irqreturn_t (*irq_handler)(int irq, void *dev_instance); 376 377 /* only required for per-port MSI(-X) support */ 378 int (*get_irq_vector)(struct ata_host *host, 379 int port); 380 }; 381 382 extern int ahci_ignore_sss; 383 384 extern const struct attribute_group *ahci_shost_groups[]; 385 extern const struct attribute_group *ahci_sdev_groups[]; 386 387 /* 388 * This must be instantiated by the edge drivers. Read the comments 389 * for ATA_BASE_SHT 390 */ 391 #define AHCI_SHT(drv_name) \ 392 __ATA_BASE_SHT(drv_name), \ 393 .can_queue = AHCI_MAX_CMDS, \ 394 .sg_tablesize = AHCI_MAX_SG, \ 395 .dma_boundary = AHCI_DMA_BOUNDARY, \ 396 .shost_groups = ahci_shost_groups, \ 397 .sdev_groups = ahci_sdev_groups, \ 398 .change_queue_depth = ata_scsi_change_queue_depth, \ 399 .tag_alloc_policy = BLK_TAG_ALLOC_RR, \ 400 .slave_configure = ata_scsi_slave_config 401 402 extern struct ata_port_operations ahci_ops; 403 extern struct ata_port_operations ahci_platform_ops; 404 extern struct ata_port_operations ahci_pmp_retry_srst_ops; 405 406 unsigned int ahci_dev_classify(struct ata_port *ap); 407 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 408 u32 opts); 409 void ahci_save_initial_config(struct device *dev, 410 struct ahci_host_priv *hpriv); 411 void ahci_init_controller(struct ata_host *host); 412 int ahci_reset_controller(struct ata_host *host); 413 414 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 415 int pmp, unsigned long deadline, 416 int (*check_ready)(struct ata_link *link)); 417 418 int ahci_do_hardreset(struct ata_link *link, unsigned int *class, 419 unsigned long deadline, bool *online); 420 421 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); 422 int ahci_stop_engine(struct ata_port *ap); 423 void ahci_start_fis_rx(struct ata_port *ap); 424 void ahci_start_engine(struct ata_port *ap); 425 int ahci_check_ready(struct ata_link *link); 426 int ahci_kick_engine(struct ata_port *ap); 427 int ahci_port_resume(struct ata_port *ap); 428 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 429 struct ata_port_info *pi); 430 int ahci_reset_em(struct ata_host *host); 431 void ahci_print_info(struct ata_host *host, const char *scc_s); 432 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht); 433 void ahci_error_handler(struct ata_port *ap); 434 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked); 435 436 static inline void __iomem *__ahci_port_base(struct ahci_host_priv *hpriv, 437 unsigned int port_no) 438 { 439 void __iomem *mmio = hpriv->mmio; 440 441 return mmio + 0x100 + (port_no * 0x80); 442 } 443 444 static inline void __iomem *ahci_port_base(struct ata_port *ap) 445 { 446 struct ahci_host_priv *hpriv = ap->host->private_data; 447 448 return __ahci_port_base(hpriv, ap->port_no); 449 } 450 451 static inline int ahci_nr_ports(u32 cap) 452 { 453 return (cap & 0x1f) + 1; 454 } 455 456 #endif /* _AHCI_H */ 457