1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ahci.c - AHCI SATA support 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/device.h> 27 #include <linux/dmi.h> 28 #include <linux/gfp.h> 29 #include <scsi/scsi_host.h> 30 #include <scsi/scsi_cmnd.h> 31 #include <linux/libata.h> 32 #include <linux/ahci-remap.h> 33 #include <linux/io-64-nonatomic-lo-hi.h> 34 #include "ahci.h" 35 36 #define DRV_NAME "ahci" 37 #define DRV_VERSION "3.0" 38 39 enum { 40 AHCI_PCI_BAR_STA2X11 = 0, 41 AHCI_PCI_BAR_CAVIUM = 0, 42 AHCI_PCI_BAR_LOONGSON = 0, 43 AHCI_PCI_BAR_ENMOTUS = 2, 44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4, 45 AHCI_PCI_BAR_STANDARD = 5, 46 }; 47 48 enum board_ids { 49 /* board IDs by feature in alphabetical order */ 50 board_ahci, 51 board_ahci_43bit_dma, 52 board_ahci_ign_iferr, 53 board_ahci_no_debounce_delay, 54 board_ahci_no_msi, 55 /* 56 * board_ahci_pcs_quirk is for legacy Intel platforms. 57 * Modern Intel platforms should use board_ahci instead. 58 * (Some modern Intel platforms might have been added with 59 * board_ahci_pcs_quirk, however, we cannot change them to board_ahci 60 * without testing that the platform actually works without the quirk.) 61 */ 62 board_ahci_pcs_quirk, 63 board_ahci_pcs_quirk_no_devslp, 64 board_ahci_pcs_quirk_no_sntf, 65 board_ahci_yes_fbs, 66 67 /* board IDs for specific chipsets in alphabetical order */ 68 board_ahci_al, 69 board_ahci_avn, 70 board_ahci_mcp65, 71 board_ahci_mcp77, 72 board_ahci_mcp89, 73 board_ahci_mv, 74 board_ahci_sb600, 75 board_ahci_sb700, /* for SB700 and SB800 */ 76 board_ahci_vt8251, 77 78 /* aliases */ 79 board_ahci_mcp_linux = board_ahci_mcp65, 80 board_ahci_mcp67 = board_ahci_mcp65, 81 board_ahci_mcp73 = board_ahci_mcp65, 82 board_ahci_mcp79 = board_ahci_mcp77, 83 }; 84 85 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 86 static void ahci_remove_one(struct pci_dev *dev); 87 static void ahci_shutdown_one(struct pci_dev *dev); 88 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv); 89 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 90 unsigned long deadline); 91 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 92 unsigned long deadline); 93 static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 94 static bool is_mcp89_apple(struct pci_dev *pdev); 95 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 96 unsigned long deadline); 97 #ifdef CONFIG_PM 98 static int ahci_pci_device_runtime_suspend(struct device *dev); 99 static int ahci_pci_device_runtime_resume(struct device *dev); 100 #ifdef CONFIG_PM_SLEEP 101 static int ahci_pci_device_suspend(struct device *dev); 102 static int ahci_pci_device_resume(struct device *dev); 103 #endif 104 #endif /* CONFIG_PM */ 105 106 static const struct scsi_host_template ahci_sht = { 107 AHCI_SHT("ahci"), 108 }; 109 110 static struct ata_port_operations ahci_vt8251_ops = { 111 .inherits = &ahci_ops, 112 .hardreset = ahci_vt8251_hardreset, 113 }; 114 115 static struct ata_port_operations ahci_p5wdh_ops = { 116 .inherits = &ahci_ops, 117 .hardreset = ahci_p5wdh_hardreset, 118 }; 119 120 static struct ata_port_operations ahci_avn_ops = { 121 .inherits = &ahci_ops, 122 .hardreset = ahci_avn_hardreset, 123 }; 124 125 static const struct ata_port_info ahci_port_info[] = { 126 /* by features */ 127 [board_ahci] = { 128 .flags = AHCI_FLAG_COMMON, 129 .pio_mask = ATA_PIO4, 130 .udma_mask = ATA_UDMA6, 131 .port_ops = &ahci_ops, 132 }, 133 [board_ahci_43bit_dma] = { 134 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY), 135 .flags = AHCI_FLAG_COMMON, 136 .pio_mask = ATA_PIO4, 137 .udma_mask = ATA_UDMA6, 138 .port_ops = &ahci_ops, 139 }, 140 [board_ahci_ign_iferr] = { 141 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 142 .flags = AHCI_FLAG_COMMON, 143 .pio_mask = ATA_PIO4, 144 .udma_mask = ATA_UDMA6, 145 .port_ops = &ahci_ops, 146 }, 147 [board_ahci_no_debounce_delay] = { 148 .flags = AHCI_FLAG_COMMON, 149 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY, 150 .pio_mask = ATA_PIO4, 151 .udma_mask = ATA_UDMA6, 152 .port_ops = &ahci_ops, 153 }, 154 [board_ahci_no_msi] = { 155 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 156 .flags = AHCI_FLAG_COMMON, 157 .pio_mask = ATA_PIO4, 158 .udma_mask = ATA_UDMA6, 159 .port_ops = &ahci_ops, 160 }, 161 [board_ahci_pcs_quirk] = { 162 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK), 163 .flags = AHCI_FLAG_COMMON, 164 .pio_mask = ATA_PIO4, 165 .udma_mask = ATA_UDMA6, 166 .port_ops = &ahci_ops, 167 }, 168 [board_ahci_pcs_quirk_no_devslp] = { 169 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK | 170 AHCI_HFLAG_NO_DEVSLP), 171 .flags = AHCI_FLAG_COMMON, 172 .pio_mask = ATA_PIO4, 173 .udma_mask = ATA_UDMA6, 174 .port_ops = &ahci_ops, 175 }, 176 [board_ahci_pcs_quirk_no_sntf] = { 177 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK | 178 AHCI_HFLAG_NO_SNTF), 179 .flags = AHCI_FLAG_COMMON, 180 .pio_mask = ATA_PIO4, 181 .udma_mask = ATA_UDMA6, 182 .port_ops = &ahci_ops, 183 }, 184 [board_ahci_yes_fbs] = { 185 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 186 .flags = AHCI_FLAG_COMMON, 187 .pio_mask = ATA_PIO4, 188 .udma_mask = ATA_UDMA6, 189 .port_ops = &ahci_ops, 190 }, 191 /* by chipsets */ 192 [board_ahci_al] = { 193 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI), 194 .flags = AHCI_FLAG_COMMON, 195 .pio_mask = ATA_PIO4, 196 .udma_mask = ATA_UDMA6, 197 .port_ops = &ahci_ops, 198 }, 199 [board_ahci_avn] = { 200 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK), 201 .flags = AHCI_FLAG_COMMON, 202 .pio_mask = ATA_PIO4, 203 .udma_mask = ATA_UDMA6, 204 .port_ops = &ahci_avn_ops, 205 }, 206 [board_ahci_mcp65] = { 207 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 208 AHCI_HFLAG_YES_NCQ), 209 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 210 .pio_mask = ATA_PIO4, 211 .udma_mask = ATA_UDMA6, 212 .port_ops = &ahci_ops, 213 }, 214 [board_ahci_mcp77] = { 215 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 216 .flags = AHCI_FLAG_COMMON, 217 .pio_mask = ATA_PIO4, 218 .udma_mask = ATA_UDMA6, 219 .port_ops = &ahci_ops, 220 }, 221 [board_ahci_mcp89] = { 222 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 223 .flags = AHCI_FLAG_COMMON, 224 .pio_mask = ATA_PIO4, 225 .udma_mask = ATA_UDMA6, 226 .port_ops = &ahci_ops, 227 }, 228 [board_ahci_mv] = { 229 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 230 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 231 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 232 .pio_mask = ATA_PIO4, 233 .udma_mask = ATA_UDMA6, 234 .port_ops = &ahci_ops, 235 }, 236 [board_ahci_sb600] = { 237 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 238 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 239 AHCI_HFLAG_32BIT_ONLY), 240 .flags = AHCI_FLAG_COMMON, 241 .pio_mask = ATA_PIO4, 242 .udma_mask = ATA_UDMA6, 243 .port_ops = &ahci_pmp_retry_srst_ops, 244 }, 245 [board_ahci_sb700] = { /* for SB700 and SB800 */ 246 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 247 .flags = AHCI_FLAG_COMMON, 248 .pio_mask = ATA_PIO4, 249 .udma_mask = ATA_UDMA6, 250 .port_ops = &ahci_pmp_retry_srst_ops, 251 }, 252 [board_ahci_vt8251] = { 253 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 254 .flags = AHCI_FLAG_COMMON, 255 .pio_mask = ATA_PIO4, 256 .udma_mask = ATA_UDMA6, 257 .port_ops = &ahci_vt8251_ops, 258 }, 259 }; 260 261 static const struct pci_device_id ahci_pci_tbl[] = { 262 /* Intel */ 263 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci_pcs_quirk }, /* Comet Lake PCH-H RAID */ 264 { PCI_VDEVICE(INTEL, 0x2652), board_ahci_pcs_quirk }, /* ICH6 */ 265 { PCI_VDEVICE(INTEL, 0x2653), board_ahci_pcs_quirk }, /* ICH6M */ 266 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci_pcs_quirk }, /* ICH7 */ 267 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci_pcs_quirk }, /* ICH7M */ 268 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci_pcs_quirk }, /* ICH7R */ 269 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 270 { PCI_VDEVICE(INTEL, 0x2681), board_ahci_pcs_quirk }, /* ESB2 */ 271 { PCI_VDEVICE(INTEL, 0x2682), board_ahci_pcs_quirk }, /* ESB2 */ 272 { PCI_VDEVICE(INTEL, 0x2683), board_ahci_pcs_quirk }, /* ESB2 */ 273 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci_pcs_quirk }, /* ICH7-M DH */ 274 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pcs_quirk }, /* ICH8 */ 275 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pcs_quirk_no_sntf }, /* ICH8/Lewisburg RAID*/ 276 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pcs_quirk }, /* ICH8 */ 277 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pcs_quirk }, /* ICH8M */ 278 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pcs_quirk }, /* ICH8M */ 279 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pcs_quirk }, /* ICH9 */ 280 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pcs_quirk }, /* ICH9 */ 281 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pcs_quirk }, /* ICH9 */ 282 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pcs_quirk }, /* ICH9 */ 283 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pcs_quirk }, /* ICH9 */ 284 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pcs_quirk }, /* ICH9M */ 285 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pcs_quirk }, /* ICH9M */ 286 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pcs_quirk }, /* ICH9M */ 287 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pcs_quirk }, /* ICH9M */ 288 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pcs_quirk }, /* ICH9M */ 289 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pcs_quirk }, /* ICH9 */ 290 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pcs_quirk }, /* ICH9M */ 291 { PCI_VDEVICE(INTEL, 0x502a), board_ahci_pcs_quirk }, /* Tolapai */ 292 { PCI_VDEVICE(INTEL, 0x502b), board_ahci_pcs_quirk }, /* Tolapai */ 293 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci_pcs_quirk }, /* ICH10 */ 294 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci_pcs_quirk }, /* ICH10 */ 295 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci_pcs_quirk }, /* ICH10 */ 296 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci_pcs_quirk }, /* PCH AHCI */ 297 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci_pcs_quirk }, /* PCH AHCI */ 298 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci_pcs_quirk }, /* PCH RAID */ 299 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci_pcs_quirk }, /* PCH RAID */ 300 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_pcs_quirk }, /* PCH M AHCI */ 301 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci_pcs_quirk }, /* PCH RAID */ 302 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_pcs_quirk }, /* PCH M RAID */ 303 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci_pcs_quirk }, /* PCH AHCI */ 304 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */ 305 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */ 306 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */ 307 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */ 308 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */ 309 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */ 310 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */ 311 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */ 312 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */ 313 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */ 314 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */ 315 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */ 316 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */ 317 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */ 318 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */ 319 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */ 320 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */ 321 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */ 322 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */ 323 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */ 324 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci_pcs_quirk }, /* CPT AHCI */ 325 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_pcs_quirk }, /* CPT M AHCI */ 326 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci_pcs_quirk }, /* CPT RAID */ 327 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_pcs_quirk }, /* CPT M RAID */ 328 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci_pcs_quirk }, /* CPT RAID */ 329 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci_pcs_quirk }, /* CPT RAID */ 330 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci_pcs_quirk }, /* PBG AHCI */ 331 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci_pcs_quirk }, /* PBG RAID */ 332 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci_pcs_quirk }, /* PBG RAID */ 333 { PCI_VDEVICE(INTEL, 0x2323), board_ahci_pcs_quirk }, /* DH89xxCC AHCI */ 334 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci_pcs_quirk }, /* Panther Point AHCI */ 335 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_pcs_quirk }, /* Panther M AHCI */ 336 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci_pcs_quirk }, /* Panther Point RAID */ 337 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci_pcs_quirk }, /* Panther Point RAID */ 338 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci_pcs_quirk }, /* Panther Point RAID */ 339 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_pcs_quirk }, /* Panther M RAID */ 340 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci_pcs_quirk }, /* Panther Point RAID */ 341 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci_pcs_quirk }, /* Lynx Point AHCI */ 342 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_pcs_quirk }, /* Lynx M AHCI */ 343 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci_pcs_quirk }, /* Lynx Point RAID */ 344 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_pcs_quirk }, /* Lynx M RAID */ 345 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci_pcs_quirk }, /* Lynx Point RAID */ 346 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_pcs_quirk }, /* Lynx M RAID */ 347 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci_pcs_quirk }, /* Lynx Point RAID */ 348 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_pcs_quirk }, /* Lynx M RAID */ 349 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_pcs_quirk }, /* Lynx LP AHCI */ 350 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_pcs_quirk }, /* Lynx LP AHCI */ 351 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 352 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 353 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 354 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 355 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 356 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 357 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_pcs_quirk }, /* Cannon Lake PCH-LP AHCI */ 358 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci_pcs_quirk }, /* Avoton AHCI */ 359 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci_pcs_quirk }, /* Avoton AHCI */ 360 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci_pcs_quirk }, /* Avoton RAID */ 361 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci_pcs_quirk }, /* Avoton RAID */ 362 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci_pcs_quirk }, /* Avoton RAID */ 363 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci_pcs_quirk }, /* Avoton RAID */ 364 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci_pcs_quirk }, /* Avoton RAID */ 365 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci_pcs_quirk }, /* Avoton RAID */ 366 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 367 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 368 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 369 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 370 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 371 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 372 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 373 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 374 { PCI_VDEVICE(INTEL, 0x2823), board_ahci_pcs_quirk }, /* Wellsburg/Lewisburg AHCI*/ 375 { PCI_VDEVICE(INTEL, 0x2826), board_ahci_pcs_quirk }, /* *burg SATA0 'RAID' */ 376 { PCI_VDEVICE(INTEL, 0x2827), board_ahci_pcs_quirk }, /* *burg SATA1 'RAID' */ 377 { PCI_VDEVICE(INTEL, 0x282f), board_ahci_pcs_quirk }, /* *burg SATA2 'RAID' */ 378 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */ 379 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */ 380 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */ 381 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */ 382 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci_pcs_quirk }, /* Wellsburg AHCI */ 383 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 384 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 385 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 386 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci_pcs_quirk }, /* Wellsburg AHCI */ 387 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 388 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 389 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 390 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci_pcs_quirk }, /* Coleto Creek AHCI */ 391 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_pcs_quirk }, /* Wildcat LP AHCI */ 392 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_pcs_quirk }, /* Wildcat LP RAID */ 393 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_pcs_quirk }, /* Wildcat LP RAID */ 394 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_pcs_quirk }, /* Wildcat LP RAID */ 395 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci_pcs_quirk }, /* 9 Series AHCI */ 396 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_pcs_quirk }, /* 9 Series M AHCI */ 397 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci_pcs_quirk }, /* 9 Series RAID */ 398 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_pcs_quirk }, /* 9 Series M RAID */ 399 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci_pcs_quirk }, /* 9 Series RAID */ 400 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_pcs_quirk }, /* 9 Series M RAID */ 401 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci_pcs_quirk }, /* 9 Series RAID */ 402 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_pcs_quirk }, /* 9 Series M RAID */ 403 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_pcs_quirk }, /* Sunrise LP AHCI */ 404 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_pcs_quirk }, /* Sunrise LP RAID */ 405 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_pcs_quirk }, /* Sunrise LP RAID */ 406 { PCI_VDEVICE(INTEL, 0xa102), board_ahci_pcs_quirk }, /* Sunrise Point-H AHCI */ 407 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_pcs_quirk }, /* Sunrise M AHCI */ 408 { PCI_VDEVICE(INTEL, 0xa105), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */ 409 { PCI_VDEVICE(INTEL, 0xa106), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */ 410 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_pcs_quirk }, /* Sunrise M RAID */ 411 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */ 412 { PCI_VDEVICE(INTEL, 0xa182), board_ahci_pcs_quirk }, /* Lewisburg AHCI*/ 413 { PCI_VDEVICE(INTEL, 0xa186), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 414 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 415 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 416 { PCI_VDEVICE(INTEL, 0xa202), board_ahci_pcs_quirk }, /* Lewisburg AHCI*/ 417 { PCI_VDEVICE(INTEL, 0xa206), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 418 { PCI_VDEVICE(INTEL, 0xa252), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 419 { PCI_VDEVICE(INTEL, 0xa256), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 420 { PCI_VDEVICE(INTEL, 0xa356), board_ahci_pcs_quirk }, /* Cannon Lake PCH-H RAID */ 421 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci_pcs_quirk }, /* Comet Lake-H RAID */ 422 { PCI_VDEVICE(INTEL, 0xa386), board_ahci_pcs_quirk }, /* Comet Lake PCH-V RAID */ 423 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_pcs_quirk }, /* Bay Trail AHCI */ 424 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_pcs_quirk_no_devslp }, /* Bay Trail AHCI */ 425 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_pcs_quirk }, /* Cherry Tr. AHCI */ 426 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_pcs_quirk }, /* ApolloLake AHCI */ 427 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_pcs_quirk }, /* Ice Lake LP AHCI */ 428 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_pcs_quirk }, /* Comet Lake PCH-U AHCI */ 429 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_pcs_quirk }, /* Comet Lake PCH RAID */ 430 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */ 431 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_pcs_quirk }, /* Elkhart Lake AHCI */ 432 { PCI_VDEVICE(INTEL, 0x7ae2), board_ahci_pcs_quirk }, /* Alder Lake-P AHCI */ 433 434 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 435 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 436 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 437 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 438 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 439 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 440 /* May need to update quirk_jmicron_async_suspend() for additions */ 441 442 /* ATI */ 443 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 444 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 445 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 446 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 447 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 448 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 449 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 450 451 /* Amazon's Annapurna Labs support */ 452 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031), 453 .class = PCI_CLASS_STORAGE_SATA_AHCI, 454 .class_mask = 0xffffff, 455 board_ahci_al }, 456 /* AMD */ 457 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 458 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */ 459 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 460 { PCI_VDEVICE(AMD, 0x7901), board_ahci }, /* AMD Green Sardine */ 461 /* AMD is using RAID class only for ahci controllers */ 462 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 463 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 464 465 /* Dell S140/S150 */ 466 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID, 467 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci_pcs_quirk }, 468 469 /* VIA */ 470 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 471 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 472 473 /* NVIDIA */ 474 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 475 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 476 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 477 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 478 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 479 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 480 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 481 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 482 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 483 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 484 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 485 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 486 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 487 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 488 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 489 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 490 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 491 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 492 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 493 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 494 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 495 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 496 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 497 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 498 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 499 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 500 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 501 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 502 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 503 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 504 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 505 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 506 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 507 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 508 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 509 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 510 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 511 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 512 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 513 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 514 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 515 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 516 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 517 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 518 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 519 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 520 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 521 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 522 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 523 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 524 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 525 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 526 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 527 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 528 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 529 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 530 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 531 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 532 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 533 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 534 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 535 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 536 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 537 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 538 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 539 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 540 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 541 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 542 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 543 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 544 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 545 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 546 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 547 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 548 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 549 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 550 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 551 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 552 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 553 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 554 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 555 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 556 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 557 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 558 559 /* SiS */ 560 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 561 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 562 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 563 564 /* ST Microelectronics */ 565 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 566 567 /* Marvell */ 568 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 569 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 570 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 571 .class = PCI_CLASS_STORAGE_SATA_AHCI, 572 .class_mask = 0xffffff, 573 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 574 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 575 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 576 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 577 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 578 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 579 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 580 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 581 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 582 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 583 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 584 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 585 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 586 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 587 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 588 .driver_data = board_ahci_yes_fbs }, 589 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ 590 .driver_data = board_ahci_yes_fbs }, 591 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 592 .driver_data = board_ahci_yes_fbs }, 593 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 594 .driver_data = board_ahci_yes_fbs }, 595 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235), 596 .driver_data = board_ahci_no_debounce_delay }, 597 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ 598 .driver_data = board_ahci_yes_fbs }, 599 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ 600 .driver_data = board_ahci_yes_fbs }, 601 602 /* Promise */ 603 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 604 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 605 606 /* ASMedia */ 607 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci_43bit_dma }, /* ASM1060 */ 608 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci_43bit_dma }, /* ASM1060 */ 609 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */ 610 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma }, /* ASM1061/1062 */ 611 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci_43bit_dma }, /* ASM1061R */ 612 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci_43bit_dma }, /* ASM1062R */ 613 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci_43bit_dma }, /* ASM1062+JMB575 */ 614 { PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci }, /* ASM1062A */ 615 { PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */ 616 { PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci }, /* ASM1164 */ 617 { PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci }, /* ASM1165 */ 618 { PCI_VDEVICE(ASMEDIA, 0x1166), board_ahci }, /* ASM1166 */ 619 620 /* 621 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 622 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 623 */ 624 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_no_msi }, 625 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_no_msi }, 626 627 /* Enmotus */ 628 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 629 630 /* Loongson */ 631 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci }, 632 633 /* Generic, PCI class code for AHCI */ 634 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 635 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 636 637 { } /* terminate list */ 638 }; 639 640 static const struct dev_pm_ops ahci_pci_pm_ops = { 641 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) 642 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, 643 ahci_pci_device_runtime_resume, NULL) 644 }; 645 646 static struct pci_driver ahci_pci_driver = { 647 .name = DRV_NAME, 648 .id_table = ahci_pci_tbl, 649 .probe = ahci_init_one, 650 .remove = ahci_remove_one, 651 .shutdown = ahci_shutdown_one, 652 .driver = { 653 .pm = &ahci_pci_pm_ops, 654 }, 655 }; 656 657 #if IS_ENABLED(CONFIG_PATA_MARVELL) 658 static int marvell_enable; 659 #else 660 static int marvell_enable = 1; 661 #endif 662 module_param(marvell_enable, int, 0644); 663 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 664 665 static int mobile_lpm_policy = -1; 666 module_param(mobile_lpm_policy, int, 0644); 667 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); 668 669 static void ahci_pci_save_initial_config(struct pci_dev *pdev, 670 struct ahci_host_priv *hpriv) 671 { 672 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 673 dev_info(&pdev->dev, "JMB361 has only one port\n"); 674 hpriv->saved_port_map = 1; 675 } 676 677 /* 678 * Temporary Marvell 6145 hack: PATA port presence 679 * is asserted through the standard AHCI port 680 * presence register, as bit 4 (counting from 0) 681 */ 682 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 683 if (pdev->device == 0x6121) 684 hpriv->mask_port_map = 0x3; 685 else 686 hpriv->mask_port_map = 0xf; 687 dev_info(&pdev->dev, 688 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 689 } 690 691 ahci_save_initial_config(&pdev->dev, hpriv); 692 } 693 694 static int ahci_pci_reset_controller(struct ata_host *host) 695 { 696 struct pci_dev *pdev = to_pci_dev(host->dev); 697 struct ahci_host_priv *hpriv = host->private_data; 698 int rc; 699 700 rc = ahci_reset_controller(host); 701 if (rc) 702 return rc; 703 704 /* 705 * If platform firmware failed to enable ports, try to enable 706 * them here. 707 */ 708 ahci_intel_pcs_quirk(pdev, hpriv); 709 710 return 0; 711 } 712 713 static void ahci_pci_init_controller(struct ata_host *host) 714 { 715 struct ahci_host_priv *hpriv = host->private_data; 716 struct pci_dev *pdev = to_pci_dev(host->dev); 717 void __iomem *port_mmio; 718 u32 tmp; 719 int mv; 720 721 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 722 if (pdev->device == 0x6121) 723 mv = 2; 724 else 725 mv = 4; 726 port_mmio = __ahci_port_base(hpriv, mv); 727 728 writel(0, port_mmio + PORT_IRQ_MASK); 729 730 /* clear port IRQ */ 731 tmp = readl(port_mmio + PORT_IRQ_STAT); 732 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp); 733 if (tmp) 734 writel(tmp, port_mmio + PORT_IRQ_STAT); 735 } 736 737 ahci_init_controller(host); 738 } 739 740 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 741 unsigned long deadline) 742 { 743 struct ata_port *ap = link->ap; 744 struct ahci_host_priv *hpriv = ap->host->private_data; 745 bool online; 746 int rc; 747 748 hpriv->stop_engine(ap); 749 750 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 751 deadline, &online, NULL); 752 753 hpriv->start_engine(ap); 754 755 /* vt8251 doesn't clear BSY on signature FIS reception, 756 * request follow-up softreset. 757 */ 758 return online ? -EAGAIN : rc; 759 } 760 761 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 762 unsigned long deadline) 763 { 764 struct ata_port *ap = link->ap; 765 struct ahci_port_priv *pp = ap->private_data; 766 struct ahci_host_priv *hpriv = ap->host->private_data; 767 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 768 struct ata_taskfile tf; 769 bool online; 770 int rc; 771 772 hpriv->stop_engine(ap); 773 774 /* clear D2H reception area to properly wait for D2H FIS */ 775 ata_tf_init(link->device, &tf); 776 tf.status = ATA_BUSY; 777 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 778 779 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 780 deadline, &online, NULL); 781 782 hpriv->start_engine(ap); 783 784 /* The pseudo configuration device on SIMG4726 attached to 785 * ASUS P5W-DH Deluxe doesn't send signature FIS after 786 * hardreset if no device is attached to the first downstream 787 * port && the pseudo device locks up on SRST w/ PMP==0. To 788 * work around this, wait for !BSY only briefly. If BSY isn't 789 * cleared, perform CLO and proceed to IDENTIFY (achieved by 790 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 791 * 792 * Wait for two seconds. Devices attached to downstream port 793 * which can't process the following IDENTIFY after this will 794 * have to be reset again. For most cases, this should 795 * suffice while making probing snappish enough. 796 */ 797 if (online) { 798 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 799 ahci_check_ready); 800 if (rc) 801 ahci_kick_engine(ap); 802 } 803 return rc; 804 } 805 806 /* 807 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 808 * 809 * It has been observed with some SSDs that the timing of events in the 810 * link synchronization phase can leave the port in a state that can not 811 * be recovered by a SATA-hard-reset alone. The failing signature is 812 * SStatus.DET stuck at 1 ("Device presence detected but Phy 813 * communication not established"). It was found that unloading and 814 * reloading the driver when this problem occurs allows the drive 815 * connection to be recovered (DET advanced to 0x3). The critical 816 * component of reloading the driver is that the port state machines are 817 * reset by bouncing "port enable" in the AHCI PCS configuration 818 * register. So, reproduce that effect by bouncing a port whenever we 819 * see DET==1 after a reset. 820 */ 821 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 822 unsigned long deadline) 823 { 824 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context); 825 struct ata_port *ap = link->ap; 826 struct ahci_port_priv *pp = ap->private_data; 827 struct ahci_host_priv *hpriv = ap->host->private_data; 828 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 829 unsigned long tmo = deadline - jiffies; 830 struct ata_taskfile tf; 831 bool online; 832 int rc, i; 833 834 hpriv->stop_engine(ap); 835 836 for (i = 0; i < 2; i++) { 837 u16 val; 838 u32 sstatus; 839 int port = ap->port_no; 840 struct ata_host *host = ap->host; 841 struct pci_dev *pdev = to_pci_dev(host->dev); 842 843 /* clear D2H reception area to properly wait for D2H FIS */ 844 ata_tf_init(link->device, &tf); 845 tf.status = ATA_BUSY; 846 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 847 848 rc = sata_link_hardreset(link, timing, deadline, &online, 849 ahci_check_ready); 850 851 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 852 (sstatus & 0xf) != 1) 853 break; 854 855 ata_link_info(link, "avn bounce port%d\n", port); 856 857 pci_read_config_word(pdev, 0x92, &val); 858 val &= ~(1 << port); 859 pci_write_config_word(pdev, 0x92, val); 860 ata_msleep(ap, 1000); 861 val |= 1 << port; 862 pci_write_config_word(pdev, 0x92, val); 863 deadline += tmo; 864 } 865 866 hpriv->start_engine(ap); 867 868 if (online) 869 *class = ahci_dev_classify(ap); 870 871 return rc; 872 } 873 874 875 #ifdef CONFIG_PM 876 static void ahci_pci_disable_interrupts(struct ata_host *host) 877 { 878 struct ahci_host_priv *hpriv = host->private_data; 879 void __iomem *mmio = hpriv->mmio; 880 u32 ctl; 881 882 /* AHCI spec rev1.1 section 8.3.3: 883 * Software must disable interrupts prior to requesting a 884 * transition of the HBA to D3 state. 885 */ 886 ctl = readl(mmio + HOST_CTL); 887 ctl &= ~HOST_IRQ_EN; 888 writel(ctl, mmio + HOST_CTL); 889 readl(mmio + HOST_CTL); /* flush */ 890 } 891 892 static int ahci_pci_device_runtime_suspend(struct device *dev) 893 { 894 struct pci_dev *pdev = to_pci_dev(dev); 895 struct ata_host *host = pci_get_drvdata(pdev); 896 897 ahci_pci_disable_interrupts(host); 898 return 0; 899 } 900 901 static int ahci_pci_device_runtime_resume(struct device *dev) 902 { 903 struct pci_dev *pdev = to_pci_dev(dev); 904 struct ata_host *host = pci_get_drvdata(pdev); 905 int rc; 906 907 rc = ahci_pci_reset_controller(host); 908 if (rc) 909 return rc; 910 ahci_pci_init_controller(host); 911 return 0; 912 } 913 914 #ifdef CONFIG_PM_SLEEP 915 static int ahci_pci_device_suspend(struct device *dev) 916 { 917 struct pci_dev *pdev = to_pci_dev(dev); 918 struct ata_host *host = pci_get_drvdata(pdev); 919 struct ahci_host_priv *hpriv = host->private_data; 920 921 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 922 dev_err(&pdev->dev, 923 "BIOS update required for suspend/resume\n"); 924 return -EIO; 925 } 926 927 ahci_pci_disable_interrupts(host); 928 ata_host_suspend(host, PMSG_SUSPEND); 929 return 0; 930 } 931 932 static int ahci_pci_device_resume(struct device *dev) 933 { 934 struct pci_dev *pdev = to_pci_dev(dev); 935 struct ata_host *host = pci_get_drvdata(pdev); 936 int rc; 937 938 /* Apple BIOS helpfully mangles the registers on resume */ 939 if (is_mcp89_apple(pdev)) 940 ahci_mcp89_apple_enable(pdev); 941 942 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 943 rc = ahci_pci_reset_controller(host); 944 if (rc) 945 return rc; 946 947 ahci_pci_init_controller(host); 948 } 949 950 ata_host_resume(host); 951 952 return 0; 953 } 954 #endif 955 956 #endif /* CONFIG_PM */ 957 958 static int ahci_configure_dma_masks(struct pci_dev *pdev, 959 struct ahci_host_priv *hpriv) 960 { 961 int dma_bits; 962 int rc; 963 964 if (hpriv->cap & HOST_CAP_64) { 965 dma_bits = 64; 966 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY) 967 dma_bits = 43; 968 } else { 969 dma_bits = 32; 970 } 971 972 /* 973 * If the device fixup already set the dma_mask to some non-standard 974 * value, don't extend it here. This happens on STA2X11, for example. 975 * 976 * XXX: manipulating the DMA mask from platform code is completely 977 * bogus, platform code should use dev->bus_dma_limit instead.. 978 */ 979 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 980 return 0; 981 982 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits)); 983 if (rc) 984 dev_err(&pdev->dev, "DMA enable failed\n"); 985 return rc; 986 } 987 988 static void ahci_pci_print_info(struct ata_host *host) 989 { 990 struct pci_dev *pdev = to_pci_dev(host->dev); 991 u16 cc; 992 const char *scc_s; 993 994 pci_read_config_word(pdev, 0x0a, &cc); 995 if (cc == PCI_CLASS_STORAGE_IDE) 996 scc_s = "IDE"; 997 else if (cc == PCI_CLASS_STORAGE_SATA) 998 scc_s = "SATA"; 999 else if (cc == PCI_CLASS_STORAGE_RAID) 1000 scc_s = "RAID"; 1001 else 1002 scc_s = "unknown"; 1003 1004 ahci_print_info(host, scc_s); 1005 } 1006 1007 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 1008 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 1009 * support PMP and the 4726 either directly exports the device 1010 * attached to the first downstream port or acts as a hardware storage 1011 * controller and emulate a single ATA device (can be RAID 0/1 or some 1012 * other configuration). 1013 * 1014 * When there's no device attached to the first downstream port of the 1015 * 4726, "Config Disk" appears, which is a pseudo ATA device to 1016 * configure the 4726. However, ATA emulation of the device is very 1017 * lame. It doesn't send signature D2H Reg FIS after the initial 1018 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 1019 * 1020 * The following function works around the problem by always using 1021 * hardreset on the port and not depending on receiving signature FIS 1022 * afterward. If signature FIS isn't received soon, ATA class is 1023 * assumed without follow-up softreset. 1024 */ 1025 static void ahci_p5wdh_workaround(struct ata_host *host) 1026 { 1027 static const struct dmi_system_id sysids[] = { 1028 { 1029 .ident = "P5W DH Deluxe", 1030 .matches = { 1031 DMI_MATCH(DMI_SYS_VENDOR, 1032 "ASUSTEK COMPUTER INC"), 1033 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 1034 }, 1035 }, 1036 { } 1037 }; 1038 struct pci_dev *pdev = to_pci_dev(host->dev); 1039 1040 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 1041 dmi_check_system(sysids)) { 1042 struct ata_port *ap = host->ports[1]; 1043 1044 dev_info(&pdev->dev, 1045 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 1046 1047 ap->ops = &ahci_p5wdh_ops; 1048 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 1049 } 1050 } 1051 1052 /* 1053 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 1054 * booting in BIOS compatibility mode. We restore the registers but not ID. 1055 */ 1056 static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 1057 { 1058 u32 val; 1059 1060 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 1061 1062 pci_read_config_dword(pdev, 0xf8, &val); 1063 val |= 1 << 0x1b; 1064 /* the following changes the device ID, but appears not to affect function */ 1065 /* val = (val & ~0xf0000000) | 0x80000000; */ 1066 pci_write_config_dword(pdev, 0xf8, val); 1067 1068 pci_read_config_dword(pdev, 0x54c, &val); 1069 val |= 1 << 0xc; 1070 pci_write_config_dword(pdev, 0x54c, val); 1071 1072 pci_read_config_dword(pdev, 0x4a4, &val); 1073 val &= 0xff; 1074 val |= 0x01060100; 1075 pci_write_config_dword(pdev, 0x4a4, val); 1076 1077 pci_read_config_dword(pdev, 0x54c, &val); 1078 val &= ~(1 << 0xc); 1079 pci_write_config_dword(pdev, 0x54c, val); 1080 1081 pci_read_config_dword(pdev, 0xf8, &val); 1082 val &= ~(1 << 0x1b); 1083 pci_write_config_dword(pdev, 0xf8, val); 1084 } 1085 1086 static bool is_mcp89_apple(struct pci_dev *pdev) 1087 { 1088 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1089 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1090 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1091 pdev->subsystem_device == 0xcb89; 1092 } 1093 1094 /* only some SB600 ahci controllers can do 64bit DMA */ 1095 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 1096 { 1097 static const struct dmi_system_id sysids[] = { 1098 /* 1099 * The oldest version known to be broken is 0901 and 1100 * working is 1501 which was released on 2007-10-26. 1101 * Enable 64bit DMA on 1501 and anything newer. 1102 * 1103 * Please read bko#9412 for more info. 1104 */ 1105 { 1106 .ident = "ASUS M2A-VM", 1107 .matches = { 1108 DMI_MATCH(DMI_BOARD_VENDOR, 1109 "ASUSTeK Computer INC."), 1110 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 1111 }, 1112 .driver_data = "20071026", /* yyyymmdd */ 1113 }, 1114 /* 1115 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 1116 * support 64bit DMA. 1117 * 1118 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1119 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1120 * This spelling mistake was fixed in BIOS version 1.5, so 1121 * 1.5 and later have the Manufacturer as 1122 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1123 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1124 * 1125 * BIOS versions earlier than 1.9 had a Board Product Name 1126 * DMI field of "MS-7376". This was changed to be 1127 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1128 * match on DMI_BOARD_NAME of "MS-7376". 1129 */ 1130 { 1131 .ident = "MSI K9A2 Platinum", 1132 .matches = { 1133 DMI_MATCH(DMI_BOARD_VENDOR, 1134 "MICRO-STAR INTER"), 1135 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1136 }, 1137 }, 1138 /* 1139 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1140 * 64bit DMA. 1141 * 1142 * This board also had the typo mentioned above in the 1143 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1144 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1145 */ 1146 { 1147 .ident = "MSI K9AGM2", 1148 .matches = { 1149 DMI_MATCH(DMI_BOARD_VENDOR, 1150 "MICRO-STAR INTER"), 1151 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1152 }, 1153 }, 1154 /* 1155 * All BIOS versions for the Asus M3A support 64bit DMA. 1156 * (all release versions from 0301 to 1206 were tested) 1157 */ 1158 { 1159 .ident = "ASUS M3A", 1160 .matches = { 1161 DMI_MATCH(DMI_BOARD_VENDOR, 1162 "ASUSTeK Computer INC."), 1163 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1164 }, 1165 }, 1166 { } 1167 }; 1168 const struct dmi_system_id *match; 1169 int year, month, date; 1170 char buf[9]; 1171 1172 match = dmi_first_match(sysids); 1173 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1174 !match) 1175 return false; 1176 1177 if (!match->driver_data) 1178 goto enable_64bit; 1179 1180 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1181 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1182 1183 if (strcmp(buf, match->driver_data) >= 0) 1184 goto enable_64bit; 1185 else { 1186 dev_warn(&pdev->dev, 1187 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1188 match->ident); 1189 return false; 1190 } 1191 1192 enable_64bit: 1193 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1194 return true; 1195 } 1196 1197 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1198 { 1199 static const struct dmi_system_id broken_systems[] = { 1200 { 1201 .ident = "HP Compaq nx6310", 1202 .matches = { 1203 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1204 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1205 }, 1206 /* PCI slot number of the controller */ 1207 .driver_data = (void *)0x1FUL, 1208 }, 1209 { 1210 .ident = "HP Compaq 6720s", 1211 .matches = { 1212 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1213 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1214 }, 1215 /* PCI slot number of the controller */ 1216 .driver_data = (void *)0x1FUL, 1217 }, 1218 1219 { } /* terminate list */ 1220 }; 1221 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1222 1223 if (dmi) { 1224 unsigned long slot = (unsigned long)dmi->driver_data; 1225 /* apply the quirk only to on-board controllers */ 1226 return slot == PCI_SLOT(pdev->devfn); 1227 } 1228 1229 return false; 1230 } 1231 1232 static bool ahci_broken_suspend(struct pci_dev *pdev) 1233 { 1234 static const struct dmi_system_id sysids[] = { 1235 /* 1236 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1237 * to the harddisk doesn't become online after 1238 * resuming from STR. Warn and fail suspend. 1239 * 1240 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1241 * 1242 * Use dates instead of versions to match as HP is 1243 * apparently recycling both product and version 1244 * strings. 1245 * 1246 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1247 */ 1248 { 1249 .ident = "dv4", 1250 .matches = { 1251 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1252 DMI_MATCH(DMI_PRODUCT_NAME, 1253 "HP Pavilion dv4 Notebook PC"), 1254 }, 1255 .driver_data = "20090105", /* F.30 */ 1256 }, 1257 { 1258 .ident = "dv5", 1259 .matches = { 1260 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1261 DMI_MATCH(DMI_PRODUCT_NAME, 1262 "HP Pavilion dv5 Notebook PC"), 1263 }, 1264 .driver_data = "20090506", /* F.16 */ 1265 }, 1266 { 1267 .ident = "dv6", 1268 .matches = { 1269 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1270 DMI_MATCH(DMI_PRODUCT_NAME, 1271 "HP Pavilion dv6 Notebook PC"), 1272 }, 1273 .driver_data = "20090423", /* F.21 */ 1274 }, 1275 { 1276 .ident = "HDX18", 1277 .matches = { 1278 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1279 DMI_MATCH(DMI_PRODUCT_NAME, 1280 "HP HDX18 Notebook PC"), 1281 }, 1282 .driver_data = "20090430", /* F.23 */ 1283 }, 1284 /* 1285 * Acer eMachines G725 has the same problem. BIOS 1286 * V1.03 is known to be broken. V3.04 is known to 1287 * work. Between, there are V1.06, V2.06 and V3.03 1288 * that we don't have much idea about. For now, 1289 * blacklist anything older than V3.04. 1290 * 1291 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1292 */ 1293 { 1294 .ident = "G725", 1295 .matches = { 1296 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1297 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1298 }, 1299 .driver_data = "20091216", /* V3.04 */ 1300 }, 1301 { } /* terminate list */ 1302 }; 1303 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1304 int year, month, date; 1305 char buf[9]; 1306 1307 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1308 return false; 1309 1310 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1311 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1312 1313 return strcmp(buf, dmi->driver_data) < 0; 1314 } 1315 1316 static bool ahci_broken_lpm(struct pci_dev *pdev) 1317 { 1318 static const struct dmi_system_id sysids[] = { 1319 /* Various Lenovo 50 series have LPM issues with older BIOSen */ 1320 { 1321 .matches = { 1322 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1323 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), 1324 }, 1325 .driver_data = "20180406", /* 1.31 */ 1326 }, 1327 { 1328 .matches = { 1329 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1330 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), 1331 }, 1332 .driver_data = "20180420", /* 1.28 */ 1333 }, 1334 { 1335 .matches = { 1336 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1337 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), 1338 }, 1339 .driver_data = "20180315", /* 1.33 */ 1340 }, 1341 { 1342 .matches = { 1343 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1344 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), 1345 }, 1346 /* 1347 * Note date based on release notes, 2.35 has been 1348 * reported to be good, but I've been unable to get 1349 * a hold of the reporter to get the DMI BIOS date. 1350 * TODO: fix this. 1351 */ 1352 .driver_data = "20180310", /* 2.35 */ 1353 }, 1354 { } /* terminate list */ 1355 }; 1356 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1357 int year, month, date; 1358 char buf[9]; 1359 1360 if (!dmi) 1361 return false; 1362 1363 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1364 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1365 1366 return strcmp(buf, dmi->driver_data) < 0; 1367 } 1368 1369 static bool ahci_broken_online(struct pci_dev *pdev) 1370 { 1371 #define ENCODE_BUSDEVFN(bus, slot, func) \ 1372 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1373 static const struct dmi_system_id sysids[] = { 1374 /* 1375 * There are several gigabyte boards which use 1376 * SIMG5723s configured as hardware RAID. Certain 1377 * 5723 firmware revisions shipped there keep the link 1378 * online but fail to answer properly to SRST or 1379 * IDENTIFY when no device is attached downstream 1380 * causing libata to retry quite a few times leading 1381 * to excessive detection delay. 1382 * 1383 * As these firmwares respond to the second reset try 1384 * with invalid device signature, considering unknown 1385 * sig as offline works around the problem acceptably. 1386 */ 1387 { 1388 .ident = "EP45-DQ6", 1389 .matches = { 1390 DMI_MATCH(DMI_BOARD_VENDOR, 1391 "Gigabyte Technology Co., Ltd."), 1392 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1393 }, 1394 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1395 }, 1396 { 1397 .ident = "EP45-DS5", 1398 .matches = { 1399 DMI_MATCH(DMI_BOARD_VENDOR, 1400 "Gigabyte Technology Co., Ltd."), 1401 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1402 }, 1403 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1404 }, 1405 { } /* terminate list */ 1406 }; 1407 #undef ENCODE_BUSDEVFN 1408 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1409 unsigned int val; 1410 1411 if (!dmi) 1412 return false; 1413 1414 val = (unsigned long)dmi->driver_data; 1415 1416 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1417 } 1418 1419 #ifdef CONFIG_ATA_ACPI 1420 static void ahci_gtf_filter_workaround(struct ata_host *host) 1421 { 1422 static const struct dmi_system_id sysids[] = { 1423 /* 1424 * Aspire 3810T issues a bunch of SATA enable commands 1425 * via _GTF including an invalid one and one which is 1426 * rejected by the device. Among the successful ones 1427 * is FPDMA non-zero offset enable which when enabled 1428 * only on the drive side leads to NCQ command 1429 * failures. Filter it out. 1430 */ 1431 { 1432 .ident = "Aspire 3810T", 1433 .matches = { 1434 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1435 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1436 }, 1437 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1438 }, 1439 { } 1440 }; 1441 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1442 unsigned int filter; 1443 int i; 1444 1445 if (!dmi) 1446 return; 1447 1448 filter = (unsigned long)dmi->driver_data; 1449 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1450 filter, dmi->ident); 1451 1452 for (i = 0; i < host->n_ports; i++) { 1453 struct ata_port *ap = host->ports[i]; 1454 struct ata_link *link; 1455 struct ata_device *dev; 1456 1457 ata_for_each_link(link, ap, EDGE) 1458 ata_for_each_dev(dev, link, ALL) 1459 dev->gtf_filter |= filter; 1460 } 1461 } 1462 #else 1463 static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1464 {} 1465 #endif 1466 1467 /* 1468 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected 1469 * as DUMMY, or detected but eventually get a "link down" and never get up 1470 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the 1471 * port_map may hold a value of 0x00. 1472 * 1473 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports 1474 * and can significantly reduce the occurrence of the problem. 1475 * 1476 * https://bugzilla.kernel.org/show_bug.cgi?id=189471 1477 */ 1478 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, 1479 struct pci_dev *pdev) 1480 { 1481 static const struct dmi_system_id sysids[] = { 1482 { 1483 .ident = "Acer Switch Alpha 12", 1484 .matches = { 1485 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1486 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") 1487 }, 1488 }, 1489 { } 1490 }; 1491 1492 if (dmi_check_system(sysids)) { 1493 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); 1494 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { 1495 hpriv->port_map = 0x7; 1496 hpriv->cap = 0xC734FF02; 1497 } 1498 } 1499 } 1500 1501 #ifdef CONFIG_ARM64 1502 /* 1503 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. 1504 * Workaround is to make sure all pending IRQs are served before leaving 1505 * handler. 1506 */ 1507 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) 1508 { 1509 struct ata_host *host = dev_instance; 1510 struct ahci_host_priv *hpriv; 1511 unsigned int rc = 0; 1512 void __iomem *mmio; 1513 u32 irq_stat, irq_masked; 1514 unsigned int handled = 1; 1515 1516 hpriv = host->private_data; 1517 mmio = hpriv->mmio; 1518 irq_stat = readl(mmio + HOST_IRQ_STAT); 1519 if (!irq_stat) 1520 return IRQ_NONE; 1521 1522 do { 1523 irq_masked = irq_stat & hpriv->port_map; 1524 spin_lock(&host->lock); 1525 rc = ahci_handle_port_intr(host, irq_masked); 1526 if (!rc) 1527 handled = 0; 1528 writel(irq_stat, mmio + HOST_IRQ_STAT); 1529 irq_stat = readl(mmio + HOST_IRQ_STAT); 1530 spin_unlock(&host->lock); 1531 } while (irq_stat); 1532 1533 return IRQ_RETVAL(handled); 1534 } 1535 #endif 1536 1537 static void ahci_remap_check(struct pci_dev *pdev, int bar, 1538 struct ahci_host_priv *hpriv) 1539 { 1540 int i; 1541 u32 cap; 1542 1543 /* 1544 * Check if this device might have remapped nvme devices. 1545 */ 1546 if (pdev->vendor != PCI_VENDOR_ID_INTEL || 1547 pci_resource_len(pdev, bar) < SZ_512K || 1548 bar != AHCI_PCI_BAR_STANDARD || 1549 !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) 1550 return; 1551 1552 cap = readq(hpriv->mmio + AHCI_REMAP_CAP); 1553 for (i = 0; i < AHCI_MAX_REMAP; i++) { 1554 if ((cap & (1 << i)) == 0) 1555 continue; 1556 if (readl(hpriv->mmio + ahci_remap_dcc(i)) 1557 != PCI_CLASS_STORAGE_EXPRESS) 1558 continue; 1559 1560 /* We've found a remapped device */ 1561 hpriv->remapped_nvme++; 1562 } 1563 1564 if (!hpriv->remapped_nvme) 1565 return; 1566 1567 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n", 1568 hpriv->remapped_nvme); 1569 dev_warn(&pdev->dev, 1570 "Switch your BIOS from RAID to AHCI mode to use them.\n"); 1571 1572 /* 1573 * Don't rely on the msi-x capability in the remap case, 1574 * share the legacy interrupt across ahci and remapped devices. 1575 */ 1576 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1577 } 1578 1579 static int ahci_get_irq_vector(struct ata_host *host, int port) 1580 { 1581 return pci_irq_vector(to_pci_dev(host->dev), port); 1582 } 1583 1584 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, 1585 struct ahci_host_priv *hpriv) 1586 { 1587 int nvec; 1588 1589 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1590 return -ENODEV; 1591 1592 /* 1593 * If number of MSIs is less than number of ports then Sharing Last 1594 * Message mode could be enforced. In this case assume that advantage 1595 * of multipe MSIs is negated and use single MSI mode instead. 1596 */ 1597 if (n_ports > 1) { 1598 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, 1599 PCI_IRQ_MSIX | PCI_IRQ_MSI); 1600 if (nvec > 0) { 1601 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { 1602 hpriv->get_irq_vector = ahci_get_irq_vector; 1603 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1604 return nvec; 1605 } 1606 1607 /* 1608 * Fallback to single MSI mode if the controller 1609 * enforced MRSM mode. 1610 */ 1611 printk(KERN_INFO 1612 "ahci: MRSM is on, fallback to single MSI\n"); 1613 pci_free_irq_vectors(pdev); 1614 } 1615 } 1616 1617 /* 1618 * If the host is not capable of supporting per-port vectors, fall 1619 * back to single MSI before finally attempting single MSI-X. 1620 */ 1621 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1622 if (nvec == 1) 1623 return nvec; 1624 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); 1625 } 1626 1627 static void ahci_mark_external_port(struct ata_port *ap) 1628 { 1629 struct ahci_host_priv *hpriv = ap->host->private_data; 1630 void __iomem *port_mmio = ahci_port_base(ap); 1631 u32 tmp; 1632 1633 /* mark external ports (hotplug-capable, eSATA) */ 1634 tmp = readl(port_mmio + PORT_CMD); 1635 if (((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) || 1636 (tmp & PORT_CMD_HPCP)) 1637 ap->pflags |= ATA_PFLAG_EXTERNAL; 1638 } 1639 1640 static void ahci_update_initial_lpm_policy(struct ata_port *ap) 1641 { 1642 struct ahci_host_priv *hpriv = ap->host->private_data; 1643 int policy = CONFIG_SATA_MOBILE_LPM_POLICY; 1644 1645 /* 1646 * AHCI contains a known incompatibility between LPM and hot-plug 1647 * removal events, see 7.3.1 Hot Plug Removal Detection and Power 1648 * Management Interaction in AHCI 1.3.1. Therefore, do not enable 1649 * LPM if the port advertises itself as an external port. 1650 */ 1651 if (ap->pflags & ATA_PFLAG_EXTERNAL) 1652 return; 1653 1654 /* user modified policy via module param */ 1655 if (mobile_lpm_policy != -1) { 1656 policy = mobile_lpm_policy; 1657 goto update_policy; 1658 } 1659 1660 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) { 1661 if (hpriv->cap & HOST_CAP_PART) 1662 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL; 1663 else if (hpriv->cap & HOST_CAP_SSC) 1664 policy = ATA_LPM_MIN_POWER; 1665 } 1666 1667 update_policy: 1668 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER) 1669 ap->target_lpm_policy = policy; 1670 } 1671 1672 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv) 1673 { 1674 u16 tmp16; 1675 1676 if (!(hpriv->flags & AHCI_HFLAG_INTEL_PCS_QUIRK)) 1677 return; 1678 1679 /* 1680 * port_map is determined from PORTS_IMPL PCI register which is 1681 * implemented as write or write-once register. If the register 1682 * isn't programmed, ahci automatically generates it from number 1683 * of ports, which is good enough for PCS programming. It is 1684 * otherwise expected that platform firmware enables the ports 1685 * before the OS boots. 1686 */ 1687 pci_read_config_word(pdev, PCS_6, &tmp16); 1688 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 1689 tmp16 |= hpriv->port_map; 1690 pci_write_config_word(pdev, PCS_6, tmp16); 1691 } 1692 } 1693 1694 static ssize_t remapped_nvme_show(struct device *dev, 1695 struct device_attribute *attr, 1696 char *buf) 1697 { 1698 struct ata_host *host = dev_get_drvdata(dev); 1699 struct ahci_host_priv *hpriv = host->private_data; 1700 1701 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme); 1702 } 1703 1704 static DEVICE_ATTR_RO(remapped_nvme); 1705 1706 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1707 { 1708 unsigned int board_id = ent->driver_data; 1709 struct ata_port_info pi = ahci_port_info[board_id]; 1710 const struct ata_port_info *ppi[] = { &pi, NULL }; 1711 struct device *dev = &pdev->dev; 1712 struct ahci_host_priv *hpriv; 1713 struct ata_host *host; 1714 int n_ports, i, rc; 1715 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1716 1717 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1718 1719 ata_print_version_once(&pdev->dev, DRV_VERSION); 1720 1721 /* The AHCI driver can only drive the SATA ports, the PATA driver 1722 can drive them all so if both drivers are selected make sure 1723 AHCI stays out of the way */ 1724 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1725 return -ENODEV; 1726 1727 /* Apple BIOS on MCP89 prevents us using AHCI */ 1728 if (is_mcp89_apple(pdev)) 1729 ahci_mcp89_apple_enable(pdev); 1730 1731 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1732 * At the moment, we can only use the AHCI mode. Let the users know 1733 * that for SAS drives they're out of luck. 1734 */ 1735 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1736 dev_info(&pdev->dev, 1737 "PDC42819 can only drive SATA devices with this driver\n"); 1738 1739 /* Some devices use non-standard BARs */ 1740 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1741 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1742 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1743 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1744 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { 1745 if (pdev->device == 0xa01c) 1746 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; 1747 if (pdev->device == 0xa084) 1748 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; 1749 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) { 1750 if (pdev->device == 0x7a08) 1751 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON; 1752 } 1753 1754 /* acquire resources */ 1755 rc = pcim_enable_device(pdev); 1756 if (rc) 1757 return rc; 1758 1759 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1760 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1761 u8 map; 1762 1763 /* ICH6s share the same PCI ID for both piix and ahci 1764 * modes. Enabling ahci mode while MAP indicates 1765 * combined mode is a bad idea. Yield to ata_piix. 1766 */ 1767 pci_read_config_byte(pdev, ICH_MAP, &map); 1768 if (map & 0x3) { 1769 dev_info(&pdev->dev, 1770 "controller is in combined mode, can't enable AHCI mode\n"); 1771 return -ENODEV; 1772 } 1773 } 1774 1775 /* AHCI controllers often implement SFF compatible interface. 1776 * Grab all PCI BARs just in case. 1777 */ 1778 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1779 if (rc == -EBUSY) 1780 pcim_pin_device(pdev); 1781 if (rc) 1782 return rc; 1783 1784 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1785 if (!hpriv) 1786 return -ENOMEM; 1787 hpriv->flags |= (unsigned long)pi.private_data; 1788 1789 /* MCP65 revision A1 and A2 can't do MSI */ 1790 if (board_id == board_ahci_mcp65 && 1791 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1792 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1793 1794 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1795 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1796 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1797 1798 /* only some SB600s can do 64bit DMA */ 1799 if (ahci_sb600_enable_64bit(pdev)) 1800 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1801 1802 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1803 1804 /* detect remapped nvme devices */ 1805 ahci_remap_check(pdev, ahci_pci_bar, hpriv); 1806 1807 sysfs_add_file_to_group(&pdev->dev.kobj, 1808 &dev_attr_remapped_nvme.attr, 1809 NULL); 1810 1811 #ifdef CONFIG_ARM64 1812 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI && 1813 pdev->device == 0xa235 && 1814 pdev->revision < 0x30) 1815 hpriv->flags |= AHCI_HFLAG_NO_SXS; 1816 1817 if (pdev->vendor == 0x177d && pdev->device == 0xa01c) 1818 hpriv->irq_handler = ahci_thunderx_irq_handler; 1819 #endif 1820 1821 /* save initial config */ 1822 ahci_pci_save_initial_config(pdev, hpriv); 1823 1824 /* prepare host */ 1825 if (hpriv->cap & HOST_CAP_NCQ) { 1826 pi.flags |= ATA_FLAG_NCQ; 1827 /* 1828 * Auto-activate optimization is supposed to be 1829 * supported on all AHCI controllers indicating NCQ 1830 * capability, but it seems to be broken on some 1831 * chipsets including NVIDIAs. 1832 */ 1833 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1834 pi.flags |= ATA_FLAG_FPDMA_AA; 1835 1836 /* 1837 * All AHCI controllers should be forward-compatible 1838 * with the new auxiliary field. This code should be 1839 * conditionalized if any buggy AHCI controllers are 1840 * encountered. 1841 */ 1842 pi.flags |= ATA_FLAG_FPDMA_AUX; 1843 } 1844 1845 if (hpriv->cap & HOST_CAP_PMP) 1846 pi.flags |= ATA_FLAG_PMP; 1847 1848 ahci_set_em_messages(hpriv, &pi); 1849 1850 if (ahci_broken_system_poweroff(pdev)) { 1851 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1852 dev_info(&pdev->dev, 1853 "quirky BIOS, skipping spindown on poweroff\n"); 1854 } 1855 1856 if (ahci_broken_lpm(pdev)) { 1857 pi.flags |= ATA_FLAG_NO_LPM; 1858 dev_warn(&pdev->dev, 1859 "BIOS update required for Link Power Management support\n"); 1860 } 1861 1862 if (ahci_broken_suspend(pdev)) { 1863 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1864 dev_warn(&pdev->dev, 1865 "BIOS update required for suspend/resume\n"); 1866 } 1867 1868 if (ahci_broken_online(pdev)) { 1869 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1870 dev_info(&pdev->dev, 1871 "online status unreliable, applying workaround\n"); 1872 } 1873 1874 1875 /* Acer SA5-271 workaround modifies private_data */ 1876 acer_sa5_271_workaround(hpriv, pdev); 1877 1878 /* CAP.NP sometimes indicate the index of the last enabled 1879 * port, at other times, that of the last possible port, so 1880 * determining the maximum port number requires looking at 1881 * both CAP.NP and port_map. 1882 */ 1883 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1884 1885 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1886 if (!host) 1887 return -ENOMEM; 1888 host->private_data = hpriv; 1889 1890 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { 1891 /* legacy intx interrupts */ 1892 pci_intx(pdev, 1); 1893 } 1894 hpriv->irq = pci_irq_vector(pdev, 0); 1895 1896 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1897 host->flags |= ATA_HOST_PARALLEL_SCAN; 1898 else 1899 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1900 1901 if (!(hpriv->cap & HOST_CAP_PART)) 1902 host->flags |= ATA_HOST_NO_PART; 1903 1904 if (!(hpriv->cap & HOST_CAP_SSC)) 1905 host->flags |= ATA_HOST_NO_SSC; 1906 1907 if (!(hpriv->cap2 & HOST_CAP2_SDS)) 1908 host->flags |= ATA_HOST_NO_DEVSLP; 1909 1910 if (pi.flags & ATA_FLAG_EM) 1911 ahci_reset_em(host); 1912 1913 for (i = 0; i < host->n_ports; i++) { 1914 struct ata_port *ap = host->ports[i]; 1915 1916 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1917 ata_port_pbar_desc(ap, ahci_pci_bar, 1918 0x100 + ap->port_no * 0x80, "port"); 1919 1920 /* set enclosure management message type */ 1921 if (ap->flags & ATA_FLAG_EM) 1922 ap->em_message_type = hpriv->em_msg_type; 1923 1924 ahci_mark_external_port(ap); 1925 1926 ahci_update_initial_lpm_policy(ap); 1927 1928 /* disabled/not-implemented port */ 1929 if (!(hpriv->port_map & (1 << i))) 1930 ap->ops = &ata_dummy_port_ops; 1931 } 1932 1933 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1934 ahci_p5wdh_workaround(host); 1935 1936 /* apply gtf filter quirk */ 1937 ahci_gtf_filter_workaround(host); 1938 1939 /* initialize adapter */ 1940 rc = ahci_configure_dma_masks(pdev, hpriv); 1941 if (rc) 1942 return rc; 1943 1944 rc = ahci_pci_reset_controller(host); 1945 if (rc) 1946 return rc; 1947 1948 ahci_pci_init_controller(host); 1949 ahci_pci_print_info(host); 1950 1951 pci_set_master(pdev); 1952 1953 rc = ahci_host_activate(host, &ahci_sht); 1954 if (rc) 1955 return rc; 1956 1957 pm_runtime_put_noidle(&pdev->dev); 1958 return 0; 1959 } 1960 1961 static void ahci_shutdown_one(struct pci_dev *pdev) 1962 { 1963 ata_pci_shutdown_one(pdev); 1964 } 1965 1966 static void ahci_remove_one(struct pci_dev *pdev) 1967 { 1968 sysfs_remove_file_from_group(&pdev->dev.kobj, 1969 &dev_attr_remapped_nvme.attr, 1970 NULL); 1971 pm_runtime_get_noresume(&pdev->dev); 1972 ata_pci_remove_one(pdev); 1973 } 1974 1975 module_pci_driver(ahci_pci_driver); 1976 1977 MODULE_AUTHOR("Jeff Garzik"); 1978 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1979 MODULE_LICENSE("GPL"); 1980 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1981 MODULE_VERSION(DRV_VERSION); 1982