1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ahci.c - AHCI SATA support 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/device.h> 27 #include <linux/dmi.h> 28 #include <linux/gfp.h> 29 #include <scsi/scsi_host.h> 30 #include <scsi/scsi_cmnd.h> 31 #include <linux/libata.h> 32 #include <linux/ahci-remap.h> 33 #include <linux/io-64-nonatomic-lo-hi.h> 34 #include "ahci.h" 35 36 #define DRV_NAME "ahci" 37 #define DRV_VERSION "3.0" 38 39 enum { 40 AHCI_PCI_BAR_STA2X11 = 0, 41 AHCI_PCI_BAR_CAVIUM = 0, 42 AHCI_PCI_BAR_LOONGSON = 0, 43 AHCI_PCI_BAR_ENMOTUS = 2, 44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4, 45 AHCI_PCI_BAR_STANDARD = 5, 46 }; 47 48 enum board_ids { 49 /* board IDs by feature in alphabetical order */ 50 board_ahci, 51 board_ahci_43bit_dma, 52 board_ahci_ign_iferr, 53 board_ahci_no_debounce_delay, 54 board_ahci_no_msi, 55 /* 56 * board_ahci_pcs_quirk is for legacy Intel platforms. 57 * Modern Intel platforms should use board_ahci instead. 58 * (Some modern Intel platforms might have been added with 59 * board_ahci_pcs_quirk, however, we cannot change them to board_ahci 60 * without testing that the platform actually works without the quirk.) 61 */ 62 board_ahci_pcs_quirk, 63 board_ahci_pcs_quirk_no_devslp, 64 board_ahci_pcs_quirk_no_sntf, 65 board_ahci_yes_fbs, 66 67 /* board IDs for specific chipsets in alphabetical order */ 68 board_ahci_al, 69 board_ahci_avn, 70 board_ahci_mcp65, 71 board_ahci_mcp77, 72 board_ahci_mcp89, 73 board_ahci_mv, 74 board_ahci_sb600, 75 board_ahci_sb700, /* for SB700 and SB800 */ 76 board_ahci_vt8251, 77 78 /* aliases */ 79 board_ahci_mcp_linux = board_ahci_mcp65, 80 board_ahci_mcp67 = board_ahci_mcp65, 81 board_ahci_mcp73 = board_ahci_mcp65, 82 board_ahci_mcp79 = board_ahci_mcp77, 83 }; 84 85 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 86 static void ahci_remove_one(struct pci_dev *dev); 87 static void ahci_shutdown_one(struct pci_dev *dev); 88 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv); 89 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 90 unsigned long deadline); 91 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 92 unsigned long deadline); 93 static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 94 static bool is_mcp89_apple(struct pci_dev *pdev); 95 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 96 unsigned long deadline); 97 #ifdef CONFIG_PM 98 static int ahci_pci_device_runtime_suspend(struct device *dev); 99 static int ahci_pci_device_runtime_resume(struct device *dev); 100 #ifdef CONFIG_PM_SLEEP 101 static int ahci_pci_device_suspend(struct device *dev); 102 static int ahci_pci_device_resume(struct device *dev); 103 #endif 104 #endif /* CONFIG_PM */ 105 106 static const struct scsi_host_template ahci_sht = { 107 AHCI_SHT("ahci"), 108 }; 109 110 static struct ata_port_operations ahci_vt8251_ops = { 111 .inherits = &ahci_ops, 112 .hardreset = ahci_vt8251_hardreset, 113 }; 114 115 static struct ata_port_operations ahci_p5wdh_ops = { 116 .inherits = &ahci_ops, 117 .hardreset = ahci_p5wdh_hardreset, 118 }; 119 120 static struct ata_port_operations ahci_avn_ops = { 121 .inherits = &ahci_ops, 122 .hardreset = ahci_avn_hardreset, 123 }; 124 125 static const struct ata_port_info ahci_port_info[] = { 126 /* by features */ 127 [board_ahci] = { 128 .flags = AHCI_FLAG_COMMON, 129 .pio_mask = ATA_PIO4, 130 .udma_mask = ATA_UDMA6, 131 .port_ops = &ahci_ops, 132 }, 133 [board_ahci_43bit_dma] = { 134 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY), 135 .flags = AHCI_FLAG_COMMON, 136 .pio_mask = ATA_PIO4, 137 .udma_mask = ATA_UDMA6, 138 .port_ops = &ahci_ops, 139 }, 140 [board_ahci_ign_iferr] = { 141 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 142 .flags = AHCI_FLAG_COMMON, 143 .pio_mask = ATA_PIO4, 144 .udma_mask = ATA_UDMA6, 145 .port_ops = &ahci_ops, 146 }, 147 [board_ahci_no_debounce_delay] = { 148 .flags = AHCI_FLAG_COMMON, 149 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY, 150 .pio_mask = ATA_PIO4, 151 .udma_mask = ATA_UDMA6, 152 .port_ops = &ahci_ops, 153 }, 154 [board_ahci_no_msi] = { 155 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 156 .flags = AHCI_FLAG_COMMON, 157 .pio_mask = ATA_PIO4, 158 .udma_mask = ATA_UDMA6, 159 .port_ops = &ahci_ops, 160 }, 161 [board_ahci_pcs_quirk] = { 162 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK), 163 .flags = AHCI_FLAG_COMMON, 164 .pio_mask = ATA_PIO4, 165 .udma_mask = ATA_UDMA6, 166 .port_ops = &ahci_ops, 167 }, 168 [board_ahci_pcs_quirk_no_devslp] = { 169 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK | 170 AHCI_HFLAG_NO_DEVSLP), 171 .flags = AHCI_FLAG_COMMON, 172 .pio_mask = ATA_PIO4, 173 .udma_mask = ATA_UDMA6, 174 .port_ops = &ahci_ops, 175 }, 176 [board_ahci_pcs_quirk_no_sntf] = { 177 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK | 178 AHCI_HFLAG_NO_SNTF), 179 .flags = AHCI_FLAG_COMMON, 180 .pio_mask = ATA_PIO4, 181 .udma_mask = ATA_UDMA6, 182 .port_ops = &ahci_ops, 183 }, 184 [board_ahci_yes_fbs] = { 185 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 186 .flags = AHCI_FLAG_COMMON, 187 .pio_mask = ATA_PIO4, 188 .udma_mask = ATA_UDMA6, 189 .port_ops = &ahci_ops, 190 }, 191 /* by chipsets */ 192 [board_ahci_al] = { 193 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI), 194 .flags = AHCI_FLAG_COMMON, 195 .pio_mask = ATA_PIO4, 196 .udma_mask = ATA_UDMA6, 197 .port_ops = &ahci_ops, 198 }, 199 [board_ahci_avn] = { 200 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK), 201 .flags = AHCI_FLAG_COMMON, 202 .pio_mask = ATA_PIO4, 203 .udma_mask = ATA_UDMA6, 204 .port_ops = &ahci_avn_ops, 205 }, 206 [board_ahci_mcp65] = { 207 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 208 AHCI_HFLAG_YES_NCQ), 209 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 210 .pio_mask = ATA_PIO4, 211 .udma_mask = ATA_UDMA6, 212 .port_ops = &ahci_ops, 213 }, 214 [board_ahci_mcp77] = { 215 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 216 .flags = AHCI_FLAG_COMMON, 217 .pio_mask = ATA_PIO4, 218 .udma_mask = ATA_UDMA6, 219 .port_ops = &ahci_ops, 220 }, 221 [board_ahci_mcp89] = { 222 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 223 .flags = AHCI_FLAG_COMMON, 224 .pio_mask = ATA_PIO4, 225 .udma_mask = ATA_UDMA6, 226 .port_ops = &ahci_ops, 227 }, 228 [board_ahci_mv] = { 229 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 230 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 231 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 232 .pio_mask = ATA_PIO4, 233 .udma_mask = ATA_UDMA6, 234 .port_ops = &ahci_ops, 235 }, 236 [board_ahci_sb600] = { 237 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 238 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 239 AHCI_HFLAG_32BIT_ONLY), 240 .flags = AHCI_FLAG_COMMON, 241 .pio_mask = ATA_PIO4, 242 .udma_mask = ATA_UDMA6, 243 .port_ops = &ahci_pmp_retry_srst_ops, 244 }, 245 [board_ahci_sb700] = { /* for SB700 and SB800 */ 246 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 247 .flags = AHCI_FLAG_COMMON, 248 .pio_mask = ATA_PIO4, 249 .udma_mask = ATA_UDMA6, 250 .port_ops = &ahci_pmp_retry_srst_ops, 251 }, 252 [board_ahci_vt8251] = { 253 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 254 .flags = AHCI_FLAG_COMMON, 255 .pio_mask = ATA_PIO4, 256 .udma_mask = ATA_UDMA6, 257 .port_ops = &ahci_vt8251_ops, 258 }, 259 }; 260 261 static const struct pci_device_id ahci_pci_tbl[] = { 262 /* Intel */ 263 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci_pcs_quirk }, /* Comet Lake PCH-H RAID */ 264 { PCI_VDEVICE(INTEL, 0x2652), board_ahci_pcs_quirk }, /* ICH6 */ 265 { PCI_VDEVICE(INTEL, 0x2653), board_ahci_pcs_quirk }, /* ICH6M */ 266 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci_pcs_quirk }, /* ICH7 */ 267 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci_pcs_quirk }, /* ICH7M */ 268 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci_pcs_quirk }, /* ICH7R */ 269 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 270 { PCI_VDEVICE(INTEL, 0x2681), board_ahci_pcs_quirk }, /* ESB2 */ 271 { PCI_VDEVICE(INTEL, 0x2682), board_ahci_pcs_quirk }, /* ESB2 */ 272 { PCI_VDEVICE(INTEL, 0x2683), board_ahci_pcs_quirk }, /* ESB2 */ 273 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci_pcs_quirk }, /* ICH7-M DH */ 274 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pcs_quirk }, /* ICH8 */ 275 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pcs_quirk_no_sntf }, /* ICH8/Lewisburg RAID*/ 276 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pcs_quirk }, /* ICH8 */ 277 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pcs_quirk }, /* ICH8M */ 278 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pcs_quirk }, /* ICH8M */ 279 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pcs_quirk }, /* ICH9 */ 280 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pcs_quirk }, /* ICH9 */ 281 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pcs_quirk }, /* ICH9 */ 282 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pcs_quirk }, /* ICH9 */ 283 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pcs_quirk }, /* ICH9 */ 284 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pcs_quirk }, /* ICH9M */ 285 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pcs_quirk }, /* ICH9M */ 286 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pcs_quirk }, /* ICH9M */ 287 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pcs_quirk }, /* ICH9M */ 288 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pcs_quirk }, /* ICH9M */ 289 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pcs_quirk }, /* ICH9 */ 290 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pcs_quirk }, /* ICH9M */ 291 { PCI_VDEVICE(INTEL, 0x502a), board_ahci_pcs_quirk }, /* Tolapai */ 292 { PCI_VDEVICE(INTEL, 0x502b), board_ahci_pcs_quirk }, /* Tolapai */ 293 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci_pcs_quirk }, /* ICH10 */ 294 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci_pcs_quirk }, /* ICH10 */ 295 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci_pcs_quirk }, /* ICH10 */ 296 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci_pcs_quirk }, /* PCH AHCI */ 297 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci_pcs_quirk }, /* PCH AHCI */ 298 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci_pcs_quirk }, /* PCH RAID */ 299 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci_pcs_quirk }, /* PCH RAID */ 300 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_pcs_quirk }, /* PCH M AHCI */ 301 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci_pcs_quirk }, /* PCH RAID */ 302 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_pcs_quirk }, /* PCH M RAID */ 303 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci_pcs_quirk }, /* PCH AHCI */ 304 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */ 305 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */ 306 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */ 307 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */ 308 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */ 309 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */ 310 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */ 311 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */ 312 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */ 313 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */ 314 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */ 315 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */ 316 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */ 317 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */ 318 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */ 319 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */ 320 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */ 321 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */ 322 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */ 323 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */ 324 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci_pcs_quirk }, /* CPT AHCI */ 325 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_pcs_quirk }, /* CPT M AHCI */ 326 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci_pcs_quirk }, /* CPT RAID */ 327 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_pcs_quirk }, /* CPT M RAID */ 328 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci_pcs_quirk }, /* CPT RAID */ 329 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci_pcs_quirk }, /* CPT RAID */ 330 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci_pcs_quirk }, /* PBG AHCI */ 331 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci_pcs_quirk }, /* PBG RAID */ 332 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci_pcs_quirk }, /* PBG RAID */ 333 { PCI_VDEVICE(INTEL, 0x2323), board_ahci_pcs_quirk }, /* DH89xxCC AHCI */ 334 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci_pcs_quirk }, /* Panther Point AHCI */ 335 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_pcs_quirk }, /* Panther M AHCI */ 336 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci_pcs_quirk }, /* Panther Point RAID */ 337 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci_pcs_quirk }, /* Panther Point RAID */ 338 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci_pcs_quirk }, /* Panther Point RAID */ 339 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_pcs_quirk }, /* Panther M RAID */ 340 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci_pcs_quirk }, /* Panther Point RAID */ 341 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci_pcs_quirk }, /* Lynx Point AHCI */ 342 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_pcs_quirk }, /* Lynx M AHCI */ 343 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci_pcs_quirk }, /* Lynx Point RAID */ 344 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_pcs_quirk }, /* Lynx M RAID */ 345 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci_pcs_quirk }, /* Lynx Point RAID */ 346 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_pcs_quirk }, /* Lynx M RAID */ 347 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci_pcs_quirk }, /* Lynx Point RAID */ 348 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_pcs_quirk }, /* Lynx M RAID */ 349 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_pcs_quirk }, /* Lynx LP AHCI */ 350 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_pcs_quirk }, /* Lynx LP AHCI */ 351 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 352 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 353 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 354 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 355 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 356 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_pcs_quirk }, /* Lynx LP RAID */ 357 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_pcs_quirk }, /* Cannon Lake PCH-LP AHCI */ 358 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci_pcs_quirk }, /* Avoton AHCI */ 359 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci_pcs_quirk }, /* Avoton AHCI */ 360 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci_pcs_quirk }, /* Avoton RAID */ 361 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci_pcs_quirk }, /* Avoton RAID */ 362 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci_pcs_quirk }, /* Avoton RAID */ 363 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci_pcs_quirk }, /* Avoton RAID */ 364 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci_pcs_quirk }, /* Avoton RAID */ 365 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci_pcs_quirk }, /* Avoton RAID */ 366 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 367 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 368 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 369 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 370 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 371 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 372 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 373 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 374 { PCI_VDEVICE(INTEL, 0x2823), board_ahci_pcs_quirk }, /* Wellsburg/Lewisburg AHCI*/ 375 { PCI_VDEVICE(INTEL, 0x2826), board_ahci_pcs_quirk }, /* *burg SATA0 'RAID' */ 376 { PCI_VDEVICE(INTEL, 0x2827), board_ahci_pcs_quirk }, /* *burg SATA1 'RAID' */ 377 { PCI_VDEVICE(INTEL, 0x282f), board_ahci_pcs_quirk }, /* *burg SATA2 'RAID' */ 378 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */ 379 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */ 380 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */ 381 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */ 382 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci_pcs_quirk }, /* Wellsburg AHCI */ 383 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 384 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 385 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 386 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci_pcs_quirk }, /* Wellsburg AHCI */ 387 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 388 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 389 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci_pcs_quirk }, /* Wellsburg RAID */ 390 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci_pcs_quirk }, /* Coleto Creek AHCI */ 391 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_pcs_quirk }, /* Wildcat LP AHCI */ 392 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_pcs_quirk }, /* Wildcat LP RAID */ 393 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_pcs_quirk }, /* Wildcat LP RAID */ 394 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_pcs_quirk }, /* Wildcat LP RAID */ 395 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci_pcs_quirk }, /* 9 Series AHCI */ 396 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_pcs_quirk }, /* 9 Series M AHCI */ 397 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci_pcs_quirk }, /* 9 Series RAID */ 398 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_pcs_quirk }, /* 9 Series M RAID */ 399 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci_pcs_quirk }, /* 9 Series RAID */ 400 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_pcs_quirk }, /* 9 Series M RAID */ 401 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci_pcs_quirk }, /* 9 Series RAID */ 402 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_pcs_quirk }, /* 9 Series M RAID */ 403 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_pcs_quirk }, /* Sunrise LP AHCI */ 404 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_pcs_quirk }, /* Sunrise LP RAID */ 405 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_pcs_quirk }, /* Sunrise LP RAID */ 406 { PCI_VDEVICE(INTEL, 0xa102), board_ahci_pcs_quirk }, /* Sunrise Point-H AHCI */ 407 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_pcs_quirk }, /* Sunrise M AHCI */ 408 { PCI_VDEVICE(INTEL, 0xa105), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */ 409 { PCI_VDEVICE(INTEL, 0xa106), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */ 410 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_pcs_quirk }, /* Sunrise M RAID */ 411 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */ 412 { PCI_VDEVICE(INTEL, 0xa182), board_ahci_pcs_quirk }, /* Lewisburg AHCI*/ 413 { PCI_VDEVICE(INTEL, 0xa186), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 414 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 415 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 416 { PCI_VDEVICE(INTEL, 0xa202), board_ahci_pcs_quirk }, /* Lewisburg AHCI*/ 417 { PCI_VDEVICE(INTEL, 0xa206), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 418 { PCI_VDEVICE(INTEL, 0xa252), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 419 { PCI_VDEVICE(INTEL, 0xa256), board_ahci_pcs_quirk }, /* Lewisburg RAID*/ 420 { PCI_VDEVICE(INTEL, 0xa356), board_ahci_pcs_quirk }, /* Cannon Lake PCH-H RAID */ 421 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci_pcs_quirk }, /* Comet Lake-H RAID */ 422 { PCI_VDEVICE(INTEL, 0xa386), board_ahci_pcs_quirk }, /* Comet Lake PCH-V RAID */ 423 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_pcs_quirk }, /* Bay Trail AHCI */ 424 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_pcs_quirk_no_devslp }, /* Bay Trail AHCI */ 425 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_pcs_quirk }, /* Cherry Tr. AHCI */ 426 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_pcs_quirk }, /* ApolloLake AHCI */ 427 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_pcs_quirk }, /* Ice Lake LP AHCI */ 428 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_pcs_quirk }, /* Comet Lake PCH-U AHCI */ 429 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_pcs_quirk }, /* Comet Lake PCH RAID */ 430 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */ 431 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_pcs_quirk }, /* Elkhart Lake AHCI */ 432 { PCI_VDEVICE(INTEL, 0x7ae2), board_ahci_pcs_quirk }, /* Alder Lake-P AHCI */ 433 434 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 435 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 436 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 437 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 438 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 439 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 440 /* May need to update quirk_jmicron_async_suspend() for additions */ 441 442 /* ATI */ 443 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 444 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 445 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 446 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 447 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 448 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 449 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 450 451 /* Amazon's Annapurna Labs support */ 452 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031), 453 .class = PCI_CLASS_STORAGE_SATA_AHCI, 454 .class_mask = 0xffffff, 455 board_ahci_al }, 456 /* AMD */ 457 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 458 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */ 459 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 460 { PCI_VDEVICE(AMD, 0x7901), board_ahci }, /* AMD Green Sardine */ 461 /* AMD is using RAID class only for ahci controllers */ 462 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 463 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 464 465 /* Dell S140/S150 */ 466 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID, 467 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci_pcs_quirk }, 468 469 /* VIA */ 470 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 471 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 472 473 /* NVIDIA */ 474 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 475 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 476 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 477 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 478 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 479 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 480 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 481 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 482 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 483 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 484 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 485 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 486 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 487 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 488 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 489 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 490 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 491 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 492 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 493 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 494 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 495 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 496 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 497 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 498 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 499 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 500 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 501 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 502 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 503 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 504 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 505 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 506 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 507 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 508 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 509 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 510 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 511 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 512 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 513 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 514 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 515 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 516 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 517 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 518 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 519 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 520 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 521 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 522 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 523 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 524 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 525 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 526 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 527 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 528 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 529 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 530 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 531 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 532 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 533 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 534 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 535 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 536 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 537 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 538 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 539 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 540 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 541 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 542 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 543 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 544 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 545 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 546 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 547 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 548 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 549 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 550 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 551 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 552 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 553 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 554 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 555 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 556 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 557 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 558 559 /* SiS */ 560 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 561 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 562 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 563 564 /* ST Microelectronics */ 565 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 566 567 /* Marvell */ 568 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 569 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 570 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 571 .class = PCI_CLASS_STORAGE_SATA_AHCI, 572 .class_mask = 0xffffff, 573 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 574 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 575 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 576 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 577 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 578 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 579 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 580 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 581 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 582 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 583 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 584 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 585 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 586 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 587 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 588 .driver_data = board_ahci_yes_fbs }, 589 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ 590 .driver_data = board_ahci_yes_fbs }, 591 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 592 .driver_data = board_ahci_yes_fbs }, 593 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 594 .driver_data = board_ahci_yes_fbs }, 595 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235), 596 .driver_data = board_ahci_no_debounce_delay }, 597 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ 598 .driver_data = board_ahci_yes_fbs }, 599 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ 600 .driver_data = board_ahci_yes_fbs }, 601 602 /* Promise */ 603 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 604 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 605 606 /* ASMedia */ 607 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci_43bit_dma }, /* ASM1060 */ 608 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci_43bit_dma }, /* ASM1060 */ 609 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */ 610 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma }, /* ASM1061/1062 */ 611 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci_43bit_dma }, /* ASM1061R */ 612 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci_43bit_dma }, /* ASM1062R */ 613 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci_43bit_dma }, /* ASM1062+JMB575 */ 614 { PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci }, /* ASM1062A */ 615 { PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */ 616 { PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci }, /* ASM1164 */ 617 { PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci }, /* ASM1165 */ 618 { PCI_VDEVICE(ASMEDIA, 0x1166), board_ahci }, /* ASM1166 */ 619 620 /* 621 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 622 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 623 */ 624 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_no_msi }, 625 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_no_msi }, 626 627 /* Enmotus */ 628 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 629 630 /* Loongson */ 631 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci }, 632 633 /* Generic, PCI class code for AHCI */ 634 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 635 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 636 637 { } /* terminate list */ 638 }; 639 640 static const struct dev_pm_ops ahci_pci_pm_ops = { 641 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) 642 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, 643 ahci_pci_device_runtime_resume, NULL) 644 }; 645 646 static struct pci_driver ahci_pci_driver = { 647 .name = DRV_NAME, 648 .id_table = ahci_pci_tbl, 649 .probe = ahci_init_one, 650 .remove = ahci_remove_one, 651 .shutdown = ahci_shutdown_one, 652 .driver = { 653 .pm = &ahci_pci_pm_ops, 654 }, 655 }; 656 657 #if IS_ENABLED(CONFIG_PATA_MARVELL) 658 static int marvell_enable; 659 #else 660 static int marvell_enable = 1; 661 #endif 662 module_param(marvell_enable, int, 0644); 663 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 664 665 static int mobile_lpm_policy = -1; 666 module_param(mobile_lpm_policy, int, 0644); 667 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); 668 669 static void ahci_pci_save_initial_config(struct pci_dev *pdev, 670 struct ahci_host_priv *hpriv) 671 { 672 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA) { 673 switch (pdev->device) { 674 case 0x1166: 675 dev_info(&pdev->dev, "ASM1166 has only six ports\n"); 676 hpriv->saved_port_map = 0x3f; 677 break; 678 case 0x1064: 679 dev_info(&pdev->dev, "ASM1064 has only four ports\n"); 680 hpriv->saved_port_map = 0xf; 681 break; 682 } 683 } 684 685 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 686 dev_info(&pdev->dev, "JMB361 has only one port\n"); 687 hpriv->saved_port_map = 1; 688 } 689 690 /* 691 * Temporary Marvell 6145 hack: PATA port presence 692 * is asserted through the standard AHCI port 693 * presence register, as bit 4 (counting from 0) 694 */ 695 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 696 if (pdev->device == 0x6121) 697 hpriv->mask_port_map = 0x3; 698 else 699 hpriv->mask_port_map = 0xf; 700 dev_info(&pdev->dev, 701 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 702 } 703 704 ahci_save_initial_config(&pdev->dev, hpriv); 705 } 706 707 static int ahci_pci_reset_controller(struct ata_host *host) 708 { 709 struct pci_dev *pdev = to_pci_dev(host->dev); 710 struct ahci_host_priv *hpriv = host->private_data; 711 int rc; 712 713 rc = ahci_reset_controller(host); 714 if (rc) 715 return rc; 716 717 /* 718 * If platform firmware failed to enable ports, try to enable 719 * them here. 720 */ 721 ahci_intel_pcs_quirk(pdev, hpriv); 722 723 return 0; 724 } 725 726 static void ahci_pci_init_controller(struct ata_host *host) 727 { 728 struct ahci_host_priv *hpriv = host->private_data; 729 struct pci_dev *pdev = to_pci_dev(host->dev); 730 void __iomem *port_mmio; 731 u32 tmp; 732 int mv; 733 734 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 735 if (pdev->device == 0x6121) 736 mv = 2; 737 else 738 mv = 4; 739 port_mmio = __ahci_port_base(hpriv, mv); 740 741 writel(0, port_mmio + PORT_IRQ_MASK); 742 743 /* clear port IRQ */ 744 tmp = readl(port_mmio + PORT_IRQ_STAT); 745 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp); 746 if (tmp) 747 writel(tmp, port_mmio + PORT_IRQ_STAT); 748 } 749 750 ahci_init_controller(host); 751 } 752 753 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 754 unsigned long deadline) 755 { 756 struct ata_port *ap = link->ap; 757 struct ahci_host_priv *hpriv = ap->host->private_data; 758 bool online; 759 int rc; 760 761 hpriv->stop_engine(ap); 762 763 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 764 deadline, &online, NULL); 765 766 hpriv->start_engine(ap); 767 768 /* vt8251 doesn't clear BSY on signature FIS reception, 769 * request follow-up softreset. 770 */ 771 return online ? -EAGAIN : rc; 772 } 773 774 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 775 unsigned long deadline) 776 { 777 struct ata_port *ap = link->ap; 778 struct ahci_port_priv *pp = ap->private_data; 779 struct ahci_host_priv *hpriv = ap->host->private_data; 780 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 781 struct ata_taskfile tf; 782 bool online; 783 int rc; 784 785 hpriv->stop_engine(ap); 786 787 /* clear D2H reception area to properly wait for D2H FIS */ 788 ata_tf_init(link->device, &tf); 789 tf.status = ATA_BUSY; 790 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 791 792 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 793 deadline, &online, NULL); 794 795 hpriv->start_engine(ap); 796 797 /* The pseudo configuration device on SIMG4726 attached to 798 * ASUS P5W-DH Deluxe doesn't send signature FIS after 799 * hardreset if no device is attached to the first downstream 800 * port && the pseudo device locks up on SRST w/ PMP==0. To 801 * work around this, wait for !BSY only briefly. If BSY isn't 802 * cleared, perform CLO and proceed to IDENTIFY (achieved by 803 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 804 * 805 * Wait for two seconds. Devices attached to downstream port 806 * which can't process the following IDENTIFY after this will 807 * have to be reset again. For most cases, this should 808 * suffice while making probing snappish enough. 809 */ 810 if (online) { 811 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 812 ahci_check_ready); 813 if (rc) 814 ahci_kick_engine(ap); 815 } 816 return rc; 817 } 818 819 /* 820 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 821 * 822 * It has been observed with some SSDs that the timing of events in the 823 * link synchronization phase can leave the port in a state that can not 824 * be recovered by a SATA-hard-reset alone. The failing signature is 825 * SStatus.DET stuck at 1 ("Device presence detected but Phy 826 * communication not established"). It was found that unloading and 827 * reloading the driver when this problem occurs allows the drive 828 * connection to be recovered (DET advanced to 0x3). The critical 829 * component of reloading the driver is that the port state machines are 830 * reset by bouncing "port enable" in the AHCI PCS configuration 831 * register. So, reproduce that effect by bouncing a port whenever we 832 * see DET==1 after a reset. 833 */ 834 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 835 unsigned long deadline) 836 { 837 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context); 838 struct ata_port *ap = link->ap; 839 struct ahci_port_priv *pp = ap->private_data; 840 struct ahci_host_priv *hpriv = ap->host->private_data; 841 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 842 unsigned long tmo = deadline - jiffies; 843 struct ata_taskfile tf; 844 bool online; 845 int rc, i; 846 847 hpriv->stop_engine(ap); 848 849 for (i = 0; i < 2; i++) { 850 u16 val; 851 u32 sstatus; 852 int port = ap->port_no; 853 struct ata_host *host = ap->host; 854 struct pci_dev *pdev = to_pci_dev(host->dev); 855 856 /* clear D2H reception area to properly wait for D2H FIS */ 857 ata_tf_init(link->device, &tf); 858 tf.status = ATA_BUSY; 859 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 860 861 rc = sata_link_hardreset(link, timing, deadline, &online, 862 ahci_check_ready); 863 864 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 865 (sstatus & 0xf) != 1) 866 break; 867 868 ata_link_info(link, "avn bounce port%d\n", port); 869 870 pci_read_config_word(pdev, 0x92, &val); 871 val &= ~(1 << port); 872 pci_write_config_word(pdev, 0x92, val); 873 ata_msleep(ap, 1000); 874 val |= 1 << port; 875 pci_write_config_word(pdev, 0x92, val); 876 deadline += tmo; 877 } 878 879 hpriv->start_engine(ap); 880 881 if (online) 882 *class = ahci_dev_classify(ap); 883 884 return rc; 885 } 886 887 888 #ifdef CONFIG_PM 889 static void ahci_pci_disable_interrupts(struct ata_host *host) 890 { 891 struct ahci_host_priv *hpriv = host->private_data; 892 void __iomem *mmio = hpriv->mmio; 893 u32 ctl; 894 895 /* AHCI spec rev1.1 section 8.3.3: 896 * Software must disable interrupts prior to requesting a 897 * transition of the HBA to D3 state. 898 */ 899 ctl = readl(mmio + HOST_CTL); 900 ctl &= ~HOST_IRQ_EN; 901 writel(ctl, mmio + HOST_CTL); 902 readl(mmio + HOST_CTL); /* flush */ 903 } 904 905 static int ahci_pci_device_runtime_suspend(struct device *dev) 906 { 907 struct pci_dev *pdev = to_pci_dev(dev); 908 struct ata_host *host = pci_get_drvdata(pdev); 909 910 ahci_pci_disable_interrupts(host); 911 return 0; 912 } 913 914 static int ahci_pci_device_runtime_resume(struct device *dev) 915 { 916 struct pci_dev *pdev = to_pci_dev(dev); 917 struct ata_host *host = pci_get_drvdata(pdev); 918 int rc; 919 920 rc = ahci_pci_reset_controller(host); 921 if (rc) 922 return rc; 923 ahci_pci_init_controller(host); 924 return 0; 925 } 926 927 #ifdef CONFIG_PM_SLEEP 928 static int ahci_pci_device_suspend(struct device *dev) 929 { 930 struct pci_dev *pdev = to_pci_dev(dev); 931 struct ata_host *host = pci_get_drvdata(pdev); 932 struct ahci_host_priv *hpriv = host->private_data; 933 934 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 935 dev_err(&pdev->dev, 936 "BIOS update required for suspend/resume\n"); 937 return -EIO; 938 } 939 940 ahci_pci_disable_interrupts(host); 941 ata_host_suspend(host, PMSG_SUSPEND); 942 return 0; 943 } 944 945 static int ahci_pci_device_resume(struct device *dev) 946 { 947 struct pci_dev *pdev = to_pci_dev(dev); 948 struct ata_host *host = pci_get_drvdata(pdev); 949 int rc; 950 951 /* Apple BIOS helpfully mangles the registers on resume */ 952 if (is_mcp89_apple(pdev)) 953 ahci_mcp89_apple_enable(pdev); 954 955 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 956 rc = ahci_pci_reset_controller(host); 957 if (rc) 958 return rc; 959 960 ahci_pci_init_controller(host); 961 } 962 963 ata_host_resume(host); 964 965 return 0; 966 } 967 #endif 968 969 #endif /* CONFIG_PM */ 970 971 static int ahci_configure_dma_masks(struct pci_dev *pdev, 972 struct ahci_host_priv *hpriv) 973 { 974 int dma_bits; 975 int rc; 976 977 if (hpriv->cap & HOST_CAP_64) { 978 dma_bits = 64; 979 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY) 980 dma_bits = 43; 981 } else { 982 dma_bits = 32; 983 } 984 985 /* 986 * If the device fixup already set the dma_mask to some non-standard 987 * value, don't extend it here. This happens on STA2X11, for example. 988 * 989 * XXX: manipulating the DMA mask from platform code is completely 990 * bogus, platform code should use dev->bus_dma_limit instead.. 991 */ 992 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 993 return 0; 994 995 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits)); 996 if (rc) 997 dev_err(&pdev->dev, "DMA enable failed\n"); 998 return rc; 999 } 1000 1001 static void ahci_pci_print_info(struct ata_host *host) 1002 { 1003 struct pci_dev *pdev = to_pci_dev(host->dev); 1004 u16 cc; 1005 const char *scc_s; 1006 1007 pci_read_config_word(pdev, 0x0a, &cc); 1008 if (cc == PCI_CLASS_STORAGE_IDE) 1009 scc_s = "IDE"; 1010 else if (cc == PCI_CLASS_STORAGE_SATA) 1011 scc_s = "SATA"; 1012 else if (cc == PCI_CLASS_STORAGE_RAID) 1013 scc_s = "RAID"; 1014 else 1015 scc_s = "unknown"; 1016 1017 ahci_print_info(host, scc_s); 1018 } 1019 1020 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 1021 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 1022 * support PMP and the 4726 either directly exports the device 1023 * attached to the first downstream port or acts as a hardware storage 1024 * controller and emulate a single ATA device (can be RAID 0/1 or some 1025 * other configuration). 1026 * 1027 * When there's no device attached to the first downstream port of the 1028 * 4726, "Config Disk" appears, which is a pseudo ATA device to 1029 * configure the 4726. However, ATA emulation of the device is very 1030 * lame. It doesn't send signature D2H Reg FIS after the initial 1031 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 1032 * 1033 * The following function works around the problem by always using 1034 * hardreset on the port and not depending on receiving signature FIS 1035 * afterward. If signature FIS isn't received soon, ATA class is 1036 * assumed without follow-up softreset. 1037 */ 1038 static void ahci_p5wdh_workaround(struct ata_host *host) 1039 { 1040 static const struct dmi_system_id sysids[] = { 1041 { 1042 .ident = "P5W DH Deluxe", 1043 .matches = { 1044 DMI_MATCH(DMI_SYS_VENDOR, 1045 "ASUSTEK COMPUTER INC"), 1046 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 1047 }, 1048 }, 1049 { } 1050 }; 1051 struct pci_dev *pdev = to_pci_dev(host->dev); 1052 1053 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 1054 dmi_check_system(sysids)) { 1055 struct ata_port *ap = host->ports[1]; 1056 1057 dev_info(&pdev->dev, 1058 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 1059 1060 ap->ops = &ahci_p5wdh_ops; 1061 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 1062 } 1063 } 1064 1065 /* 1066 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 1067 * booting in BIOS compatibility mode. We restore the registers but not ID. 1068 */ 1069 static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 1070 { 1071 u32 val; 1072 1073 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 1074 1075 pci_read_config_dword(pdev, 0xf8, &val); 1076 val |= 1 << 0x1b; 1077 /* the following changes the device ID, but appears not to affect function */ 1078 /* val = (val & ~0xf0000000) | 0x80000000; */ 1079 pci_write_config_dword(pdev, 0xf8, val); 1080 1081 pci_read_config_dword(pdev, 0x54c, &val); 1082 val |= 1 << 0xc; 1083 pci_write_config_dword(pdev, 0x54c, val); 1084 1085 pci_read_config_dword(pdev, 0x4a4, &val); 1086 val &= 0xff; 1087 val |= 0x01060100; 1088 pci_write_config_dword(pdev, 0x4a4, val); 1089 1090 pci_read_config_dword(pdev, 0x54c, &val); 1091 val &= ~(1 << 0xc); 1092 pci_write_config_dword(pdev, 0x54c, val); 1093 1094 pci_read_config_dword(pdev, 0xf8, &val); 1095 val &= ~(1 << 0x1b); 1096 pci_write_config_dword(pdev, 0xf8, val); 1097 } 1098 1099 static bool is_mcp89_apple(struct pci_dev *pdev) 1100 { 1101 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1102 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1103 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1104 pdev->subsystem_device == 0xcb89; 1105 } 1106 1107 /* only some SB600 ahci controllers can do 64bit DMA */ 1108 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 1109 { 1110 static const struct dmi_system_id sysids[] = { 1111 /* 1112 * The oldest version known to be broken is 0901 and 1113 * working is 1501 which was released on 2007-10-26. 1114 * Enable 64bit DMA on 1501 and anything newer. 1115 * 1116 * Please read bko#9412 for more info. 1117 */ 1118 { 1119 .ident = "ASUS M2A-VM", 1120 .matches = { 1121 DMI_MATCH(DMI_BOARD_VENDOR, 1122 "ASUSTeK Computer INC."), 1123 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 1124 }, 1125 .driver_data = "20071026", /* yyyymmdd */ 1126 }, 1127 /* 1128 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 1129 * support 64bit DMA. 1130 * 1131 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1132 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1133 * This spelling mistake was fixed in BIOS version 1.5, so 1134 * 1.5 and later have the Manufacturer as 1135 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1136 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1137 * 1138 * BIOS versions earlier than 1.9 had a Board Product Name 1139 * DMI field of "MS-7376". This was changed to be 1140 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1141 * match on DMI_BOARD_NAME of "MS-7376". 1142 */ 1143 { 1144 .ident = "MSI K9A2 Platinum", 1145 .matches = { 1146 DMI_MATCH(DMI_BOARD_VENDOR, 1147 "MICRO-STAR INTER"), 1148 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1149 }, 1150 }, 1151 /* 1152 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1153 * 64bit DMA. 1154 * 1155 * This board also had the typo mentioned above in the 1156 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1157 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1158 */ 1159 { 1160 .ident = "MSI K9AGM2", 1161 .matches = { 1162 DMI_MATCH(DMI_BOARD_VENDOR, 1163 "MICRO-STAR INTER"), 1164 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1165 }, 1166 }, 1167 /* 1168 * All BIOS versions for the Asus M3A support 64bit DMA. 1169 * (all release versions from 0301 to 1206 were tested) 1170 */ 1171 { 1172 .ident = "ASUS M3A", 1173 .matches = { 1174 DMI_MATCH(DMI_BOARD_VENDOR, 1175 "ASUSTeK Computer INC."), 1176 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1177 }, 1178 }, 1179 { } 1180 }; 1181 const struct dmi_system_id *match; 1182 int year, month, date; 1183 char buf[9]; 1184 1185 match = dmi_first_match(sysids); 1186 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1187 !match) 1188 return false; 1189 1190 if (!match->driver_data) 1191 goto enable_64bit; 1192 1193 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1194 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1195 1196 if (strcmp(buf, match->driver_data) >= 0) 1197 goto enable_64bit; 1198 else { 1199 dev_warn(&pdev->dev, 1200 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1201 match->ident); 1202 return false; 1203 } 1204 1205 enable_64bit: 1206 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1207 return true; 1208 } 1209 1210 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1211 { 1212 static const struct dmi_system_id broken_systems[] = { 1213 { 1214 .ident = "HP Compaq nx6310", 1215 .matches = { 1216 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1217 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1218 }, 1219 /* PCI slot number of the controller */ 1220 .driver_data = (void *)0x1FUL, 1221 }, 1222 { 1223 .ident = "HP Compaq 6720s", 1224 .matches = { 1225 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1226 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1227 }, 1228 /* PCI slot number of the controller */ 1229 .driver_data = (void *)0x1FUL, 1230 }, 1231 1232 { } /* terminate list */ 1233 }; 1234 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1235 1236 if (dmi) { 1237 unsigned long slot = (unsigned long)dmi->driver_data; 1238 /* apply the quirk only to on-board controllers */ 1239 return slot == PCI_SLOT(pdev->devfn); 1240 } 1241 1242 return false; 1243 } 1244 1245 static bool ahci_broken_suspend(struct pci_dev *pdev) 1246 { 1247 static const struct dmi_system_id sysids[] = { 1248 /* 1249 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1250 * to the harddisk doesn't become online after 1251 * resuming from STR. Warn and fail suspend. 1252 * 1253 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1254 * 1255 * Use dates instead of versions to match as HP is 1256 * apparently recycling both product and version 1257 * strings. 1258 * 1259 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1260 */ 1261 { 1262 .ident = "dv4", 1263 .matches = { 1264 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1265 DMI_MATCH(DMI_PRODUCT_NAME, 1266 "HP Pavilion dv4 Notebook PC"), 1267 }, 1268 .driver_data = "20090105", /* F.30 */ 1269 }, 1270 { 1271 .ident = "dv5", 1272 .matches = { 1273 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1274 DMI_MATCH(DMI_PRODUCT_NAME, 1275 "HP Pavilion dv5 Notebook PC"), 1276 }, 1277 .driver_data = "20090506", /* F.16 */ 1278 }, 1279 { 1280 .ident = "dv6", 1281 .matches = { 1282 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1283 DMI_MATCH(DMI_PRODUCT_NAME, 1284 "HP Pavilion dv6 Notebook PC"), 1285 }, 1286 .driver_data = "20090423", /* F.21 */ 1287 }, 1288 { 1289 .ident = "HDX18", 1290 .matches = { 1291 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1292 DMI_MATCH(DMI_PRODUCT_NAME, 1293 "HP HDX18 Notebook PC"), 1294 }, 1295 .driver_data = "20090430", /* F.23 */ 1296 }, 1297 /* 1298 * Acer eMachines G725 has the same problem. BIOS 1299 * V1.03 is known to be broken. V3.04 is known to 1300 * work. Between, there are V1.06, V2.06 and V3.03 1301 * that we don't have much idea about. For now, 1302 * blacklist anything older than V3.04. 1303 * 1304 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1305 */ 1306 { 1307 .ident = "G725", 1308 .matches = { 1309 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1310 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1311 }, 1312 .driver_data = "20091216", /* V3.04 */ 1313 }, 1314 { } /* terminate list */ 1315 }; 1316 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1317 int year, month, date; 1318 char buf[9]; 1319 1320 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1321 return false; 1322 1323 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1324 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1325 1326 return strcmp(buf, dmi->driver_data) < 0; 1327 } 1328 1329 static bool ahci_broken_lpm(struct pci_dev *pdev) 1330 { 1331 static const struct dmi_system_id sysids[] = { 1332 /* Various Lenovo 50 series have LPM issues with older BIOSen */ 1333 { 1334 .matches = { 1335 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1336 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), 1337 }, 1338 .driver_data = "20180406", /* 1.31 */ 1339 }, 1340 { 1341 .matches = { 1342 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1343 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), 1344 }, 1345 .driver_data = "20180420", /* 1.28 */ 1346 }, 1347 { 1348 .matches = { 1349 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1350 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), 1351 }, 1352 .driver_data = "20180315", /* 1.33 */ 1353 }, 1354 { 1355 .matches = { 1356 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1357 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), 1358 }, 1359 /* 1360 * Note date based on release notes, 2.35 has been 1361 * reported to be good, but I've been unable to get 1362 * a hold of the reporter to get the DMI BIOS date. 1363 * TODO: fix this. 1364 */ 1365 .driver_data = "20180310", /* 2.35 */ 1366 }, 1367 { } /* terminate list */ 1368 }; 1369 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1370 int year, month, date; 1371 char buf[9]; 1372 1373 if (!dmi) 1374 return false; 1375 1376 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1377 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1378 1379 return strcmp(buf, dmi->driver_data) < 0; 1380 } 1381 1382 static bool ahci_broken_online(struct pci_dev *pdev) 1383 { 1384 #define ENCODE_BUSDEVFN(bus, slot, func) \ 1385 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1386 static const struct dmi_system_id sysids[] = { 1387 /* 1388 * There are several gigabyte boards which use 1389 * SIMG5723s configured as hardware RAID. Certain 1390 * 5723 firmware revisions shipped there keep the link 1391 * online but fail to answer properly to SRST or 1392 * IDENTIFY when no device is attached downstream 1393 * causing libata to retry quite a few times leading 1394 * to excessive detection delay. 1395 * 1396 * As these firmwares respond to the second reset try 1397 * with invalid device signature, considering unknown 1398 * sig as offline works around the problem acceptably. 1399 */ 1400 { 1401 .ident = "EP45-DQ6", 1402 .matches = { 1403 DMI_MATCH(DMI_BOARD_VENDOR, 1404 "Gigabyte Technology Co., Ltd."), 1405 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1406 }, 1407 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1408 }, 1409 { 1410 .ident = "EP45-DS5", 1411 .matches = { 1412 DMI_MATCH(DMI_BOARD_VENDOR, 1413 "Gigabyte Technology Co., Ltd."), 1414 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1415 }, 1416 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1417 }, 1418 { } /* terminate list */ 1419 }; 1420 #undef ENCODE_BUSDEVFN 1421 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1422 unsigned int val; 1423 1424 if (!dmi) 1425 return false; 1426 1427 val = (unsigned long)dmi->driver_data; 1428 1429 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1430 } 1431 1432 #ifdef CONFIG_ATA_ACPI 1433 static void ahci_gtf_filter_workaround(struct ata_host *host) 1434 { 1435 static const struct dmi_system_id sysids[] = { 1436 /* 1437 * Aspire 3810T issues a bunch of SATA enable commands 1438 * via _GTF including an invalid one and one which is 1439 * rejected by the device. Among the successful ones 1440 * is FPDMA non-zero offset enable which when enabled 1441 * only on the drive side leads to NCQ command 1442 * failures. Filter it out. 1443 */ 1444 { 1445 .ident = "Aspire 3810T", 1446 .matches = { 1447 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1448 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1449 }, 1450 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1451 }, 1452 { } 1453 }; 1454 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1455 unsigned int filter; 1456 int i; 1457 1458 if (!dmi) 1459 return; 1460 1461 filter = (unsigned long)dmi->driver_data; 1462 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1463 filter, dmi->ident); 1464 1465 for (i = 0; i < host->n_ports; i++) { 1466 struct ata_port *ap = host->ports[i]; 1467 struct ata_link *link; 1468 struct ata_device *dev; 1469 1470 ata_for_each_link(link, ap, EDGE) 1471 ata_for_each_dev(dev, link, ALL) 1472 dev->gtf_filter |= filter; 1473 } 1474 } 1475 #else 1476 static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1477 {} 1478 #endif 1479 1480 /* 1481 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected 1482 * as DUMMY, or detected but eventually get a "link down" and never get up 1483 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the 1484 * port_map may hold a value of 0x00. 1485 * 1486 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports 1487 * and can significantly reduce the occurrence of the problem. 1488 * 1489 * https://bugzilla.kernel.org/show_bug.cgi?id=189471 1490 */ 1491 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, 1492 struct pci_dev *pdev) 1493 { 1494 static const struct dmi_system_id sysids[] = { 1495 { 1496 .ident = "Acer Switch Alpha 12", 1497 .matches = { 1498 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1499 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") 1500 }, 1501 }, 1502 { } 1503 }; 1504 1505 if (dmi_check_system(sysids)) { 1506 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); 1507 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { 1508 hpriv->port_map = 0x7; 1509 hpriv->cap = 0xC734FF02; 1510 } 1511 } 1512 } 1513 1514 #ifdef CONFIG_ARM64 1515 /* 1516 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. 1517 * Workaround is to make sure all pending IRQs are served before leaving 1518 * handler. 1519 */ 1520 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) 1521 { 1522 struct ata_host *host = dev_instance; 1523 struct ahci_host_priv *hpriv; 1524 unsigned int rc = 0; 1525 void __iomem *mmio; 1526 u32 irq_stat, irq_masked; 1527 unsigned int handled = 1; 1528 1529 hpriv = host->private_data; 1530 mmio = hpriv->mmio; 1531 irq_stat = readl(mmio + HOST_IRQ_STAT); 1532 if (!irq_stat) 1533 return IRQ_NONE; 1534 1535 do { 1536 irq_masked = irq_stat & hpriv->port_map; 1537 spin_lock(&host->lock); 1538 rc = ahci_handle_port_intr(host, irq_masked); 1539 if (!rc) 1540 handled = 0; 1541 writel(irq_stat, mmio + HOST_IRQ_STAT); 1542 irq_stat = readl(mmio + HOST_IRQ_STAT); 1543 spin_unlock(&host->lock); 1544 } while (irq_stat); 1545 1546 return IRQ_RETVAL(handled); 1547 } 1548 #endif 1549 1550 static void ahci_remap_check(struct pci_dev *pdev, int bar, 1551 struct ahci_host_priv *hpriv) 1552 { 1553 int i; 1554 u32 cap; 1555 1556 /* 1557 * Check if this device might have remapped nvme devices. 1558 */ 1559 if (pdev->vendor != PCI_VENDOR_ID_INTEL || 1560 pci_resource_len(pdev, bar) < SZ_512K || 1561 bar != AHCI_PCI_BAR_STANDARD || 1562 !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) 1563 return; 1564 1565 cap = readq(hpriv->mmio + AHCI_REMAP_CAP); 1566 for (i = 0; i < AHCI_MAX_REMAP; i++) { 1567 if ((cap & (1 << i)) == 0) 1568 continue; 1569 if (readl(hpriv->mmio + ahci_remap_dcc(i)) 1570 != PCI_CLASS_STORAGE_EXPRESS) 1571 continue; 1572 1573 /* We've found a remapped device */ 1574 hpriv->remapped_nvme++; 1575 } 1576 1577 if (!hpriv->remapped_nvme) 1578 return; 1579 1580 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n", 1581 hpriv->remapped_nvme); 1582 dev_warn(&pdev->dev, 1583 "Switch your BIOS from RAID to AHCI mode to use them.\n"); 1584 1585 /* 1586 * Don't rely on the msi-x capability in the remap case, 1587 * share the legacy interrupt across ahci and remapped devices. 1588 */ 1589 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1590 } 1591 1592 static int ahci_get_irq_vector(struct ata_host *host, int port) 1593 { 1594 return pci_irq_vector(to_pci_dev(host->dev), port); 1595 } 1596 1597 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, 1598 struct ahci_host_priv *hpriv) 1599 { 1600 int nvec; 1601 1602 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1603 return -ENODEV; 1604 1605 /* 1606 * If number of MSIs is less than number of ports then Sharing Last 1607 * Message mode could be enforced. In this case assume that advantage 1608 * of multipe MSIs is negated and use single MSI mode instead. 1609 */ 1610 if (n_ports > 1) { 1611 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, 1612 PCI_IRQ_MSIX | PCI_IRQ_MSI); 1613 if (nvec > 0) { 1614 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { 1615 hpriv->get_irq_vector = ahci_get_irq_vector; 1616 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1617 return nvec; 1618 } 1619 1620 /* 1621 * Fallback to single MSI mode if the controller 1622 * enforced MRSM mode. 1623 */ 1624 printk(KERN_INFO 1625 "ahci: MRSM is on, fallback to single MSI\n"); 1626 pci_free_irq_vectors(pdev); 1627 } 1628 } 1629 1630 /* 1631 * If the host is not capable of supporting per-port vectors, fall 1632 * back to single MSI before finally attempting single MSI-X. 1633 */ 1634 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1635 if (nvec == 1) 1636 return nvec; 1637 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); 1638 } 1639 1640 static void ahci_mark_external_port(struct ata_port *ap) 1641 { 1642 struct ahci_host_priv *hpriv = ap->host->private_data; 1643 void __iomem *port_mmio = ahci_port_base(ap); 1644 u32 tmp; 1645 1646 /* mark external ports (hotplug-capable, eSATA) */ 1647 tmp = readl(port_mmio + PORT_CMD); 1648 if (((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) || 1649 (tmp & PORT_CMD_HPCP)) 1650 ap->pflags |= ATA_PFLAG_EXTERNAL; 1651 } 1652 1653 static void ahci_update_initial_lpm_policy(struct ata_port *ap) 1654 { 1655 struct ahci_host_priv *hpriv = ap->host->private_data; 1656 int policy = CONFIG_SATA_MOBILE_LPM_POLICY; 1657 1658 /* 1659 * AHCI contains a known incompatibility between LPM and hot-plug 1660 * removal events, see 7.3.1 Hot Plug Removal Detection and Power 1661 * Management Interaction in AHCI 1.3.1. Therefore, do not enable 1662 * LPM if the port advertises itself as an external port. 1663 */ 1664 if (ap->pflags & ATA_PFLAG_EXTERNAL) 1665 return; 1666 1667 /* user modified policy via module param */ 1668 if (mobile_lpm_policy != -1) { 1669 policy = mobile_lpm_policy; 1670 goto update_policy; 1671 } 1672 1673 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) { 1674 if (hpriv->cap & HOST_CAP_PART) 1675 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL; 1676 else if (hpriv->cap & HOST_CAP_SSC) 1677 policy = ATA_LPM_MIN_POWER; 1678 } 1679 1680 update_policy: 1681 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER) 1682 ap->target_lpm_policy = policy; 1683 } 1684 1685 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv) 1686 { 1687 u16 tmp16; 1688 1689 if (!(hpriv->flags & AHCI_HFLAG_INTEL_PCS_QUIRK)) 1690 return; 1691 1692 /* 1693 * port_map is determined from PORTS_IMPL PCI register which is 1694 * implemented as write or write-once register. If the register 1695 * isn't programmed, ahci automatically generates it from number 1696 * of ports, which is good enough for PCS programming. It is 1697 * otherwise expected that platform firmware enables the ports 1698 * before the OS boots. 1699 */ 1700 pci_read_config_word(pdev, PCS_6, &tmp16); 1701 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 1702 tmp16 |= hpriv->port_map; 1703 pci_write_config_word(pdev, PCS_6, tmp16); 1704 } 1705 } 1706 1707 static ssize_t remapped_nvme_show(struct device *dev, 1708 struct device_attribute *attr, 1709 char *buf) 1710 { 1711 struct ata_host *host = dev_get_drvdata(dev); 1712 struct ahci_host_priv *hpriv = host->private_data; 1713 1714 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme); 1715 } 1716 1717 static DEVICE_ATTR_RO(remapped_nvme); 1718 1719 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1720 { 1721 unsigned int board_id = ent->driver_data; 1722 struct ata_port_info pi = ahci_port_info[board_id]; 1723 const struct ata_port_info *ppi[] = { &pi, NULL }; 1724 struct device *dev = &pdev->dev; 1725 struct ahci_host_priv *hpriv; 1726 struct ata_host *host; 1727 int n_ports, i, rc; 1728 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1729 1730 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1731 1732 ata_print_version_once(&pdev->dev, DRV_VERSION); 1733 1734 /* The AHCI driver can only drive the SATA ports, the PATA driver 1735 can drive them all so if both drivers are selected make sure 1736 AHCI stays out of the way */ 1737 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1738 return -ENODEV; 1739 1740 /* Apple BIOS on MCP89 prevents us using AHCI */ 1741 if (is_mcp89_apple(pdev)) 1742 ahci_mcp89_apple_enable(pdev); 1743 1744 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1745 * At the moment, we can only use the AHCI mode. Let the users know 1746 * that for SAS drives they're out of luck. 1747 */ 1748 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1749 dev_info(&pdev->dev, 1750 "PDC42819 can only drive SATA devices with this driver\n"); 1751 1752 /* Some devices use non-standard BARs */ 1753 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1754 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1755 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1756 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1757 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { 1758 if (pdev->device == 0xa01c) 1759 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; 1760 if (pdev->device == 0xa084) 1761 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; 1762 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) { 1763 if (pdev->device == 0x7a08) 1764 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON; 1765 } 1766 1767 /* acquire resources */ 1768 rc = pcim_enable_device(pdev); 1769 if (rc) 1770 return rc; 1771 1772 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1773 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1774 u8 map; 1775 1776 /* ICH6s share the same PCI ID for both piix and ahci 1777 * modes. Enabling ahci mode while MAP indicates 1778 * combined mode is a bad idea. Yield to ata_piix. 1779 */ 1780 pci_read_config_byte(pdev, ICH_MAP, &map); 1781 if (map & 0x3) { 1782 dev_info(&pdev->dev, 1783 "controller is in combined mode, can't enable AHCI mode\n"); 1784 return -ENODEV; 1785 } 1786 } 1787 1788 /* AHCI controllers often implement SFF compatible interface. 1789 * Grab all PCI BARs just in case. 1790 */ 1791 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1792 if (rc == -EBUSY) 1793 pcim_pin_device(pdev); 1794 if (rc) 1795 return rc; 1796 1797 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1798 if (!hpriv) 1799 return -ENOMEM; 1800 hpriv->flags |= (unsigned long)pi.private_data; 1801 1802 /* MCP65 revision A1 and A2 can't do MSI */ 1803 if (board_id == board_ahci_mcp65 && 1804 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1805 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1806 1807 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1808 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1809 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1810 1811 /* only some SB600s can do 64bit DMA */ 1812 if (ahci_sb600_enable_64bit(pdev)) 1813 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1814 1815 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1816 1817 /* detect remapped nvme devices */ 1818 ahci_remap_check(pdev, ahci_pci_bar, hpriv); 1819 1820 sysfs_add_file_to_group(&pdev->dev.kobj, 1821 &dev_attr_remapped_nvme.attr, 1822 NULL); 1823 1824 #ifdef CONFIG_ARM64 1825 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI && 1826 pdev->device == 0xa235 && 1827 pdev->revision < 0x30) 1828 hpriv->flags |= AHCI_HFLAG_NO_SXS; 1829 1830 if (pdev->vendor == 0x177d && pdev->device == 0xa01c) 1831 hpriv->irq_handler = ahci_thunderx_irq_handler; 1832 #endif 1833 1834 /* save initial config */ 1835 ahci_pci_save_initial_config(pdev, hpriv); 1836 1837 /* prepare host */ 1838 if (hpriv->cap & HOST_CAP_NCQ) { 1839 pi.flags |= ATA_FLAG_NCQ; 1840 /* 1841 * Auto-activate optimization is supposed to be 1842 * supported on all AHCI controllers indicating NCQ 1843 * capability, but it seems to be broken on some 1844 * chipsets including NVIDIAs. 1845 */ 1846 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1847 pi.flags |= ATA_FLAG_FPDMA_AA; 1848 1849 /* 1850 * All AHCI controllers should be forward-compatible 1851 * with the new auxiliary field. This code should be 1852 * conditionalized if any buggy AHCI controllers are 1853 * encountered. 1854 */ 1855 pi.flags |= ATA_FLAG_FPDMA_AUX; 1856 } 1857 1858 if (hpriv->cap & HOST_CAP_PMP) 1859 pi.flags |= ATA_FLAG_PMP; 1860 1861 ahci_set_em_messages(hpriv, &pi); 1862 1863 if (ahci_broken_system_poweroff(pdev)) { 1864 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1865 dev_info(&pdev->dev, 1866 "quirky BIOS, skipping spindown on poweroff\n"); 1867 } 1868 1869 if (ahci_broken_lpm(pdev)) { 1870 pi.flags |= ATA_FLAG_NO_LPM; 1871 dev_warn(&pdev->dev, 1872 "BIOS update required for Link Power Management support\n"); 1873 } 1874 1875 if (ahci_broken_suspend(pdev)) { 1876 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1877 dev_warn(&pdev->dev, 1878 "BIOS update required for suspend/resume\n"); 1879 } 1880 1881 if (ahci_broken_online(pdev)) { 1882 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1883 dev_info(&pdev->dev, 1884 "online status unreliable, applying workaround\n"); 1885 } 1886 1887 1888 /* Acer SA5-271 workaround modifies private_data */ 1889 acer_sa5_271_workaround(hpriv, pdev); 1890 1891 /* CAP.NP sometimes indicate the index of the last enabled 1892 * port, at other times, that of the last possible port, so 1893 * determining the maximum port number requires looking at 1894 * both CAP.NP and port_map. 1895 */ 1896 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1897 1898 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1899 if (!host) 1900 return -ENOMEM; 1901 host->private_data = hpriv; 1902 1903 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { 1904 /* legacy intx interrupts */ 1905 pci_intx(pdev, 1); 1906 } 1907 hpriv->irq = pci_irq_vector(pdev, 0); 1908 1909 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1910 host->flags |= ATA_HOST_PARALLEL_SCAN; 1911 else 1912 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1913 1914 if (!(hpriv->cap & HOST_CAP_PART)) 1915 host->flags |= ATA_HOST_NO_PART; 1916 1917 if (!(hpriv->cap & HOST_CAP_SSC)) 1918 host->flags |= ATA_HOST_NO_SSC; 1919 1920 if (!(hpriv->cap2 & HOST_CAP2_SDS)) 1921 host->flags |= ATA_HOST_NO_DEVSLP; 1922 1923 if (pi.flags & ATA_FLAG_EM) 1924 ahci_reset_em(host); 1925 1926 for (i = 0; i < host->n_ports; i++) { 1927 struct ata_port *ap = host->ports[i]; 1928 1929 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1930 ata_port_pbar_desc(ap, ahci_pci_bar, 1931 0x100 + ap->port_no * 0x80, "port"); 1932 1933 /* set enclosure management message type */ 1934 if (ap->flags & ATA_FLAG_EM) 1935 ap->em_message_type = hpriv->em_msg_type; 1936 1937 ahci_mark_external_port(ap); 1938 1939 ahci_update_initial_lpm_policy(ap); 1940 1941 /* disabled/not-implemented port */ 1942 if (!(hpriv->port_map & (1 << i))) 1943 ap->ops = &ata_dummy_port_ops; 1944 } 1945 1946 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1947 ahci_p5wdh_workaround(host); 1948 1949 /* apply gtf filter quirk */ 1950 ahci_gtf_filter_workaround(host); 1951 1952 /* initialize adapter */ 1953 rc = ahci_configure_dma_masks(pdev, hpriv); 1954 if (rc) 1955 return rc; 1956 1957 rc = ahci_pci_reset_controller(host); 1958 if (rc) 1959 return rc; 1960 1961 ahci_pci_init_controller(host); 1962 ahci_pci_print_info(host); 1963 1964 pci_set_master(pdev); 1965 1966 rc = ahci_host_activate(host, &ahci_sht); 1967 if (rc) 1968 return rc; 1969 1970 pm_runtime_put_noidle(&pdev->dev); 1971 return 0; 1972 } 1973 1974 static void ahci_shutdown_one(struct pci_dev *pdev) 1975 { 1976 ata_pci_shutdown_one(pdev); 1977 } 1978 1979 static void ahci_remove_one(struct pci_dev *pdev) 1980 { 1981 sysfs_remove_file_from_group(&pdev->dev.kobj, 1982 &dev_attr_remapped_nvme.attr, 1983 NULL); 1984 pm_runtime_get_noresume(&pdev->dev); 1985 ata_pci_remove_one(pdev); 1986 } 1987 1988 module_pci_driver(ahci_pci_driver); 1989 1990 MODULE_AUTHOR("Jeff Garzik"); 1991 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1992 MODULE_LICENSE("GPL"); 1993 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1994 MODULE_VERSION(DRV_VERSION); 1995