1 /* 2 * ahci.c - AHCI SATA support 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/init.h> 39 #include <linux/blkdev.h> 40 #include <linux/delay.h> 41 #include <linux/interrupt.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/device.h> 44 #include <linux/dmi.h> 45 #include <scsi/scsi_host.h> 46 #include <scsi/scsi_cmnd.h> 47 #include <linux/libata.h> 48 49 #define DRV_NAME "ahci" 50 #define DRV_VERSION "3.0" 51 52 /* Enclosure Management Control */ 53 #define EM_CTRL_MSG_TYPE 0x000f0000 54 55 /* Enclosure Management LED Message Type */ 56 #define EM_MSG_LED_HBA_PORT 0x0000000f 57 #define EM_MSG_LED_PMP_SLOT 0x0000ff00 58 #define EM_MSG_LED_VALUE 0xffff0000 59 #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000 60 #define EM_MSG_LED_VALUE_OFF 0xfff80000 61 #define EM_MSG_LED_VALUE_ON 0x00010000 62 63 static int ahci_skip_host_reset; 64 static int ahci_ignore_sss; 65 66 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 67 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 68 69 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 70 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 71 72 static int ahci_enable_alpm(struct ata_port *ap, 73 enum link_pm policy); 74 static void ahci_disable_alpm(struct ata_port *ap); 75 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 76 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 77 size_t size); 78 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 79 ssize_t size); 80 81 enum { 82 AHCI_PCI_BAR = 5, 83 AHCI_MAX_PORTS = 32, 84 AHCI_MAX_SG = 168, /* hardware max is 64K */ 85 AHCI_DMA_BOUNDARY = 0xffffffff, 86 AHCI_MAX_CMDS = 32, 87 AHCI_CMD_SZ = 32, 88 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, 89 AHCI_RX_FIS_SZ = 256, 90 AHCI_CMD_TBL_CDB = 0x40, 91 AHCI_CMD_TBL_HDR_SZ = 0x80, 92 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), 93 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, 94 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + 95 AHCI_RX_FIS_SZ, 96 AHCI_IRQ_ON_SG = (1 << 31), 97 AHCI_CMD_ATAPI = (1 << 5), 98 AHCI_CMD_WRITE = (1 << 6), 99 AHCI_CMD_PREFETCH = (1 << 7), 100 AHCI_CMD_RESET = (1 << 8), 101 AHCI_CMD_CLR_BUSY = (1 << 10), 102 103 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ 104 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ 105 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ 106 107 board_ahci = 0, 108 board_ahci_vt8251 = 1, 109 board_ahci_ign_iferr = 2, 110 board_ahci_sb600 = 3, 111 board_ahci_mv = 4, 112 board_ahci_sb700 = 5, /* for SB700 and SB800 */ 113 board_ahci_mcp65 = 6, 114 board_ahci_nopmp = 7, 115 board_ahci_yesncq = 8, 116 117 /* global controller registers */ 118 HOST_CAP = 0x00, /* host capabilities */ 119 HOST_CTL = 0x04, /* global host control */ 120 HOST_IRQ_STAT = 0x08, /* interrupt status */ 121 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ 122 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ 123 HOST_EM_LOC = 0x1c, /* Enclosure Management location */ 124 HOST_EM_CTL = 0x20, /* Enclosure Management Control */ 125 126 /* HOST_CTL bits */ 127 HOST_RESET = (1 << 0), /* reset controller; self-clear */ 128 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ 129 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ 130 131 /* HOST_CAP bits */ 132 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */ 133 HOST_CAP_SSC = (1 << 14), /* Slumber capable */ 134 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ 135 HOST_CAP_CLO = (1 << 24), /* Command List Override support */ 136 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ 137 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ 138 HOST_CAP_SNTF = (1 << 29), /* SNotification register */ 139 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ 140 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ 141 142 /* registers for each SATA port */ 143 PORT_LST_ADDR = 0x00, /* command list DMA addr */ 144 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ 145 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ 146 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ 147 PORT_IRQ_STAT = 0x10, /* interrupt status */ 148 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ 149 PORT_CMD = 0x18, /* port command */ 150 PORT_TFDATA = 0x20, /* taskfile data */ 151 PORT_SIG = 0x24, /* device TF signature */ 152 PORT_CMD_ISSUE = 0x38, /* command issue */ 153 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ 154 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ 155 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ 156 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ 157 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ 158 159 /* PORT_IRQ_{STAT,MASK} bits */ 160 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ 161 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ 162 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ 163 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ 164 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ 165 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ 166 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ 167 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ 168 169 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ 170 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ 171 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ 172 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ 173 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ 174 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ 175 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ 176 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ 177 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ 178 179 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | 180 PORT_IRQ_IF_ERR | 181 PORT_IRQ_CONNECT | 182 PORT_IRQ_PHYRDY | 183 PORT_IRQ_UNK_FIS | 184 PORT_IRQ_BAD_PMP, 185 PORT_IRQ_ERROR = PORT_IRQ_FREEZE | 186 PORT_IRQ_TF_ERR | 187 PORT_IRQ_HBUS_DATA_ERR, 188 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | 189 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | 190 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, 191 192 /* PORT_CMD bits */ 193 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ 194 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ 195 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ 196 PORT_CMD_PMP = (1 << 17), /* PMP attached */ 197 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ 198 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ 199 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ 200 PORT_CMD_CLO = (1 << 3), /* Command list override */ 201 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ 202 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ 203 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ 204 205 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ 206 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ 207 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ 208 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ 209 210 /* hpriv->flags bits */ 211 AHCI_HFLAG_NO_NCQ = (1 << 0), 212 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ 213 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ 214 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ 215 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ 216 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ 217 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ 218 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */ 219 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ 220 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ 221 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */ 222 223 /* ap->flags bits */ 224 225 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 226 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 227 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | 228 ATA_FLAG_IPM, 229 230 ICH_MAP = 0x90, /* ICH MAP register */ 231 232 /* em constants */ 233 EM_MAX_SLOTS = 8, 234 EM_MAX_RETRY = 5, 235 236 /* em_ctl bits */ 237 EM_CTL_RST = (1 << 9), /* Reset */ 238 EM_CTL_TM = (1 << 8), /* Transmit Message */ 239 EM_CTL_ALHD = (1 << 26), /* Activity LED */ 240 }; 241 242 struct ahci_cmd_hdr { 243 __le32 opts; 244 __le32 status; 245 __le32 tbl_addr; 246 __le32 tbl_addr_hi; 247 __le32 reserved[4]; 248 }; 249 250 struct ahci_sg { 251 __le32 addr; 252 __le32 addr_hi; 253 __le32 reserved; 254 __le32 flags_size; 255 }; 256 257 struct ahci_em_priv { 258 enum sw_activity blink_policy; 259 struct timer_list timer; 260 unsigned long saved_activity; 261 unsigned long activity; 262 unsigned long led_state; 263 }; 264 265 struct ahci_host_priv { 266 unsigned int flags; /* AHCI_HFLAG_* */ 267 u32 cap; /* cap to use */ 268 u32 port_map; /* port map to use */ 269 u32 saved_cap; /* saved initial cap */ 270 u32 saved_port_map; /* saved initial port_map */ 271 u32 em_loc; /* enclosure management location */ 272 }; 273 274 struct ahci_port_priv { 275 struct ata_link *active_link; 276 struct ahci_cmd_hdr *cmd_slot; 277 dma_addr_t cmd_slot_dma; 278 void *cmd_tbl; 279 dma_addr_t cmd_tbl_dma; 280 void *rx_fis; 281 dma_addr_t rx_fis_dma; 282 /* for NCQ spurious interrupt analysis */ 283 unsigned int ncq_saw_d2h:1; 284 unsigned int ncq_saw_dmas:1; 285 unsigned int ncq_saw_sdb:1; 286 u32 intr_mask; /* interrupts to enable */ 287 /* enclosure management info per PM slot */ 288 struct ahci_em_priv em_priv[EM_MAX_SLOTS]; 289 }; 290 291 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 292 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 293 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 294 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); 295 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 296 static int ahci_port_start(struct ata_port *ap); 297 static void ahci_port_stop(struct ata_port *ap); 298 static void ahci_qc_prep(struct ata_queued_cmd *qc); 299 static void ahci_freeze(struct ata_port *ap); 300 static void ahci_thaw(struct ata_port *ap); 301 static void ahci_pmp_attach(struct ata_port *ap); 302 static void ahci_pmp_detach(struct ata_port *ap); 303 static int ahci_softreset(struct ata_link *link, unsigned int *class, 304 unsigned long deadline); 305 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class, 306 unsigned long deadline); 307 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 308 unsigned long deadline); 309 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 310 unsigned long deadline); 311 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 312 unsigned long deadline); 313 static void ahci_postreset(struct ata_link *link, unsigned int *class); 314 static void ahci_error_handler(struct ata_port *ap); 315 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 316 static int ahci_port_resume(struct ata_port *ap); 317 static void ahci_dev_config(struct ata_device *dev); 318 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 319 u32 opts); 320 #ifdef CONFIG_PM 321 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 322 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 323 static int ahci_pci_device_resume(struct pci_dev *pdev); 324 #endif 325 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 326 static ssize_t ahci_activity_store(struct ata_device *dev, 327 enum sw_activity val); 328 static void ahci_init_sw_activity(struct ata_link *link); 329 330 static struct device_attribute *ahci_shost_attrs[] = { 331 &dev_attr_link_power_management_policy, 332 &dev_attr_em_message_type, 333 &dev_attr_em_message, 334 NULL 335 }; 336 337 static struct device_attribute *ahci_sdev_attrs[] = { 338 &dev_attr_sw_activity, 339 &dev_attr_unload_heads, 340 NULL 341 }; 342 343 static struct scsi_host_template ahci_sht = { 344 ATA_NCQ_SHT(DRV_NAME), 345 .can_queue = AHCI_MAX_CMDS - 1, 346 .sg_tablesize = AHCI_MAX_SG, 347 .dma_boundary = AHCI_DMA_BOUNDARY, 348 .shost_attrs = ahci_shost_attrs, 349 .sdev_attrs = ahci_sdev_attrs, 350 }; 351 352 static struct ata_port_operations ahci_ops = { 353 .inherits = &sata_pmp_port_ops, 354 355 .qc_defer = sata_pmp_qc_defer_cmd_switch, 356 .qc_prep = ahci_qc_prep, 357 .qc_issue = ahci_qc_issue, 358 .qc_fill_rtf = ahci_qc_fill_rtf, 359 360 .freeze = ahci_freeze, 361 .thaw = ahci_thaw, 362 .softreset = ahci_softreset, 363 .hardreset = ahci_hardreset, 364 .postreset = ahci_postreset, 365 .pmp_softreset = ahci_softreset, 366 .error_handler = ahci_error_handler, 367 .post_internal_cmd = ahci_post_internal_cmd, 368 .dev_config = ahci_dev_config, 369 370 .scr_read = ahci_scr_read, 371 .scr_write = ahci_scr_write, 372 .pmp_attach = ahci_pmp_attach, 373 .pmp_detach = ahci_pmp_detach, 374 375 .enable_pm = ahci_enable_alpm, 376 .disable_pm = ahci_disable_alpm, 377 .em_show = ahci_led_show, 378 .em_store = ahci_led_store, 379 .sw_activity_show = ahci_activity_show, 380 .sw_activity_store = ahci_activity_store, 381 #ifdef CONFIG_PM 382 .port_suspend = ahci_port_suspend, 383 .port_resume = ahci_port_resume, 384 #endif 385 .port_start = ahci_port_start, 386 .port_stop = ahci_port_stop, 387 }; 388 389 static struct ata_port_operations ahci_vt8251_ops = { 390 .inherits = &ahci_ops, 391 .hardreset = ahci_vt8251_hardreset, 392 }; 393 394 static struct ata_port_operations ahci_p5wdh_ops = { 395 .inherits = &ahci_ops, 396 .hardreset = ahci_p5wdh_hardreset, 397 }; 398 399 static struct ata_port_operations ahci_sb600_ops = { 400 .inherits = &ahci_ops, 401 .softreset = ahci_sb600_softreset, 402 .pmp_softreset = ahci_sb600_softreset, 403 }; 404 405 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) 406 407 static const struct ata_port_info ahci_port_info[] = { 408 [board_ahci] = 409 { 410 .flags = AHCI_FLAG_COMMON, 411 .pio_mask = ATA_PIO4, 412 .udma_mask = ATA_UDMA6, 413 .port_ops = &ahci_ops, 414 }, 415 [board_ahci_vt8251] = 416 { 417 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 418 .flags = AHCI_FLAG_COMMON, 419 .pio_mask = ATA_PIO4, 420 .udma_mask = ATA_UDMA6, 421 .port_ops = &ahci_vt8251_ops, 422 }, 423 [board_ahci_ign_iferr] = 424 { 425 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 426 .flags = AHCI_FLAG_COMMON, 427 .pio_mask = ATA_PIO4, 428 .udma_mask = ATA_UDMA6, 429 .port_ops = &ahci_ops, 430 }, 431 [board_ahci_sb600] = 432 { 433 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 434 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255), 435 .flags = AHCI_FLAG_COMMON, 436 .pio_mask = ATA_PIO4, 437 .udma_mask = ATA_UDMA6, 438 .port_ops = &ahci_sb600_ops, 439 }, 440 [board_ahci_mv] = 441 { 442 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 443 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 444 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 445 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, 446 .pio_mask = ATA_PIO4, 447 .udma_mask = ATA_UDMA6, 448 .port_ops = &ahci_ops, 449 }, 450 [board_ahci_sb700] = /* for SB700 and SB800 */ 451 { 452 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 453 .flags = AHCI_FLAG_COMMON, 454 .pio_mask = ATA_PIO4, 455 .udma_mask = ATA_UDMA6, 456 .port_ops = &ahci_sb600_ops, 457 }, 458 [board_ahci_mcp65] = 459 { 460 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ), 461 .flags = AHCI_FLAG_COMMON, 462 .pio_mask = ATA_PIO4, 463 .udma_mask = ATA_UDMA6, 464 .port_ops = &ahci_ops, 465 }, 466 [board_ahci_nopmp] = 467 { 468 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP), 469 .flags = AHCI_FLAG_COMMON, 470 .pio_mask = ATA_PIO4, 471 .udma_mask = ATA_UDMA6, 472 .port_ops = &ahci_ops, 473 }, 474 /* board_ahci_yesncq */ 475 { 476 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ), 477 .flags = AHCI_FLAG_COMMON, 478 .pio_mask = ATA_PIO4, 479 .udma_mask = ATA_UDMA6, 480 .port_ops = &ahci_ops, 481 }, 482 }; 483 484 static const struct pci_device_id ahci_pci_tbl[] = { 485 /* Intel */ 486 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 487 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 488 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 489 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 490 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 491 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 492 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 493 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 494 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 495 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 496 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 497 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */ 498 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 499 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 500 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 501 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 502 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 503 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 504 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 505 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 506 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ 507 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ 508 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ 509 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ 510 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ 511 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 512 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ 513 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 514 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 515 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 516 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 517 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 518 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 519 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 520 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 521 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */ 522 523 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 524 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 525 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 526 527 /* ATI */ 528 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 529 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 530 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 531 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 532 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 533 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 534 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 535 536 /* VIA */ 537 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 538 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 539 540 /* NVIDIA */ 541 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 542 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 543 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 544 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 545 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 546 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 547 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 548 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 549 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */ 550 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */ 551 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */ 552 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */ 553 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */ 554 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */ 555 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */ 556 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */ 557 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */ 558 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */ 559 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */ 560 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */ 561 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */ 562 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */ 563 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */ 564 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */ 565 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */ 566 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */ 567 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */ 568 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */ 569 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */ 570 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */ 571 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */ 572 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */ 573 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ 574 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ 575 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ 576 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ 577 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ 578 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ 579 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ 580 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ 581 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ 582 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ 583 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ 584 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ 585 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */ 586 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */ 587 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */ 588 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */ 589 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */ 590 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */ 591 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */ 592 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */ 593 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */ 594 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ 595 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ 596 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ 597 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */ 598 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */ 599 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */ 600 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */ 601 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */ 602 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */ 603 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */ 604 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */ 605 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */ 606 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */ 607 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */ 608 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */ 609 610 /* SiS */ 611 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 612 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 613 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 614 615 /* Marvell */ 616 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 617 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 618 619 /* Promise */ 620 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 621 622 /* Generic, PCI class code for AHCI */ 623 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 624 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 625 626 { } /* terminate list */ 627 }; 628 629 630 static struct pci_driver ahci_pci_driver = { 631 .name = DRV_NAME, 632 .id_table = ahci_pci_tbl, 633 .probe = ahci_init_one, 634 .remove = ata_pci_remove_one, 635 #ifdef CONFIG_PM 636 .suspend = ahci_pci_device_suspend, 637 .resume = ahci_pci_device_resume, 638 #endif 639 }; 640 641 static int ahci_em_messages = 1; 642 module_param(ahci_em_messages, int, 0444); 643 /* add other LED protocol types when they become supported */ 644 MODULE_PARM_DESC(ahci_em_messages, 645 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED"); 646 647 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE) 648 static int marvell_enable; 649 #else 650 static int marvell_enable = 1; 651 #endif 652 module_param(marvell_enable, int, 0644); 653 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 654 655 656 static inline int ahci_nr_ports(u32 cap) 657 { 658 return (cap & 0x1f) + 1; 659 } 660 661 static inline void __iomem *__ahci_port_base(struct ata_host *host, 662 unsigned int port_no) 663 { 664 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 665 666 return mmio + 0x100 + (port_no * 0x80); 667 } 668 669 static inline void __iomem *ahci_port_base(struct ata_port *ap) 670 { 671 return __ahci_port_base(ap->host, ap->port_no); 672 } 673 674 static void ahci_enable_ahci(void __iomem *mmio) 675 { 676 int i; 677 u32 tmp; 678 679 /* turn on AHCI_EN */ 680 tmp = readl(mmio + HOST_CTL); 681 if (tmp & HOST_AHCI_EN) 682 return; 683 684 /* Some controllers need AHCI_EN to be written multiple times. 685 * Try a few times before giving up. 686 */ 687 for (i = 0; i < 5; i++) { 688 tmp |= HOST_AHCI_EN; 689 writel(tmp, mmio + HOST_CTL); 690 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 691 if (tmp & HOST_AHCI_EN) 692 return; 693 msleep(10); 694 } 695 696 WARN_ON(1); 697 } 698 699 /** 700 * ahci_save_initial_config - Save and fixup initial config values 701 * @pdev: target PCI device 702 * @hpriv: host private area to store config values 703 * 704 * Some registers containing configuration info might be setup by 705 * BIOS and might be cleared on reset. This function saves the 706 * initial values of those registers into @hpriv such that they 707 * can be restored after controller reset. 708 * 709 * If inconsistent, config values are fixed up by this function. 710 * 711 * LOCKING: 712 * None. 713 */ 714 static void ahci_save_initial_config(struct pci_dev *pdev, 715 struct ahci_host_priv *hpriv) 716 { 717 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; 718 u32 cap, port_map; 719 int i; 720 int mv; 721 722 /* make sure AHCI mode is enabled before accessing CAP */ 723 ahci_enable_ahci(mmio); 724 725 /* Values prefixed with saved_ are written back to host after 726 * reset. Values without are used for driver operation. 727 */ 728 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 729 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 730 731 /* some chips have errata preventing 64bit use */ 732 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 733 dev_printk(KERN_INFO, &pdev->dev, 734 "controller can't do 64bit DMA, forcing 32bit\n"); 735 cap &= ~HOST_CAP_64; 736 } 737 738 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 739 dev_printk(KERN_INFO, &pdev->dev, 740 "controller can't do NCQ, turning off CAP_NCQ\n"); 741 cap &= ~HOST_CAP_NCQ; 742 } 743 744 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 745 dev_printk(KERN_INFO, &pdev->dev, 746 "controller can do NCQ, turning on CAP_NCQ\n"); 747 cap |= HOST_CAP_NCQ; 748 } 749 750 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 751 dev_printk(KERN_INFO, &pdev->dev, 752 "controller can't do PMP, turning off CAP_PMP\n"); 753 cap &= ~HOST_CAP_PMP; 754 } 755 756 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 && 757 port_map != 1) { 758 dev_printk(KERN_INFO, &pdev->dev, 759 "JMB361 has only one port, port_map 0x%x -> 0x%x\n", 760 port_map, 1); 761 port_map = 1; 762 } 763 764 /* 765 * Temporary Marvell 6145 hack: PATA port presence 766 * is asserted through the standard AHCI port 767 * presence register, as bit 4 (counting from 0) 768 */ 769 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 770 if (pdev->device == 0x6121) 771 mv = 0x3; 772 else 773 mv = 0xf; 774 dev_printk(KERN_ERR, &pdev->dev, 775 "MV_AHCI HACK: port_map %x -> %x\n", 776 port_map, 777 port_map & mv); 778 dev_printk(KERN_ERR, &pdev->dev, 779 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 780 781 port_map &= mv; 782 } 783 784 /* cross check port_map and cap.n_ports */ 785 if (port_map) { 786 int map_ports = 0; 787 788 for (i = 0; i < AHCI_MAX_PORTS; i++) 789 if (port_map & (1 << i)) 790 map_ports++; 791 792 /* If PI has more ports than n_ports, whine, clear 793 * port_map and let it be generated from n_ports. 794 */ 795 if (map_ports > ahci_nr_ports(cap)) { 796 dev_printk(KERN_WARNING, &pdev->dev, 797 "implemented port map (0x%x) contains more " 798 "ports than nr_ports (%u), using nr_ports\n", 799 port_map, ahci_nr_ports(cap)); 800 port_map = 0; 801 } 802 } 803 804 /* fabricate port_map from cap.nr_ports */ 805 if (!port_map) { 806 port_map = (1 << ahci_nr_ports(cap)) - 1; 807 dev_printk(KERN_WARNING, &pdev->dev, 808 "forcing PORTS_IMPL to 0x%x\n", port_map); 809 810 /* write the fixed up value to the PI register */ 811 hpriv->saved_port_map = port_map; 812 } 813 814 /* record values to use during operation */ 815 hpriv->cap = cap; 816 hpriv->port_map = port_map; 817 } 818 819 /** 820 * ahci_restore_initial_config - Restore initial config 821 * @host: target ATA host 822 * 823 * Restore initial config stored by ahci_save_initial_config(). 824 * 825 * LOCKING: 826 * None. 827 */ 828 static void ahci_restore_initial_config(struct ata_host *host) 829 { 830 struct ahci_host_priv *hpriv = host->private_data; 831 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 832 833 writel(hpriv->saved_cap, mmio + HOST_CAP); 834 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 835 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 836 } 837 838 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 839 { 840 static const int offset[] = { 841 [SCR_STATUS] = PORT_SCR_STAT, 842 [SCR_CONTROL] = PORT_SCR_CTL, 843 [SCR_ERROR] = PORT_SCR_ERR, 844 [SCR_ACTIVE] = PORT_SCR_ACT, 845 [SCR_NOTIFICATION] = PORT_SCR_NTF, 846 }; 847 struct ahci_host_priv *hpriv = ap->host->private_data; 848 849 if (sc_reg < ARRAY_SIZE(offset) && 850 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 851 return offset[sc_reg]; 852 return 0; 853 } 854 855 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 856 { 857 void __iomem *port_mmio = ahci_port_base(link->ap); 858 int offset = ahci_scr_offset(link->ap, sc_reg); 859 860 if (offset) { 861 *val = readl(port_mmio + offset); 862 return 0; 863 } 864 return -EINVAL; 865 } 866 867 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 868 { 869 void __iomem *port_mmio = ahci_port_base(link->ap); 870 int offset = ahci_scr_offset(link->ap, sc_reg); 871 872 if (offset) { 873 writel(val, port_mmio + offset); 874 return 0; 875 } 876 return -EINVAL; 877 } 878 879 static void ahci_start_engine(struct ata_port *ap) 880 { 881 void __iomem *port_mmio = ahci_port_base(ap); 882 u32 tmp; 883 884 /* start DMA */ 885 tmp = readl(port_mmio + PORT_CMD); 886 tmp |= PORT_CMD_START; 887 writel(tmp, port_mmio + PORT_CMD); 888 readl(port_mmio + PORT_CMD); /* flush */ 889 } 890 891 static int ahci_stop_engine(struct ata_port *ap) 892 { 893 void __iomem *port_mmio = ahci_port_base(ap); 894 u32 tmp; 895 896 tmp = readl(port_mmio + PORT_CMD); 897 898 /* check if the HBA is idle */ 899 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 900 return 0; 901 902 /* setting HBA to idle */ 903 tmp &= ~PORT_CMD_START; 904 writel(tmp, port_mmio + PORT_CMD); 905 906 /* wait for engine to stop. This could be as long as 500 msec */ 907 tmp = ata_wait_register(port_mmio + PORT_CMD, 908 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 909 if (tmp & PORT_CMD_LIST_ON) 910 return -EIO; 911 912 return 0; 913 } 914 915 static void ahci_start_fis_rx(struct ata_port *ap) 916 { 917 void __iomem *port_mmio = ahci_port_base(ap); 918 struct ahci_host_priv *hpriv = ap->host->private_data; 919 struct ahci_port_priv *pp = ap->private_data; 920 u32 tmp; 921 922 /* set FIS registers */ 923 if (hpriv->cap & HOST_CAP_64) 924 writel((pp->cmd_slot_dma >> 16) >> 16, 925 port_mmio + PORT_LST_ADDR_HI); 926 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 927 928 if (hpriv->cap & HOST_CAP_64) 929 writel((pp->rx_fis_dma >> 16) >> 16, 930 port_mmio + PORT_FIS_ADDR_HI); 931 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 932 933 /* enable FIS reception */ 934 tmp = readl(port_mmio + PORT_CMD); 935 tmp |= PORT_CMD_FIS_RX; 936 writel(tmp, port_mmio + PORT_CMD); 937 938 /* flush */ 939 readl(port_mmio + PORT_CMD); 940 } 941 942 static int ahci_stop_fis_rx(struct ata_port *ap) 943 { 944 void __iomem *port_mmio = ahci_port_base(ap); 945 u32 tmp; 946 947 /* disable FIS reception */ 948 tmp = readl(port_mmio + PORT_CMD); 949 tmp &= ~PORT_CMD_FIS_RX; 950 writel(tmp, port_mmio + PORT_CMD); 951 952 /* wait for completion, spec says 500ms, give it 1000 */ 953 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 954 PORT_CMD_FIS_ON, 10, 1000); 955 if (tmp & PORT_CMD_FIS_ON) 956 return -EBUSY; 957 958 return 0; 959 } 960 961 static void ahci_power_up(struct ata_port *ap) 962 { 963 struct ahci_host_priv *hpriv = ap->host->private_data; 964 void __iomem *port_mmio = ahci_port_base(ap); 965 u32 cmd; 966 967 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 968 969 /* spin up device */ 970 if (hpriv->cap & HOST_CAP_SSS) { 971 cmd |= PORT_CMD_SPIN_UP; 972 writel(cmd, port_mmio + PORT_CMD); 973 } 974 975 /* wake up link */ 976 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 977 } 978 979 static void ahci_disable_alpm(struct ata_port *ap) 980 { 981 struct ahci_host_priv *hpriv = ap->host->private_data; 982 void __iomem *port_mmio = ahci_port_base(ap); 983 u32 cmd; 984 struct ahci_port_priv *pp = ap->private_data; 985 986 /* IPM bits should be disabled by libata-core */ 987 /* get the existing command bits */ 988 cmd = readl(port_mmio + PORT_CMD); 989 990 /* disable ALPM and ASP */ 991 cmd &= ~PORT_CMD_ASP; 992 cmd &= ~PORT_CMD_ALPE; 993 994 /* force the interface back to active */ 995 cmd |= PORT_CMD_ICC_ACTIVE; 996 997 /* write out new cmd value */ 998 writel(cmd, port_mmio + PORT_CMD); 999 cmd = readl(port_mmio + PORT_CMD); 1000 1001 /* wait 10ms to be sure we've come out of any low power state */ 1002 msleep(10); 1003 1004 /* clear out any PhyRdy stuff from interrupt status */ 1005 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT); 1006 1007 /* go ahead and clean out PhyRdy Change from Serror too */ 1008 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); 1009 1010 /* 1011 * Clear flag to indicate that we should ignore all PhyRdy 1012 * state changes 1013 */ 1014 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG; 1015 1016 /* 1017 * Enable interrupts on Phy Ready. 1018 */ 1019 pp->intr_mask |= PORT_IRQ_PHYRDY; 1020 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1021 1022 /* 1023 * don't change the link pm policy - we can be called 1024 * just to turn of link pm temporarily 1025 */ 1026 } 1027 1028 static int ahci_enable_alpm(struct ata_port *ap, 1029 enum link_pm policy) 1030 { 1031 struct ahci_host_priv *hpriv = ap->host->private_data; 1032 void __iomem *port_mmio = ahci_port_base(ap); 1033 u32 cmd; 1034 struct ahci_port_priv *pp = ap->private_data; 1035 u32 asp; 1036 1037 /* Make sure the host is capable of link power management */ 1038 if (!(hpriv->cap & HOST_CAP_ALPM)) 1039 return -EINVAL; 1040 1041 switch (policy) { 1042 case MAX_PERFORMANCE: 1043 case NOT_AVAILABLE: 1044 /* 1045 * if we came here with NOT_AVAILABLE, 1046 * it just means this is the first time we 1047 * have tried to enable - default to max performance, 1048 * and let the user go to lower power modes on request. 1049 */ 1050 ahci_disable_alpm(ap); 1051 return 0; 1052 case MIN_POWER: 1053 /* configure HBA to enter SLUMBER */ 1054 asp = PORT_CMD_ASP; 1055 break; 1056 case MEDIUM_POWER: 1057 /* configure HBA to enter PARTIAL */ 1058 asp = 0; 1059 break; 1060 default: 1061 return -EINVAL; 1062 } 1063 1064 /* 1065 * Disable interrupts on Phy Ready. This keeps us from 1066 * getting woken up due to spurious phy ready interrupts 1067 * TBD - Hot plug should be done via polling now, is 1068 * that even supported? 1069 */ 1070 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 1071 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1072 1073 /* 1074 * Set a flag to indicate that we should ignore all PhyRdy 1075 * state changes since these can happen now whenever we 1076 * change link state 1077 */ 1078 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG; 1079 1080 /* get the existing command bits */ 1081 cmd = readl(port_mmio + PORT_CMD); 1082 1083 /* 1084 * Set ASP based on Policy 1085 */ 1086 cmd |= asp; 1087 1088 /* 1089 * Setting this bit will instruct the HBA to aggressively 1090 * enter a lower power link state when it's appropriate and 1091 * based on the value set above for ASP 1092 */ 1093 cmd |= PORT_CMD_ALPE; 1094 1095 /* write out new cmd value */ 1096 writel(cmd, port_mmio + PORT_CMD); 1097 cmd = readl(port_mmio + PORT_CMD); 1098 1099 /* IPM bits should be set by libata-core */ 1100 return 0; 1101 } 1102 1103 #ifdef CONFIG_PM 1104 static void ahci_power_down(struct ata_port *ap) 1105 { 1106 struct ahci_host_priv *hpriv = ap->host->private_data; 1107 void __iomem *port_mmio = ahci_port_base(ap); 1108 u32 cmd, scontrol; 1109 1110 if (!(hpriv->cap & HOST_CAP_SSS)) 1111 return; 1112 1113 /* put device into listen mode, first set PxSCTL.DET to 0 */ 1114 scontrol = readl(port_mmio + PORT_SCR_CTL); 1115 scontrol &= ~0xf; 1116 writel(scontrol, port_mmio + PORT_SCR_CTL); 1117 1118 /* then set PxCMD.SUD to 0 */ 1119 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 1120 cmd &= ~PORT_CMD_SPIN_UP; 1121 writel(cmd, port_mmio + PORT_CMD); 1122 } 1123 #endif 1124 1125 static void ahci_start_port(struct ata_port *ap) 1126 { 1127 struct ahci_port_priv *pp = ap->private_data; 1128 struct ata_link *link; 1129 struct ahci_em_priv *emp; 1130 ssize_t rc; 1131 int i; 1132 1133 /* enable FIS reception */ 1134 ahci_start_fis_rx(ap); 1135 1136 /* enable DMA */ 1137 ahci_start_engine(ap); 1138 1139 /* turn on LEDs */ 1140 if (ap->flags & ATA_FLAG_EM) { 1141 ata_for_each_link(link, ap, EDGE) { 1142 emp = &pp->em_priv[link->pmp]; 1143 1144 /* EM Transmit bit maybe busy during init */ 1145 for (i = 0; i < EM_MAX_RETRY; i++) { 1146 rc = ahci_transmit_led_message(ap, 1147 emp->led_state, 1148 4); 1149 if (rc == -EBUSY) 1150 msleep(1); 1151 else 1152 break; 1153 } 1154 } 1155 } 1156 1157 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 1158 ata_for_each_link(link, ap, EDGE) 1159 ahci_init_sw_activity(link); 1160 1161 } 1162 1163 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 1164 { 1165 int rc; 1166 1167 /* disable DMA */ 1168 rc = ahci_stop_engine(ap); 1169 if (rc) { 1170 *emsg = "failed to stop engine"; 1171 return rc; 1172 } 1173 1174 /* disable FIS reception */ 1175 rc = ahci_stop_fis_rx(ap); 1176 if (rc) { 1177 *emsg = "failed stop FIS RX"; 1178 return rc; 1179 } 1180 1181 return 0; 1182 } 1183 1184 static int ahci_reset_controller(struct ata_host *host) 1185 { 1186 struct pci_dev *pdev = to_pci_dev(host->dev); 1187 struct ahci_host_priv *hpriv = host->private_data; 1188 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 1189 u32 tmp; 1190 1191 /* we must be in AHCI mode, before using anything 1192 * AHCI-specific, such as HOST_RESET. 1193 */ 1194 ahci_enable_ahci(mmio); 1195 1196 /* global controller reset */ 1197 if (!ahci_skip_host_reset) { 1198 tmp = readl(mmio + HOST_CTL); 1199 if ((tmp & HOST_RESET) == 0) { 1200 writel(tmp | HOST_RESET, mmio + HOST_CTL); 1201 readl(mmio + HOST_CTL); /* flush */ 1202 } 1203 1204 /* 1205 * to perform host reset, OS should set HOST_RESET 1206 * and poll until this bit is read to be "0". 1207 * reset must complete within 1 second, or 1208 * the hardware should be considered fried. 1209 */ 1210 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET, 1211 HOST_RESET, 10, 1000); 1212 1213 if (tmp & HOST_RESET) { 1214 dev_printk(KERN_ERR, host->dev, 1215 "controller reset failed (0x%x)\n", tmp); 1216 return -EIO; 1217 } 1218 1219 /* turn on AHCI mode */ 1220 ahci_enable_ahci(mmio); 1221 1222 /* Some registers might be cleared on reset. Restore 1223 * initial values. 1224 */ 1225 ahci_restore_initial_config(host); 1226 } else 1227 dev_printk(KERN_INFO, host->dev, 1228 "skipping global host reset\n"); 1229 1230 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 1231 u16 tmp16; 1232 1233 /* configure PCS */ 1234 pci_read_config_word(pdev, 0x92, &tmp16); 1235 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 1236 tmp16 |= hpriv->port_map; 1237 pci_write_config_word(pdev, 0x92, tmp16); 1238 } 1239 } 1240 1241 return 0; 1242 } 1243 1244 static void ahci_sw_activity(struct ata_link *link) 1245 { 1246 struct ata_port *ap = link->ap; 1247 struct ahci_port_priv *pp = ap->private_data; 1248 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1249 1250 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 1251 return; 1252 1253 emp->activity++; 1254 if (!timer_pending(&emp->timer)) 1255 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 1256 } 1257 1258 static void ahci_sw_activity_blink(unsigned long arg) 1259 { 1260 struct ata_link *link = (struct ata_link *)arg; 1261 struct ata_port *ap = link->ap; 1262 struct ahci_port_priv *pp = ap->private_data; 1263 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1264 unsigned long led_message = emp->led_state; 1265 u32 activity_led_state; 1266 unsigned long flags; 1267 1268 led_message &= EM_MSG_LED_VALUE; 1269 led_message |= ap->port_no | (link->pmp << 8); 1270 1271 /* check to see if we've had activity. If so, 1272 * toggle state of LED and reset timer. If not, 1273 * turn LED to desired idle state. 1274 */ 1275 spin_lock_irqsave(ap->lock, flags); 1276 if (emp->saved_activity != emp->activity) { 1277 emp->saved_activity = emp->activity; 1278 /* get the current LED state */ 1279 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 1280 1281 if (activity_led_state) 1282 activity_led_state = 0; 1283 else 1284 activity_led_state = 1; 1285 1286 /* clear old state */ 1287 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1288 1289 /* toggle state */ 1290 led_message |= (activity_led_state << 16); 1291 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 1292 } else { 1293 /* switch to idle */ 1294 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1295 if (emp->blink_policy == BLINK_OFF) 1296 led_message |= (1 << 16); 1297 } 1298 spin_unlock_irqrestore(ap->lock, flags); 1299 ahci_transmit_led_message(ap, led_message, 4); 1300 } 1301 1302 static void ahci_init_sw_activity(struct ata_link *link) 1303 { 1304 struct ata_port *ap = link->ap; 1305 struct ahci_port_priv *pp = ap->private_data; 1306 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1307 1308 /* init activity stats, setup timer */ 1309 emp->saved_activity = emp->activity = 0; 1310 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); 1311 1312 /* check our blink policy and set flag for link if it's enabled */ 1313 if (emp->blink_policy) 1314 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1315 } 1316 1317 static int ahci_reset_em(struct ata_host *host) 1318 { 1319 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 1320 u32 em_ctl; 1321 1322 em_ctl = readl(mmio + HOST_EM_CTL); 1323 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 1324 return -EINVAL; 1325 1326 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 1327 return 0; 1328 } 1329 1330 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 1331 ssize_t size) 1332 { 1333 struct ahci_host_priv *hpriv = ap->host->private_data; 1334 struct ahci_port_priv *pp = ap->private_data; 1335 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1336 u32 em_ctl; 1337 u32 message[] = {0, 0}; 1338 unsigned long flags; 1339 int pmp; 1340 struct ahci_em_priv *emp; 1341 1342 /* get the slot number from the message */ 1343 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1344 if (pmp < EM_MAX_SLOTS) 1345 emp = &pp->em_priv[pmp]; 1346 else 1347 return -EINVAL; 1348 1349 spin_lock_irqsave(ap->lock, flags); 1350 1351 /* 1352 * if we are still busy transmitting a previous message, 1353 * do not allow 1354 */ 1355 em_ctl = readl(mmio + HOST_EM_CTL); 1356 if (em_ctl & EM_CTL_TM) { 1357 spin_unlock_irqrestore(ap->lock, flags); 1358 return -EBUSY; 1359 } 1360 1361 /* 1362 * create message header - this is all zero except for 1363 * the message size, which is 4 bytes. 1364 */ 1365 message[0] |= (4 << 8); 1366 1367 /* ignore 0:4 of byte zero, fill in port info yourself */ 1368 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1369 1370 /* write message to EM_LOC */ 1371 writel(message[0], mmio + hpriv->em_loc); 1372 writel(message[1], mmio + hpriv->em_loc+4); 1373 1374 /* save off new led state for port/slot */ 1375 emp->led_state = state; 1376 1377 /* 1378 * tell hardware to transmit the message 1379 */ 1380 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1381 1382 spin_unlock_irqrestore(ap->lock, flags); 1383 return size; 1384 } 1385 1386 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1387 { 1388 struct ahci_port_priv *pp = ap->private_data; 1389 struct ata_link *link; 1390 struct ahci_em_priv *emp; 1391 int rc = 0; 1392 1393 ata_for_each_link(link, ap, EDGE) { 1394 emp = &pp->em_priv[link->pmp]; 1395 rc += sprintf(buf, "%lx\n", emp->led_state); 1396 } 1397 return rc; 1398 } 1399 1400 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1401 size_t size) 1402 { 1403 int state; 1404 int pmp; 1405 struct ahci_port_priv *pp = ap->private_data; 1406 struct ahci_em_priv *emp; 1407 1408 state = simple_strtoul(buf, NULL, 0); 1409 1410 /* get the slot number from the message */ 1411 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1412 if (pmp < EM_MAX_SLOTS) 1413 emp = &pp->em_priv[pmp]; 1414 else 1415 return -EINVAL; 1416 1417 /* mask off the activity bits if we are in sw_activity 1418 * mode, user should turn off sw_activity before setting 1419 * activity led through em_message 1420 */ 1421 if (emp->blink_policy) 1422 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1423 1424 return ahci_transmit_led_message(ap, state, size); 1425 } 1426 1427 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1428 { 1429 struct ata_link *link = dev->link; 1430 struct ata_port *ap = link->ap; 1431 struct ahci_port_priv *pp = ap->private_data; 1432 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1433 u32 port_led_state = emp->led_state; 1434 1435 /* save the desired Activity LED behavior */ 1436 if (val == OFF) { 1437 /* clear LFLAG */ 1438 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1439 1440 /* set the LED to OFF */ 1441 port_led_state &= EM_MSG_LED_VALUE_OFF; 1442 port_led_state |= (ap->port_no | (link->pmp << 8)); 1443 ahci_transmit_led_message(ap, port_led_state, 4); 1444 } else { 1445 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1446 if (val == BLINK_OFF) { 1447 /* set LED to ON for idle */ 1448 port_led_state &= EM_MSG_LED_VALUE_OFF; 1449 port_led_state |= (ap->port_no | (link->pmp << 8)); 1450 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1451 ahci_transmit_led_message(ap, port_led_state, 4); 1452 } 1453 } 1454 emp->blink_policy = val; 1455 return 0; 1456 } 1457 1458 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1459 { 1460 struct ata_link *link = dev->link; 1461 struct ata_port *ap = link->ap; 1462 struct ahci_port_priv *pp = ap->private_data; 1463 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1464 1465 /* display the saved value of activity behavior for this 1466 * disk. 1467 */ 1468 return sprintf(buf, "%d\n", emp->blink_policy); 1469 } 1470 1471 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, 1472 int port_no, void __iomem *mmio, 1473 void __iomem *port_mmio) 1474 { 1475 const char *emsg = NULL; 1476 int rc; 1477 u32 tmp; 1478 1479 /* make sure port is not active */ 1480 rc = ahci_deinit_port(ap, &emsg); 1481 if (rc) 1482 dev_printk(KERN_WARNING, &pdev->dev, 1483 "%s (%d)\n", emsg, rc); 1484 1485 /* clear SError */ 1486 tmp = readl(port_mmio + PORT_SCR_ERR); 1487 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1488 writel(tmp, port_mmio + PORT_SCR_ERR); 1489 1490 /* clear port IRQ */ 1491 tmp = readl(port_mmio + PORT_IRQ_STAT); 1492 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1493 if (tmp) 1494 writel(tmp, port_mmio + PORT_IRQ_STAT); 1495 1496 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1497 } 1498 1499 static void ahci_init_controller(struct ata_host *host) 1500 { 1501 struct ahci_host_priv *hpriv = host->private_data; 1502 struct pci_dev *pdev = to_pci_dev(host->dev); 1503 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 1504 int i; 1505 void __iomem *port_mmio; 1506 u32 tmp; 1507 int mv; 1508 1509 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 1510 if (pdev->device == 0x6121) 1511 mv = 2; 1512 else 1513 mv = 4; 1514 port_mmio = __ahci_port_base(host, mv); 1515 1516 writel(0, port_mmio + PORT_IRQ_MASK); 1517 1518 /* clear port IRQ */ 1519 tmp = readl(port_mmio + PORT_IRQ_STAT); 1520 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1521 if (tmp) 1522 writel(tmp, port_mmio + PORT_IRQ_STAT); 1523 } 1524 1525 for (i = 0; i < host->n_ports; i++) { 1526 struct ata_port *ap = host->ports[i]; 1527 1528 port_mmio = ahci_port_base(ap); 1529 if (ata_port_is_dummy(ap)) 1530 continue; 1531 1532 ahci_port_init(pdev, ap, i, mmio, port_mmio); 1533 } 1534 1535 tmp = readl(mmio + HOST_CTL); 1536 VPRINTK("HOST_CTL 0x%x\n", tmp); 1537 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1538 tmp = readl(mmio + HOST_CTL); 1539 VPRINTK("HOST_CTL 0x%x\n", tmp); 1540 } 1541 1542 static void ahci_dev_config(struct ata_device *dev) 1543 { 1544 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1545 1546 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1547 dev->max_sectors = 255; 1548 ata_dev_printk(dev, KERN_INFO, 1549 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1550 } 1551 } 1552 1553 static unsigned int ahci_dev_classify(struct ata_port *ap) 1554 { 1555 void __iomem *port_mmio = ahci_port_base(ap); 1556 struct ata_taskfile tf; 1557 u32 tmp; 1558 1559 tmp = readl(port_mmio + PORT_SIG); 1560 tf.lbah = (tmp >> 24) & 0xff; 1561 tf.lbam = (tmp >> 16) & 0xff; 1562 tf.lbal = (tmp >> 8) & 0xff; 1563 tf.nsect = (tmp) & 0xff; 1564 1565 return ata_dev_classify(&tf); 1566 } 1567 1568 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1569 u32 opts) 1570 { 1571 dma_addr_t cmd_tbl_dma; 1572 1573 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1574 1575 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1576 pp->cmd_slot[tag].status = 0; 1577 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1578 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1579 } 1580 1581 static int ahci_kick_engine(struct ata_port *ap, int force_restart) 1582 { 1583 void __iomem *port_mmio = ahci_port_base(ap); 1584 struct ahci_host_priv *hpriv = ap->host->private_data; 1585 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1586 u32 tmp; 1587 int busy, rc; 1588 1589 /* do we need to kick the port? */ 1590 busy = status & (ATA_BUSY | ATA_DRQ); 1591 if (!busy && !force_restart) 1592 return 0; 1593 1594 /* stop engine */ 1595 rc = ahci_stop_engine(ap); 1596 if (rc) 1597 goto out_restart; 1598 1599 /* need to do CLO? */ 1600 if (!busy) { 1601 rc = 0; 1602 goto out_restart; 1603 } 1604 1605 if (!(hpriv->cap & HOST_CAP_CLO)) { 1606 rc = -EOPNOTSUPP; 1607 goto out_restart; 1608 } 1609 1610 /* perform CLO */ 1611 tmp = readl(port_mmio + PORT_CMD); 1612 tmp |= PORT_CMD_CLO; 1613 writel(tmp, port_mmio + PORT_CMD); 1614 1615 rc = 0; 1616 tmp = ata_wait_register(port_mmio + PORT_CMD, 1617 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1618 if (tmp & PORT_CMD_CLO) 1619 rc = -EIO; 1620 1621 /* restart engine */ 1622 out_restart: 1623 ahci_start_engine(ap); 1624 return rc; 1625 } 1626 1627 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1628 struct ata_taskfile *tf, int is_cmd, u16 flags, 1629 unsigned long timeout_msec) 1630 { 1631 const u32 cmd_fis_len = 5; /* five dwords */ 1632 struct ahci_port_priv *pp = ap->private_data; 1633 void __iomem *port_mmio = ahci_port_base(ap); 1634 u8 *fis = pp->cmd_tbl; 1635 u32 tmp; 1636 1637 /* prep the command */ 1638 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1639 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1640 1641 /* issue & wait */ 1642 writel(1, port_mmio + PORT_CMD_ISSUE); 1643 1644 if (timeout_msec) { 1645 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1646 1, timeout_msec); 1647 if (tmp & 0x1) { 1648 ahci_kick_engine(ap, 1); 1649 return -EBUSY; 1650 } 1651 } else 1652 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1653 1654 return 0; 1655 } 1656 1657 static int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1658 int pmp, unsigned long deadline, 1659 int (*check_ready)(struct ata_link *link)) 1660 { 1661 struct ata_port *ap = link->ap; 1662 const char *reason = NULL; 1663 unsigned long now, msecs; 1664 struct ata_taskfile tf; 1665 int rc; 1666 1667 DPRINTK("ENTER\n"); 1668 1669 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1670 rc = ahci_kick_engine(ap, 1); 1671 if (rc && rc != -EOPNOTSUPP) 1672 ata_link_printk(link, KERN_WARNING, 1673 "failed to reset engine (errno=%d)\n", rc); 1674 1675 ata_tf_init(link->device, &tf); 1676 1677 /* issue the first D2H Register FIS */ 1678 msecs = 0; 1679 now = jiffies; 1680 if (time_after(now, deadline)) 1681 msecs = jiffies_to_msecs(deadline - now); 1682 1683 tf.ctl |= ATA_SRST; 1684 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1685 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1686 rc = -EIO; 1687 reason = "1st FIS failed"; 1688 goto fail; 1689 } 1690 1691 /* spec says at least 5us, but be generous and sleep for 1ms */ 1692 msleep(1); 1693 1694 /* issue the second D2H Register FIS */ 1695 tf.ctl &= ~ATA_SRST; 1696 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1697 1698 /* wait for link to become ready */ 1699 rc = ata_wait_after_reset(link, deadline, check_ready); 1700 /* link occupied, -ENODEV too is an error */ 1701 if (rc) { 1702 reason = "device not ready"; 1703 goto fail; 1704 } 1705 *class = ahci_dev_classify(ap); 1706 1707 DPRINTK("EXIT, class=%u\n", *class); 1708 return 0; 1709 1710 fail: 1711 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); 1712 return rc; 1713 } 1714 1715 static int ahci_check_ready(struct ata_link *link) 1716 { 1717 void __iomem *port_mmio = ahci_port_base(link->ap); 1718 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1719 1720 return ata_check_ready(status); 1721 } 1722 1723 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1724 unsigned long deadline) 1725 { 1726 int pmp = sata_srst_pmp(link); 1727 1728 DPRINTK("ENTER\n"); 1729 1730 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1731 } 1732 1733 static int ahci_sb600_check_ready(struct ata_link *link) 1734 { 1735 void __iomem *port_mmio = ahci_port_base(link->ap); 1736 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1737 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1738 1739 /* 1740 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1741 * which can save timeout delay. 1742 */ 1743 if (irq_status & PORT_IRQ_BAD_PMP) 1744 return -EIO; 1745 1746 return ata_check_ready(status); 1747 } 1748 1749 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class, 1750 unsigned long deadline) 1751 { 1752 struct ata_port *ap = link->ap; 1753 void __iomem *port_mmio = ahci_port_base(ap); 1754 int pmp = sata_srst_pmp(link); 1755 int rc; 1756 u32 irq_sts; 1757 1758 DPRINTK("ENTER\n"); 1759 1760 rc = ahci_do_softreset(link, class, pmp, deadline, 1761 ahci_sb600_check_ready); 1762 1763 /* 1764 * Soft reset fails on some ATI chips with IPMS set when PMP 1765 * is enabled but SATA HDD/ODD is connected to SATA port, 1766 * do soft reset again to port 0. 1767 */ 1768 if (rc == -EIO) { 1769 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1770 if (irq_sts & PORT_IRQ_BAD_PMP) { 1771 ata_link_printk(link, KERN_WARNING, 1772 "failed due to HW bug, retry pmp=0\n"); 1773 rc = ahci_do_softreset(link, class, 0, deadline, 1774 ahci_check_ready); 1775 } 1776 } 1777 1778 return rc; 1779 } 1780 1781 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1782 unsigned long deadline) 1783 { 1784 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1785 struct ata_port *ap = link->ap; 1786 struct ahci_port_priv *pp = ap->private_data; 1787 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1788 struct ata_taskfile tf; 1789 bool online; 1790 int rc; 1791 1792 DPRINTK("ENTER\n"); 1793 1794 ahci_stop_engine(ap); 1795 1796 /* clear D2H reception area to properly wait for D2H FIS */ 1797 ata_tf_init(link->device, &tf); 1798 tf.command = 0x80; 1799 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1800 1801 rc = sata_link_hardreset(link, timing, deadline, &online, 1802 ahci_check_ready); 1803 1804 ahci_start_engine(ap); 1805 1806 if (online) 1807 *class = ahci_dev_classify(ap); 1808 1809 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1810 return rc; 1811 } 1812 1813 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 1814 unsigned long deadline) 1815 { 1816 struct ata_port *ap = link->ap; 1817 bool online; 1818 int rc; 1819 1820 DPRINTK("ENTER\n"); 1821 1822 ahci_stop_engine(ap); 1823 1824 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 1825 deadline, &online, NULL); 1826 1827 ahci_start_engine(ap); 1828 1829 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1830 1831 /* vt8251 doesn't clear BSY on signature FIS reception, 1832 * request follow-up softreset. 1833 */ 1834 return online ? -EAGAIN : rc; 1835 } 1836 1837 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 1838 unsigned long deadline) 1839 { 1840 struct ata_port *ap = link->ap; 1841 struct ahci_port_priv *pp = ap->private_data; 1842 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1843 struct ata_taskfile tf; 1844 bool online; 1845 int rc; 1846 1847 ahci_stop_engine(ap); 1848 1849 /* clear D2H reception area to properly wait for D2H FIS */ 1850 ata_tf_init(link->device, &tf); 1851 tf.command = 0x80; 1852 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1853 1854 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 1855 deadline, &online, NULL); 1856 1857 ahci_start_engine(ap); 1858 1859 /* The pseudo configuration device on SIMG4726 attached to 1860 * ASUS P5W-DH Deluxe doesn't send signature FIS after 1861 * hardreset if no device is attached to the first downstream 1862 * port && the pseudo device locks up on SRST w/ PMP==0. To 1863 * work around this, wait for !BSY only briefly. If BSY isn't 1864 * cleared, perform CLO and proceed to IDENTIFY (achieved by 1865 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 1866 * 1867 * Wait for two seconds. Devices attached to downstream port 1868 * which can't process the following IDENTIFY after this will 1869 * have to be reset again. For most cases, this should 1870 * suffice while making probing snappish enough. 1871 */ 1872 if (online) { 1873 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 1874 ahci_check_ready); 1875 if (rc) 1876 ahci_kick_engine(ap, 0); 1877 } 1878 return rc; 1879 } 1880 1881 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1882 { 1883 struct ata_port *ap = link->ap; 1884 void __iomem *port_mmio = ahci_port_base(ap); 1885 u32 new_tmp, tmp; 1886 1887 ata_std_postreset(link, class); 1888 1889 /* Make sure port's ATAPI bit is set appropriately */ 1890 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1891 if (*class == ATA_DEV_ATAPI) 1892 new_tmp |= PORT_CMD_ATAPI; 1893 else 1894 new_tmp &= ~PORT_CMD_ATAPI; 1895 if (new_tmp != tmp) { 1896 writel(new_tmp, port_mmio + PORT_CMD); 1897 readl(port_mmio + PORT_CMD); /* flush */ 1898 } 1899 } 1900 1901 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1902 { 1903 struct scatterlist *sg; 1904 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1905 unsigned int si; 1906 1907 VPRINTK("ENTER\n"); 1908 1909 /* 1910 * Next, the S/G list. 1911 */ 1912 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1913 dma_addr_t addr = sg_dma_address(sg); 1914 u32 sg_len = sg_dma_len(sg); 1915 1916 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1917 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1918 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1919 } 1920 1921 return si; 1922 } 1923 1924 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1925 { 1926 struct ata_port *ap = qc->ap; 1927 struct ahci_port_priv *pp = ap->private_data; 1928 int is_atapi = ata_is_atapi(qc->tf.protocol); 1929 void *cmd_tbl; 1930 u32 opts; 1931 const u32 cmd_fis_len = 5; /* five dwords */ 1932 unsigned int n_elem; 1933 1934 /* 1935 * Fill in command table information. First, the header, 1936 * a SATA Register - Host to Device command FIS. 1937 */ 1938 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1939 1940 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1941 if (is_atapi) { 1942 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1943 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1944 } 1945 1946 n_elem = 0; 1947 if (qc->flags & ATA_QCFLAG_DMAMAP) 1948 n_elem = ahci_fill_sg(qc, cmd_tbl); 1949 1950 /* 1951 * Fill in command slot information. 1952 */ 1953 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1954 if (qc->tf.flags & ATA_TFLAG_WRITE) 1955 opts |= AHCI_CMD_WRITE; 1956 if (is_atapi) 1957 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1958 1959 ahci_fill_cmd_slot(pp, qc->tag, opts); 1960 } 1961 1962 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1963 { 1964 struct ahci_host_priv *hpriv = ap->host->private_data; 1965 struct ahci_port_priv *pp = ap->private_data; 1966 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1967 struct ata_link *link = NULL; 1968 struct ata_queued_cmd *active_qc; 1969 struct ata_eh_info *active_ehi; 1970 u32 serror; 1971 1972 /* determine active link */ 1973 ata_for_each_link(link, ap, EDGE) 1974 if (ata_link_active(link)) 1975 break; 1976 if (!link) 1977 link = &ap->link; 1978 1979 active_qc = ata_qc_from_tag(ap, link->active_tag); 1980 active_ehi = &link->eh_info; 1981 1982 /* record irq stat */ 1983 ata_ehi_clear_desc(host_ehi); 1984 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1985 1986 /* AHCI needs SError cleared; otherwise, it might lock up */ 1987 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1988 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1989 host_ehi->serror |= serror; 1990 1991 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1992 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1993 irq_stat &= ~PORT_IRQ_IF_ERR; 1994 1995 if (irq_stat & PORT_IRQ_TF_ERR) { 1996 /* If qc is active, charge it; otherwise, the active 1997 * link. There's no active qc on NCQ errors. It will 1998 * be determined by EH by reading log page 10h. 1999 */ 2000 if (active_qc) 2001 active_qc->err_mask |= AC_ERR_DEV; 2002 else 2003 active_ehi->err_mask |= AC_ERR_DEV; 2004 2005 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 2006 host_ehi->serror &= ~SERR_INTERNAL; 2007 } 2008 2009 if (irq_stat & PORT_IRQ_UNK_FIS) { 2010 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); 2011 2012 active_ehi->err_mask |= AC_ERR_HSM; 2013 active_ehi->action |= ATA_EH_RESET; 2014 ata_ehi_push_desc(active_ehi, 2015 "unknown FIS %08x %08x %08x %08x" , 2016 unk[0], unk[1], unk[2], unk[3]); 2017 } 2018 2019 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 2020 active_ehi->err_mask |= AC_ERR_HSM; 2021 active_ehi->action |= ATA_EH_RESET; 2022 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 2023 } 2024 2025 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 2026 host_ehi->err_mask |= AC_ERR_HOST_BUS; 2027 host_ehi->action |= ATA_EH_RESET; 2028 ata_ehi_push_desc(host_ehi, "host bus error"); 2029 } 2030 2031 if (irq_stat & PORT_IRQ_IF_ERR) { 2032 host_ehi->err_mask |= AC_ERR_ATA_BUS; 2033 host_ehi->action |= ATA_EH_RESET; 2034 ata_ehi_push_desc(host_ehi, "interface fatal error"); 2035 } 2036 2037 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 2038 ata_ehi_hotplugged(host_ehi); 2039 ata_ehi_push_desc(host_ehi, "%s", 2040 irq_stat & PORT_IRQ_CONNECT ? 2041 "connection status changed" : "PHY RDY changed"); 2042 } 2043 2044 /* okay, let's hand over to EH */ 2045 2046 if (irq_stat & PORT_IRQ_FREEZE) 2047 ata_port_freeze(ap); 2048 else 2049 ata_port_abort(ap); 2050 } 2051 2052 static void ahci_port_intr(struct ata_port *ap) 2053 { 2054 void __iomem *port_mmio = ahci_port_base(ap); 2055 struct ata_eh_info *ehi = &ap->link.eh_info; 2056 struct ahci_port_priv *pp = ap->private_data; 2057 struct ahci_host_priv *hpriv = ap->host->private_data; 2058 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 2059 u32 status, qc_active; 2060 int rc; 2061 2062 status = readl(port_mmio + PORT_IRQ_STAT); 2063 writel(status, port_mmio + PORT_IRQ_STAT); 2064 2065 /* ignore BAD_PMP while resetting */ 2066 if (unlikely(resetting)) 2067 status &= ~PORT_IRQ_BAD_PMP; 2068 2069 /* If we are getting PhyRdy, this is 2070 * just a power state change, we should 2071 * clear out this, plus the PhyRdy/Comm 2072 * Wake bits from Serror 2073 */ 2074 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) && 2075 (status & PORT_IRQ_PHYRDY)) { 2076 status &= ~PORT_IRQ_PHYRDY; 2077 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); 2078 } 2079 2080 if (unlikely(status & PORT_IRQ_ERROR)) { 2081 ahci_error_intr(ap, status); 2082 return; 2083 } 2084 2085 if (status & PORT_IRQ_SDB_FIS) { 2086 /* If SNotification is available, leave notification 2087 * handling to sata_async_notification(). If not, 2088 * emulate it by snooping SDB FIS RX area. 2089 * 2090 * Snooping FIS RX area is probably cheaper than 2091 * poking SNotification but some constrollers which 2092 * implement SNotification, ICH9 for example, don't 2093 * store AN SDB FIS into receive area. 2094 */ 2095 if (hpriv->cap & HOST_CAP_SNTF) 2096 sata_async_notification(ap); 2097 else { 2098 /* If the 'N' bit in word 0 of the FIS is set, 2099 * we just received asynchronous notification. 2100 * Tell libata about it. 2101 */ 2102 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 2103 u32 f0 = le32_to_cpu(f[0]); 2104 2105 if (f0 & (1 << 15)) 2106 sata_async_notification(ap); 2107 } 2108 } 2109 2110 /* pp->active_link is valid iff any command is in flight */ 2111 if (ap->qc_active && pp->active_link->sactive) 2112 qc_active = readl(port_mmio + PORT_SCR_ACT); 2113 else 2114 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 2115 2116 rc = ata_qc_complete_multiple(ap, qc_active); 2117 2118 /* while resetting, invalid completions are expected */ 2119 if (unlikely(rc < 0 && !resetting)) { 2120 ehi->err_mask |= AC_ERR_HSM; 2121 ehi->action |= ATA_EH_RESET; 2122 ata_port_freeze(ap); 2123 } 2124 } 2125 2126 static irqreturn_t ahci_interrupt(int irq, void *dev_instance) 2127 { 2128 struct ata_host *host = dev_instance; 2129 struct ahci_host_priv *hpriv; 2130 unsigned int i, handled = 0; 2131 void __iomem *mmio; 2132 u32 irq_stat, irq_masked; 2133 2134 VPRINTK("ENTER\n"); 2135 2136 hpriv = host->private_data; 2137 mmio = host->iomap[AHCI_PCI_BAR]; 2138 2139 /* sigh. 0xffffffff is a valid return from h/w */ 2140 irq_stat = readl(mmio + HOST_IRQ_STAT); 2141 if (!irq_stat) 2142 return IRQ_NONE; 2143 2144 irq_masked = irq_stat & hpriv->port_map; 2145 2146 spin_lock(&host->lock); 2147 2148 for (i = 0; i < host->n_ports; i++) { 2149 struct ata_port *ap; 2150 2151 if (!(irq_masked & (1 << i))) 2152 continue; 2153 2154 ap = host->ports[i]; 2155 if (ap) { 2156 ahci_port_intr(ap); 2157 VPRINTK("port %u\n", i); 2158 } else { 2159 VPRINTK("port %u (no irq)\n", i); 2160 if (ata_ratelimit()) 2161 dev_printk(KERN_WARNING, host->dev, 2162 "interrupt on disabled port %u\n", i); 2163 } 2164 2165 handled = 1; 2166 } 2167 2168 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 2169 * it should be cleared after all the port events are cleared; 2170 * otherwise, it will raise a spurious interrupt after each 2171 * valid one. Please read section 10.6.2 of ahci 1.1 for more 2172 * information. 2173 * 2174 * Also, use the unmasked value to clear interrupt as spurious 2175 * pending event on a dummy port might cause screaming IRQ. 2176 */ 2177 writel(irq_stat, mmio + HOST_IRQ_STAT); 2178 2179 spin_unlock(&host->lock); 2180 2181 VPRINTK("EXIT\n"); 2182 2183 return IRQ_RETVAL(handled); 2184 } 2185 2186 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 2187 { 2188 struct ata_port *ap = qc->ap; 2189 void __iomem *port_mmio = ahci_port_base(ap); 2190 struct ahci_port_priv *pp = ap->private_data; 2191 2192 /* Keep track of the currently active link. It will be used 2193 * in completion path to determine whether NCQ phase is in 2194 * progress. 2195 */ 2196 pp->active_link = qc->dev->link; 2197 2198 if (qc->tf.protocol == ATA_PROT_NCQ) 2199 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 2200 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 2201 2202 ahci_sw_activity(qc->dev->link); 2203 2204 return 0; 2205 } 2206 2207 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 2208 { 2209 struct ahci_port_priv *pp = qc->ap->private_data; 2210 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 2211 2212 ata_tf_from_fis(d2h_fis, &qc->result_tf); 2213 return true; 2214 } 2215 2216 static void ahci_freeze(struct ata_port *ap) 2217 { 2218 void __iomem *port_mmio = ahci_port_base(ap); 2219 2220 /* turn IRQ off */ 2221 writel(0, port_mmio + PORT_IRQ_MASK); 2222 } 2223 2224 static void ahci_thaw(struct ata_port *ap) 2225 { 2226 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 2227 void __iomem *port_mmio = ahci_port_base(ap); 2228 u32 tmp; 2229 struct ahci_port_priv *pp = ap->private_data; 2230 2231 /* clear IRQ */ 2232 tmp = readl(port_mmio + PORT_IRQ_STAT); 2233 writel(tmp, port_mmio + PORT_IRQ_STAT); 2234 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 2235 2236 /* turn IRQ back on */ 2237 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2238 } 2239 2240 static void ahci_error_handler(struct ata_port *ap) 2241 { 2242 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 2243 /* restart engine */ 2244 ahci_stop_engine(ap); 2245 ahci_start_engine(ap); 2246 } 2247 2248 sata_pmp_error_handler(ap); 2249 } 2250 2251 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 2252 { 2253 struct ata_port *ap = qc->ap; 2254 2255 /* make DMA engine forget about the failed command */ 2256 if (qc->flags & ATA_QCFLAG_FAILED) 2257 ahci_kick_engine(ap, 1); 2258 } 2259 2260 static void ahci_pmp_attach(struct ata_port *ap) 2261 { 2262 void __iomem *port_mmio = ahci_port_base(ap); 2263 struct ahci_port_priv *pp = ap->private_data; 2264 u32 cmd; 2265 2266 cmd = readl(port_mmio + PORT_CMD); 2267 cmd |= PORT_CMD_PMP; 2268 writel(cmd, port_mmio + PORT_CMD); 2269 2270 pp->intr_mask |= PORT_IRQ_BAD_PMP; 2271 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2272 } 2273 2274 static void ahci_pmp_detach(struct ata_port *ap) 2275 { 2276 void __iomem *port_mmio = ahci_port_base(ap); 2277 struct ahci_port_priv *pp = ap->private_data; 2278 u32 cmd; 2279 2280 cmd = readl(port_mmio + PORT_CMD); 2281 cmd &= ~PORT_CMD_PMP; 2282 writel(cmd, port_mmio + PORT_CMD); 2283 2284 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 2285 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2286 } 2287 2288 static int ahci_port_resume(struct ata_port *ap) 2289 { 2290 ahci_power_up(ap); 2291 ahci_start_port(ap); 2292 2293 if (sata_pmp_attached(ap)) 2294 ahci_pmp_attach(ap); 2295 else 2296 ahci_pmp_detach(ap); 2297 2298 return 0; 2299 } 2300 2301 #ifdef CONFIG_PM 2302 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2303 { 2304 const char *emsg = NULL; 2305 int rc; 2306 2307 rc = ahci_deinit_port(ap, &emsg); 2308 if (rc == 0) 2309 ahci_power_down(ap); 2310 else { 2311 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); 2312 ahci_start_port(ap); 2313 } 2314 2315 return rc; 2316 } 2317 2318 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 2319 { 2320 struct ata_host *host = dev_get_drvdata(&pdev->dev); 2321 struct ahci_host_priv *hpriv = host->private_data; 2322 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 2323 u32 ctl; 2324 2325 if (mesg.event & PM_EVENT_SUSPEND && 2326 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 2327 dev_printk(KERN_ERR, &pdev->dev, 2328 "BIOS update required for suspend/resume\n"); 2329 return -EIO; 2330 } 2331 2332 if (mesg.event & PM_EVENT_SLEEP) { 2333 /* AHCI spec rev1.1 section 8.3.3: 2334 * Software must disable interrupts prior to requesting a 2335 * transition of the HBA to D3 state. 2336 */ 2337 ctl = readl(mmio + HOST_CTL); 2338 ctl &= ~HOST_IRQ_EN; 2339 writel(ctl, mmio + HOST_CTL); 2340 readl(mmio + HOST_CTL); /* flush */ 2341 } 2342 2343 return ata_pci_device_suspend(pdev, mesg); 2344 } 2345 2346 static int ahci_pci_device_resume(struct pci_dev *pdev) 2347 { 2348 struct ata_host *host = dev_get_drvdata(&pdev->dev); 2349 int rc; 2350 2351 rc = ata_pci_device_do_resume(pdev); 2352 if (rc) 2353 return rc; 2354 2355 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 2356 rc = ahci_reset_controller(host); 2357 if (rc) 2358 return rc; 2359 2360 ahci_init_controller(host); 2361 } 2362 2363 ata_host_resume(host); 2364 2365 return 0; 2366 } 2367 #endif 2368 2369 static int ahci_port_start(struct ata_port *ap) 2370 { 2371 struct device *dev = ap->host->dev; 2372 struct ahci_port_priv *pp; 2373 void *mem; 2374 dma_addr_t mem_dma; 2375 2376 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2377 if (!pp) 2378 return -ENOMEM; 2379 2380 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, 2381 GFP_KERNEL); 2382 if (!mem) 2383 return -ENOMEM; 2384 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); 2385 2386 /* 2387 * First item in chunk of DMA memory: 32-slot command table, 2388 * 32 bytes each in size 2389 */ 2390 pp->cmd_slot = mem; 2391 pp->cmd_slot_dma = mem_dma; 2392 2393 mem += AHCI_CMD_SLOT_SZ; 2394 mem_dma += AHCI_CMD_SLOT_SZ; 2395 2396 /* 2397 * Second item: Received-FIS area 2398 */ 2399 pp->rx_fis = mem; 2400 pp->rx_fis_dma = mem_dma; 2401 2402 mem += AHCI_RX_FIS_SZ; 2403 mem_dma += AHCI_RX_FIS_SZ; 2404 2405 /* 2406 * Third item: data area for storing a single command 2407 * and its scatter-gather table 2408 */ 2409 pp->cmd_tbl = mem; 2410 pp->cmd_tbl_dma = mem_dma; 2411 2412 /* 2413 * Save off initial list of interrupts to be enabled. 2414 * This could be changed later 2415 */ 2416 pp->intr_mask = DEF_PORT_IRQ; 2417 2418 ap->private_data = pp; 2419 2420 /* engage engines, captain */ 2421 return ahci_port_resume(ap); 2422 } 2423 2424 static void ahci_port_stop(struct ata_port *ap) 2425 { 2426 const char *emsg = NULL; 2427 int rc; 2428 2429 /* de-initialize port */ 2430 rc = ahci_deinit_port(ap, &emsg); 2431 if (rc) 2432 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); 2433 } 2434 2435 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 2436 { 2437 int rc; 2438 2439 if (using_dac && 2440 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 2441 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 2442 if (rc) { 2443 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 2444 if (rc) { 2445 dev_printk(KERN_ERR, &pdev->dev, 2446 "64-bit DMA enable failed\n"); 2447 return rc; 2448 } 2449 } 2450 } else { 2451 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2452 if (rc) { 2453 dev_printk(KERN_ERR, &pdev->dev, 2454 "32-bit DMA enable failed\n"); 2455 return rc; 2456 } 2457 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 2458 if (rc) { 2459 dev_printk(KERN_ERR, &pdev->dev, 2460 "32-bit consistent DMA enable failed\n"); 2461 return rc; 2462 } 2463 } 2464 return 0; 2465 } 2466 2467 static void ahci_print_info(struct ata_host *host) 2468 { 2469 struct ahci_host_priv *hpriv = host->private_data; 2470 struct pci_dev *pdev = to_pci_dev(host->dev); 2471 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 2472 u32 vers, cap, impl, speed; 2473 const char *speed_s; 2474 u16 cc; 2475 const char *scc_s; 2476 2477 vers = readl(mmio + HOST_VERSION); 2478 cap = hpriv->cap; 2479 impl = hpriv->port_map; 2480 2481 speed = (cap >> 20) & 0xf; 2482 if (speed == 1) 2483 speed_s = "1.5"; 2484 else if (speed == 2) 2485 speed_s = "3"; 2486 else if (speed == 3) 2487 speed_s = "6"; 2488 else 2489 speed_s = "?"; 2490 2491 pci_read_config_word(pdev, 0x0a, &cc); 2492 if (cc == PCI_CLASS_STORAGE_IDE) 2493 scc_s = "IDE"; 2494 else if (cc == PCI_CLASS_STORAGE_SATA) 2495 scc_s = "SATA"; 2496 else if (cc == PCI_CLASS_STORAGE_RAID) 2497 scc_s = "RAID"; 2498 else 2499 scc_s = "unknown"; 2500 2501 dev_printk(KERN_INFO, &pdev->dev, 2502 "AHCI %02x%02x.%02x%02x " 2503 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2504 , 2505 2506 (vers >> 24) & 0xff, 2507 (vers >> 16) & 0xff, 2508 (vers >> 8) & 0xff, 2509 vers & 0xff, 2510 2511 ((cap >> 8) & 0x1f) + 1, 2512 (cap & 0x1f) + 1, 2513 speed_s, 2514 impl, 2515 scc_s); 2516 2517 dev_printk(KERN_INFO, &pdev->dev, 2518 "flags: " 2519 "%s%s%s%s%s%s%s" 2520 "%s%s%s%s%s%s%s" 2521 "%s\n" 2522 , 2523 2524 cap & (1 << 31) ? "64bit " : "", 2525 cap & (1 << 30) ? "ncq " : "", 2526 cap & (1 << 29) ? "sntf " : "", 2527 cap & (1 << 28) ? "ilck " : "", 2528 cap & (1 << 27) ? "stag " : "", 2529 cap & (1 << 26) ? "pm " : "", 2530 cap & (1 << 25) ? "led " : "", 2531 2532 cap & (1 << 24) ? "clo " : "", 2533 cap & (1 << 19) ? "nz " : "", 2534 cap & (1 << 18) ? "only " : "", 2535 cap & (1 << 17) ? "pmp " : "", 2536 cap & (1 << 15) ? "pio " : "", 2537 cap & (1 << 14) ? "slum " : "", 2538 cap & (1 << 13) ? "part " : "", 2539 cap & (1 << 6) ? "ems ": "" 2540 ); 2541 } 2542 2543 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 2544 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 2545 * support PMP and the 4726 either directly exports the device 2546 * attached to the first downstream port or acts as a hardware storage 2547 * controller and emulate a single ATA device (can be RAID 0/1 or some 2548 * other configuration). 2549 * 2550 * When there's no device attached to the first downstream port of the 2551 * 4726, "Config Disk" appears, which is a pseudo ATA device to 2552 * configure the 4726. However, ATA emulation of the device is very 2553 * lame. It doesn't send signature D2H Reg FIS after the initial 2554 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 2555 * 2556 * The following function works around the problem by always using 2557 * hardreset on the port and not depending on receiving signature FIS 2558 * afterward. If signature FIS isn't received soon, ATA class is 2559 * assumed without follow-up softreset. 2560 */ 2561 static void ahci_p5wdh_workaround(struct ata_host *host) 2562 { 2563 static struct dmi_system_id sysids[] = { 2564 { 2565 .ident = "P5W DH Deluxe", 2566 .matches = { 2567 DMI_MATCH(DMI_SYS_VENDOR, 2568 "ASUSTEK COMPUTER INC"), 2569 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 2570 }, 2571 }, 2572 { } 2573 }; 2574 struct pci_dev *pdev = to_pci_dev(host->dev); 2575 2576 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 2577 dmi_check_system(sysids)) { 2578 struct ata_port *ap = host->ports[1]; 2579 2580 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH " 2581 "Deluxe on-board SIMG4726 workaround\n"); 2582 2583 ap->ops = &ahci_p5wdh_ops; 2584 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 2585 } 2586 } 2587 2588 /* 2589 * SB600 ahci controller on ASUS M2A-VM can't do 64bit DMA with older 2590 * BIOS. The oldest version known to be broken is 0901 and working is 2591 * 1501 which was released on 2007-10-26. Force 32bit DMA on anything 2592 * older than 1501. Please read bko#9412 for more info. 2593 */ 2594 static bool ahci_asus_m2a_vm_32bit_only(struct pci_dev *pdev) 2595 { 2596 static const struct dmi_system_id sysids[] = { 2597 { 2598 .ident = "ASUS M2A-VM", 2599 .matches = { 2600 DMI_MATCH(DMI_BOARD_VENDOR, 2601 "ASUSTeK Computer INC."), 2602 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 2603 }, 2604 }, 2605 { } 2606 }; 2607 const char *cutoff_mmdd = "10/26"; 2608 const char *date; 2609 int year; 2610 2611 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 2612 !dmi_check_system(sysids)) 2613 return false; 2614 2615 /* 2616 * Argh.... both version and date are free form strings. 2617 * Let's hope they're using the same date format across 2618 * different versions. 2619 */ 2620 date = dmi_get_system_info(DMI_BIOS_DATE); 2621 year = dmi_get_year(DMI_BIOS_DATE); 2622 if (date && strlen(date) >= 10 && date[2] == '/' && date[5] == '/' && 2623 (year > 2007 || 2624 (year == 2007 && strncmp(date, cutoff_mmdd, 5) >= 0))) 2625 return false; 2626 2627 dev_printk(KERN_WARNING, &pdev->dev, "ASUS M2A-VM: BIOS too old, " 2628 "forcing 32bit DMA, update BIOS\n"); 2629 2630 return true; 2631 } 2632 2633 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 2634 { 2635 static const struct dmi_system_id broken_systems[] = { 2636 { 2637 .ident = "HP Compaq nx6310", 2638 .matches = { 2639 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 2640 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 2641 }, 2642 /* PCI slot number of the controller */ 2643 .driver_data = (void *)0x1FUL, 2644 }, 2645 { 2646 .ident = "HP Compaq 6720s", 2647 .matches = { 2648 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 2649 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 2650 }, 2651 /* PCI slot number of the controller */ 2652 .driver_data = (void *)0x1FUL, 2653 }, 2654 2655 { } /* terminate list */ 2656 }; 2657 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 2658 2659 if (dmi) { 2660 unsigned long slot = (unsigned long)dmi->driver_data; 2661 /* apply the quirk only to on-board controllers */ 2662 return slot == PCI_SLOT(pdev->devfn); 2663 } 2664 2665 return false; 2666 } 2667 2668 static bool ahci_broken_suspend(struct pci_dev *pdev) 2669 { 2670 static const struct dmi_system_id sysids[] = { 2671 /* 2672 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 2673 * to the harddisk doesn't become online after 2674 * resuming from STR. Warn and fail suspend. 2675 */ 2676 { 2677 .ident = "dv4", 2678 .matches = { 2679 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 2680 DMI_MATCH(DMI_PRODUCT_NAME, 2681 "HP Pavilion dv4 Notebook PC"), 2682 }, 2683 .driver_data = "F.30", /* cutoff BIOS version */ 2684 }, 2685 { 2686 .ident = "dv5", 2687 .matches = { 2688 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 2689 DMI_MATCH(DMI_PRODUCT_NAME, 2690 "HP Pavilion dv5 Notebook PC"), 2691 }, 2692 .driver_data = "F.16", /* cutoff BIOS version */ 2693 }, 2694 { 2695 .ident = "dv6", 2696 .matches = { 2697 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 2698 DMI_MATCH(DMI_PRODUCT_NAME, 2699 "HP Pavilion dv6 Notebook PC"), 2700 }, 2701 .driver_data = "F.21", /* cutoff BIOS version */ 2702 }, 2703 { 2704 .ident = "HDX18", 2705 .matches = { 2706 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 2707 DMI_MATCH(DMI_PRODUCT_NAME, 2708 "HP HDX18 Notebook PC"), 2709 }, 2710 .driver_data = "F.23", /* cutoff BIOS version */ 2711 }, 2712 { } /* terminate list */ 2713 }; 2714 const struct dmi_system_id *dmi = dmi_first_match(sysids); 2715 const char *ver; 2716 2717 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 2718 return false; 2719 2720 ver = dmi_get_system_info(DMI_BIOS_VERSION); 2721 2722 return !ver || strcmp(ver, dmi->driver_data) < 0; 2723 } 2724 2725 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 2726 { 2727 static int printed_version; 2728 unsigned int board_id = ent->driver_data; 2729 struct ata_port_info pi = ahci_port_info[board_id]; 2730 const struct ata_port_info *ppi[] = { &pi, NULL }; 2731 struct device *dev = &pdev->dev; 2732 struct ahci_host_priv *hpriv; 2733 struct ata_host *host; 2734 int n_ports, i, rc; 2735 2736 VPRINTK("ENTER\n"); 2737 2738 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); 2739 2740 if (!printed_version++) 2741 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 2742 2743 /* The AHCI driver can only drive the SATA ports, the PATA driver 2744 can drive them all so if both drivers are selected make sure 2745 AHCI stays out of the way */ 2746 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 2747 return -ENODEV; 2748 2749 /* acquire resources */ 2750 rc = pcim_enable_device(pdev); 2751 if (rc) 2752 return rc; 2753 2754 /* AHCI controllers often implement SFF compatible interface. 2755 * Grab all PCI BARs just in case. 2756 */ 2757 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); 2758 if (rc == -EBUSY) 2759 pcim_pin_device(pdev); 2760 if (rc) 2761 return rc; 2762 2763 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 2764 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 2765 u8 map; 2766 2767 /* ICH6s share the same PCI ID for both piix and ahci 2768 * modes. Enabling ahci mode while MAP indicates 2769 * combined mode is a bad idea. Yield to ata_piix. 2770 */ 2771 pci_read_config_byte(pdev, ICH_MAP, &map); 2772 if (map & 0x3) { 2773 dev_printk(KERN_INFO, &pdev->dev, "controller is in " 2774 "combined mode, can't enable AHCI mode\n"); 2775 return -ENODEV; 2776 } 2777 } 2778 2779 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 2780 if (!hpriv) 2781 return -ENOMEM; 2782 hpriv->flags |= (unsigned long)pi.private_data; 2783 2784 /* MCP65 revision A1 and A2 can't do MSI */ 2785 if (board_id == board_ahci_mcp65 && 2786 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 2787 hpriv->flags |= AHCI_HFLAG_NO_MSI; 2788 2789 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 2790 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 2791 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 2792 2793 /* apply ASUS M2A_VM quirk */ 2794 if (ahci_asus_m2a_vm_32bit_only(pdev)) 2795 hpriv->flags |= AHCI_HFLAG_32BIT_ONLY; 2796 2797 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) 2798 pci_enable_msi(pdev); 2799 2800 /* save initial config */ 2801 ahci_save_initial_config(pdev, hpriv); 2802 2803 /* prepare host */ 2804 if (hpriv->cap & HOST_CAP_NCQ) 2805 pi.flags |= ATA_FLAG_NCQ; 2806 2807 if (hpriv->cap & HOST_CAP_PMP) 2808 pi.flags |= ATA_FLAG_PMP; 2809 2810 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) { 2811 u8 messages; 2812 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; 2813 u32 em_loc = readl(mmio + HOST_EM_LOC); 2814 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2815 2816 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2817 2818 /* we only support LED message type right now */ 2819 if ((messages & 0x01) && (ahci_em_messages == 1)) { 2820 /* store em_loc */ 2821 hpriv->em_loc = ((em_loc >> 16) * 4); 2822 pi.flags |= ATA_FLAG_EM; 2823 if (!(em_ctl & EM_CTL_ALHD)) 2824 pi.flags |= ATA_FLAG_SW_ACTIVITY; 2825 } 2826 } 2827 2828 if (ahci_broken_system_poweroff(pdev)) { 2829 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 2830 dev_info(&pdev->dev, 2831 "quirky BIOS, skipping spindown on poweroff\n"); 2832 } 2833 2834 if (ahci_broken_suspend(pdev)) { 2835 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 2836 dev_printk(KERN_WARNING, &pdev->dev, 2837 "BIOS update required for suspend/resume\n"); 2838 } 2839 2840 /* CAP.NP sometimes indicate the index of the last enabled 2841 * port, at other times, that of the last possible port, so 2842 * determining the maximum port number requires looking at 2843 * both CAP.NP and port_map. 2844 */ 2845 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 2846 2847 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 2848 if (!host) 2849 return -ENOMEM; 2850 host->iomap = pcim_iomap_table(pdev); 2851 host->private_data = hpriv; 2852 2853 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 2854 host->flags |= ATA_HOST_PARALLEL_SCAN; 2855 else 2856 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n"); 2857 2858 if (pi.flags & ATA_FLAG_EM) 2859 ahci_reset_em(host); 2860 2861 for (i = 0; i < host->n_ports; i++) { 2862 struct ata_port *ap = host->ports[i]; 2863 2864 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); 2865 ata_port_pbar_desc(ap, AHCI_PCI_BAR, 2866 0x100 + ap->port_no * 0x80, "port"); 2867 2868 /* set initial link pm policy */ 2869 ap->pm_policy = NOT_AVAILABLE; 2870 2871 /* set enclosure management message type */ 2872 if (ap->flags & ATA_FLAG_EM) 2873 ap->em_message_type = ahci_em_messages; 2874 2875 2876 /* disabled/not-implemented port */ 2877 if (!(hpriv->port_map & (1 << i))) 2878 ap->ops = &ata_dummy_port_ops; 2879 } 2880 2881 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 2882 ahci_p5wdh_workaround(host); 2883 2884 /* initialize adapter */ 2885 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 2886 if (rc) 2887 return rc; 2888 2889 rc = ahci_reset_controller(host); 2890 if (rc) 2891 return rc; 2892 2893 ahci_init_controller(host); 2894 ahci_print_info(host); 2895 2896 pci_set_master(pdev); 2897 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, 2898 &ahci_sht); 2899 } 2900 2901 static int __init ahci_init(void) 2902 { 2903 return pci_register_driver(&ahci_pci_driver); 2904 } 2905 2906 static void __exit ahci_exit(void) 2907 { 2908 pci_unregister_driver(&ahci_pci_driver); 2909 } 2910 2911 2912 MODULE_AUTHOR("Jeff Garzik"); 2913 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 2914 MODULE_LICENSE("GPL"); 2915 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 2916 MODULE_VERSION(DRV_VERSION); 2917 2918 module_init(ahci_init); 2919 module_exit(ahci_exit); 2920