1 /* 2 * ahci.c - AHCI SATA support 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/init.h> 39 #include <linux/blkdev.h> 40 #include <linux/delay.h> 41 #include <linux/interrupt.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/device.h> 44 #include <linux/dmi.h> 45 #include <linux/gfp.h> 46 #include <scsi/scsi_host.h> 47 #include <scsi/scsi_cmnd.h> 48 #include <linux/libata.h> 49 #include "ahci.h" 50 51 #define DRV_NAME "ahci" 52 #define DRV_VERSION "3.0" 53 54 enum { 55 AHCI_PCI_BAR_STA2X11 = 0, 56 AHCI_PCI_BAR_STANDARD = 5, 57 }; 58 59 enum board_ids { 60 /* board IDs by feature in alphabetical order */ 61 board_ahci, 62 board_ahci_ign_iferr, 63 board_ahci_nosntf, 64 board_ahci_yes_fbs, 65 66 /* board IDs for specific chipsets in alphabetical order */ 67 board_ahci_mcp65, 68 board_ahci_mcp77, 69 board_ahci_mcp89, 70 board_ahci_mv, 71 board_ahci_sb600, 72 board_ahci_sb700, /* for SB700 and SB800 */ 73 board_ahci_vt8251, 74 75 /* aliases */ 76 board_ahci_mcp_linux = board_ahci_mcp65, 77 board_ahci_mcp67 = board_ahci_mcp65, 78 board_ahci_mcp73 = board_ahci_mcp65, 79 board_ahci_mcp79 = board_ahci_mcp77, 80 }; 81 82 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 83 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 84 unsigned long deadline); 85 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 86 unsigned long deadline); 87 #ifdef CONFIG_PM 88 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 89 static int ahci_pci_device_resume(struct pci_dev *pdev); 90 #endif 91 92 static struct scsi_host_template ahci_sht = { 93 AHCI_SHT("ahci"), 94 }; 95 96 static struct ata_port_operations ahci_vt8251_ops = { 97 .inherits = &ahci_ops, 98 .hardreset = ahci_vt8251_hardreset, 99 }; 100 101 static struct ata_port_operations ahci_p5wdh_ops = { 102 .inherits = &ahci_ops, 103 .hardreset = ahci_p5wdh_hardreset, 104 }; 105 106 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) 107 108 static const struct ata_port_info ahci_port_info[] = { 109 /* by features */ 110 [board_ahci] = 111 { 112 .flags = AHCI_FLAG_COMMON, 113 .pio_mask = ATA_PIO4, 114 .udma_mask = ATA_UDMA6, 115 .port_ops = &ahci_ops, 116 }, 117 [board_ahci_ign_iferr] = 118 { 119 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 120 .flags = AHCI_FLAG_COMMON, 121 .pio_mask = ATA_PIO4, 122 .udma_mask = ATA_UDMA6, 123 .port_ops = &ahci_ops, 124 }, 125 [board_ahci_nosntf] = 126 { 127 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 128 .flags = AHCI_FLAG_COMMON, 129 .pio_mask = ATA_PIO4, 130 .udma_mask = ATA_UDMA6, 131 .port_ops = &ahci_ops, 132 }, 133 [board_ahci_yes_fbs] = 134 { 135 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 136 .flags = AHCI_FLAG_COMMON, 137 .pio_mask = ATA_PIO4, 138 .udma_mask = ATA_UDMA6, 139 .port_ops = &ahci_ops, 140 }, 141 /* by chipsets */ 142 [board_ahci_mcp65] = 143 { 144 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 145 AHCI_HFLAG_YES_NCQ), 146 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 147 .pio_mask = ATA_PIO4, 148 .udma_mask = ATA_UDMA6, 149 .port_ops = &ahci_ops, 150 }, 151 [board_ahci_mcp77] = 152 { 153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 154 .flags = AHCI_FLAG_COMMON, 155 .pio_mask = ATA_PIO4, 156 .udma_mask = ATA_UDMA6, 157 .port_ops = &ahci_ops, 158 }, 159 [board_ahci_mcp89] = 160 { 161 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 162 .flags = AHCI_FLAG_COMMON, 163 .pio_mask = ATA_PIO4, 164 .udma_mask = ATA_UDMA6, 165 .port_ops = &ahci_ops, 166 }, 167 [board_ahci_mv] = 168 { 169 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 170 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 171 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 172 .pio_mask = ATA_PIO4, 173 .udma_mask = ATA_UDMA6, 174 .port_ops = &ahci_ops, 175 }, 176 [board_ahci_sb600] = 177 { 178 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 179 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 180 AHCI_HFLAG_32BIT_ONLY), 181 .flags = AHCI_FLAG_COMMON, 182 .pio_mask = ATA_PIO4, 183 .udma_mask = ATA_UDMA6, 184 .port_ops = &ahci_pmp_retry_srst_ops, 185 }, 186 [board_ahci_sb700] = /* for SB700 and SB800 */ 187 { 188 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 189 .flags = AHCI_FLAG_COMMON, 190 .pio_mask = ATA_PIO4, 191 .udma_mask = ATA_UDMA6, 192 .port_ops = &ahci_pmp_retry_srst_ops, 193 }, 194 [board_ahci_vt8251] = 195 { 196 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 197 .flags = AHCI_FLAG_COMMON, 198 .pio_mask = ATA_PIO4, 199 .udma_mask = ATA_UDMA6, 200 .port_ops = &ahci_vt8251_ops, 201 }, 202 }; 203 204 static const struct pci_device_id ahci_pci_tbl[] = { 205 /* Intel */ 206 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 207 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 208 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 209 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 210 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 211 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 212 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 213 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 214 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 215 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 216 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 217 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ 218 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 219 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 220 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 221 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 222 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 223 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 224 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 225 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 226 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ 227 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ 228 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ 229 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ 230 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ 231 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 232 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ 233 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 234 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 235 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 236 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 237 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 238 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 239 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 240 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 241 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 242 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */ 243 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 244 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */ 245 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 246 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 247 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */ 248 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 249 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */ 250 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 251 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 252 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 253 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 254 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 255 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ 256 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 257 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 258 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */ 259 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 260 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 261 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 262 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */ 263 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 264 265 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 266 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 267 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 268 269 /* ATI */ 270 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 271 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 272 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 273 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 274 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 275 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 276 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 277 278 /* AMD */ 279 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 280 /* AMD is using RAID class only for ahci controllers */ 281 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 282 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 283 284 /* VIA */ 285 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 286 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 287 288 /* NVIDIA */ 289 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 290 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 291 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 292 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 293 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 294 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 295 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 296 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 297 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 298 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 299 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 300 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 301 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 302 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 303 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 304 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 305 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 306 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 307 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 308 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 309 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 310 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 311 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 312 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 313 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 314 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 315 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 316 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 317 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 318 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 319 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 320 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 321 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 322 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 323 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 324 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 325 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 326 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 327 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 328 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 329 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 330 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 331 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 332 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 333 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 334 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 335 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 336 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 337 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 338 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 339 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 340 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 341 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 342 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 343 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 344 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 345 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 346 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 347 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 348 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 349 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 350 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 351 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 352 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 353 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 354 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 355 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 356 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 357 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 358 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 359 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 360 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 361 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 362 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 363 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 364 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 365 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 366 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 367 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 368 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 369 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 370 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 371 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 372 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 373 374 /* SiS */ 375 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 376 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 377 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 378 379 /* ST Microelectronics */ 380 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 381 382 /* Marvell */ 383 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 384 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 385 { PCI_DEVICE(0x1b4b, 0x9123), 386 .class = PCI_CLASS_STORAGE_SATA_AHCI, 387 .class_mask = 0xffffff, 388 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 389 { PCI_DEVICE(0x1b4b, 0x9125), 390 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 391 { PCI_DEVICE(0x1b4b, 0x91a3), 392 .driver_data = board_ahci_yes_fbs }, 393 394 /* Promise */ 395 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 396 397 /* Asmedia */ 398 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1061 */ 399 400 /* Generic, PCI class code for AHCI */ 401 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 402 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 403 404 { } /* terminate list */ 405 }; 406 407 408 static struct pci_driver ahci_pci_driver = { 409 .name = DRV_NAME, 410 .id_table = ahci_pci_tbl, 411 .probe = ahci_init_one, 412 .remove = ata_pci_remove_one, 413 #ifdef CONFIG_PM 414 .suspend = ahci_pci_device_suspend, 415 .resume = ahci_pci_device_resume, 416 #endif 417 }; 418 419 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE) 420 static int marvell_enable; 421 #else 422 static int marvell_enable = 1; 423 #endif 424 module_param(marvell_enable, int, 0644); 425 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 426 427 428 static void ahci_pci_save_initial_config(struct pci_dev *pdev, 429 struct ahci_host_priv *hpriv) 430 { 431 unsigned int force_port_map = 0; 432 unsigned int mask_port_map = 0; 433 434 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 435 dev_info(&pdev->dev, "JMB361 has only one port\n"); 436 force_port_map = 1; 437 } 438 439 /* 440 * Temporary Marvell 6145 hack: PATA port presence 441 * is asserted through the standard AHCI port 442 * presence register, as bit 4 (counting from 0) 443 */ 444 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 445 if (pdev->device == 0x6121) 446 mask_port_map = 0x3; 447 else 448 mask_port_map = 0xf; 449 dev_info(&pdev->dev, 450 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 451 } 452 453 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map, 454 mask_port_map); 455 } 456 457 static int ahci_pci_reset_controller(struct ata_host *host) 458 { 459 struct pci_dev *pdev = to_pci_dev(host->dev); 460 461 ahci_reset_controller(host); 462 463 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 464 struct ahci_host_priv *hpriv = host->private_data; 465 u16 tmp16; 466 467 /* configure PCS */ 468 pci_read_config_word(pdev, 0x92, &tmp16); 469 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 470 tmp16 |= hpriv->port_map; 471 pci_write_config_word(pdev, 0x92, tmp16); 472 } 473 } 474 475 return 0; 476 } 477 478 static void ahci_pci_init_controller(struct ata_host *host) 479 { 480 struct ahci_host_priv *hpriv = host->private_data; 481 struct pci_dev *pdev = to_pci_dev(host->dev); 482 void __iomem *port_mmio; 483 u32 tmp; 484 int mv; 485 486 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 487 if (pdev->device == 0x6121) 488 mv = 2; 489 else 490 mv = 4; 491 port_mmio = __ahci_port_base(host, mv); 492 493 writel(0, port_mmio + PORT_IRQ_MASK); 494 495 /* clear port IRQ */ 496 tmp = readl(port_mmio + PORT_IRQ_STAT); 497 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 498 if (tmp) 499 writel(tmp, port_mmio + PORT_IRQ_STAT); 500 } 501 502 ahci_init_controller(host); 503 } 504 505 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 506 unsigned long deadline) 507 { 508 struct ata_port *ap = link->ap; 509 bool online; 510 int rc; 511 512 DPRINTK("ENTER\n"); 513 514 ahci_stop_engine(ap); 515 516 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 517 deadline, &online, NULL); 518 519 ahci_start_engine(ap); 520 521 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 522 523 /* vt8251 doesn't clear BSY on signature FIS reception, 524 * request follow-up softreset. 525 */ 526 return online ? -EAGAIN : rc; 527 } 528 529 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 530 unsigned long deadline) 531 { 532 struct ata_port *ap = link->ap; 533 struct ahci_port_priv *pp = ap->private_data; 534 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 535 struct ata_taskfile tf; 536 bool online; 537 int rc; 538 539 ahci_stop_engine(ap); 540 541 /* clear D2H reception area to properly wait for D2H FIS */ 542 ata_tf_init(link->device, &tf); 543 tf.command = 0x80; 544 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 545 546 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 547 deadline, &online, NULL); 548 549 ahci_start_engine(ap); 550 551 /* The pseudo configuration device on SIMG4726 attached to 552 * ASUS P5W-DH Deluxe doesn't send signature FIS after 553 * hardreset if no device is attached to the first downstream 554 * port && the pseudo device locks up on SRST w/ PMP==0. To 555 * work around this, wait for !BSY only briefly. If BSY isn't 556 * cleared, perform CLO and proceed to IDENTIFY (achieved by 557 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 558 * 559 * Wait for two seconds. Devices attached to downstream port 560 * which can't process the following IDENTIFY after this will 561 * have to be reset again. For most cases, this should 562 * suffice while making probing snappish enough. 563 */ 564 if (online) { 565 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 566 ahci_check_ready); 567 if (rc) 568 ahci_kick_engine(ap); 569 } 570 return rc; 571 } 572 573 #ifdef CONFIG_PM 574 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 575 { 576 struct ata_host *host = dev_get_drvdata(&pdev->dev); 577 struct ahci_host_priv *hpriv = host->private_data; 578 void __iomem *mmio = hpriv->mmio; 579 u32 ctl; 580 581 if (mesg.event & PM_EVENT_SUSPEND && 582 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 583 dev_err(&pdev->dev, 584 "BIOS update required for suspend/resume\n"); 585 return -EIO; 586 } 587 588 if (mesg.event & PM_EVENT_SLEEP) { 589 /* AHCI spec rev1.1 section 8.3.3: 590 * Software must disable interrupts prior to requesting a 591 * transition of the HBA to D3 state. 592 */ 593 ctl = readl(mmio + HOST_CTL); 594 ctl &= ~HOST_IRQ_EN; 595 writel(ctl, mmio + HOST_CTL); 596 readl(mmio + HOST_CTL); /* flush */ 597 } 598 599 return ata_pci_device_suspend(pdev, mesg); 600 } 601 602 static int ahci_pci_device_resume(struct pci_dev *pdev) 603 { 604 struct ata_host *host = dev_get_drvdata(&pdev->dev); 605 int rc; 606 607 rc = ata_pci_device_do_resume(pdev); 608 if (rc) 609 return rc; 610 611 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 612 rc = ahci_pci_reset_controller(host); 613 if (rc) 614 return rc; 615 616 ahci_pci_init_controller(host); 617 } 618 619 ata_host_resume(host); 620 621 return 0; 622 } 623 #endif 624 625 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 626 { 627 int rc; 628 629 /* 630 * If the device fixup already set the dma_mask to some non-standard 631 * value, don't extend it here. This happens on STA2X11, for example. 632 */ 633 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 634 return 0; 635 636 if (using_dac && 637 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 638 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 639 if (rc) { 640 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 641 if (rc) { 642 dev_err(&pdev->dev, 643 "64-bit DMA enable failed\n"); 644 return rc; 645 } 646 } 647 } else { 648 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 649 if (rc) { 650 dev_err(&pdev->dev, "32-bit DMA enable failed\n"); 651 return rc; 652 } 653 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 654 if (rc) { 655 dev_err(&pdev->dev, 656 "32-bit consistent DMA enable failed\n"); 657 return rc; 658 } 659 } 660 return 0; 661 } 662 663 static void ahci_pci_print_info(struct ata_host *host) 664 { 665 struct pci_dev *pdev = to_pci_dev(host->dev); 666 u16 cc; 667 const char *scc_s; 668 669 pci_read_config_word(pdev, 0x0a, &cc); 670 if (cc == PCI_CLASS_STORAGE_IDE) 671 scc_s = "IDE"; 672 else if (cc == PCI_CLASS_STORAGE_SATA) 673 scc_s = "SATA"; 674 else if (cc == PCI_CLASS_STORAGE_RAID) 675 scc_s = "RAID"; 676 else 677 scc_s = "unknown"; 678 679 ahci_print_info(host, scc_s); 680 } 681 682 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 683 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 684 * support PMP and the 4726 either directly exports the device 685 * attached to the first downstream port or acts as a hardware storage 686 * controller and emulate a single ATA device (can be RAID 0/1 or some 687 * other configuration). 688 * 689 * When there's no device attached to the first downstream port of the 690 * 4726, "Config Disk" appears, which is a pseudo ATA device to 691 * configure the 4726. However, ATA emulation of the device is very 692 * lame. It doesn't send signature D2H Reg FIS after the initial 693 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 694 * 695 * The following function works around the problem by always using 696 * hardreset on the port and not depending on receiving signature FIS 697 * afterward. If signature FIS isn't received soon, ATA class is 698 * assumed without follow-up softreset. 699 */ 700 static void ahci_p5wdh_workaround(struct ata_host *host) 701 { 702 static struct dmi_system_id sysids[] = { 703 { 704 .ident = "P5W DH Deluxe", 705 .matches = { 706 DMI_MATCH(DMI_SYS_VENDOR, 707 "ASUSTEK COMPUTER INC"), 708 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 709 }, 710 }, 711 { } 712 }; 713 struct pci_dev *pdev = to_pci_dev(host->dev); 714 715 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 716 dmi_check_system(sysids)) { 717 struct ata_port *ap = host->ports[1]; 718 719 dev_info(&pdev->dev, 720 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 721 722 ap->ops = &ahci_p5wdh_ops; 723 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 724 } 725 } 726 727 /* only some SB600 ahci controllers can do 64bit DMA */ 728 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 729 { 730 static const struct dmi_system_id sysids[] = { 731 /* 732 * The oldest version known to be broken is 0901 and 733 * working is 1501 which was released on 2007-10-26. 734 * Enable 64bit DMA on 1501 and anything newer. 735 * 736 * Please read bko#9412 for more info. 737 */ 738 { 739 .ident = "ASUS M2A-VM", 740 .matches = { 741 DMI_MATCH(DMI_BOARD_VENDOR, 742 "ASUSTeK Computer INC."), 743 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 744 }, 745 .driver_data = "20071026", /* yyyymmdd */ 746 }, 747 /* 748 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 749 * support 64bit DMA. 750 * 751 * BIOS versions earlier than 1.5 had the Manufacturer DMI 752 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 753 * This spelling mistake was fixed in BIOS version 1.5, so 754 * 1.5 and later have the Manufacturer as 755 * "MICRO-STAR INTERNATIONAL CO.,LTD". 756 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 757 * 758 * BIOS versions earlier than 1.9 had a Board Product Name 759 * DMI field of "MS-7376". This was changed to be 760 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 761 * match on DMI_BOARD_NAME of "MS-7376". 762 */ 763 { 764 .ident = "MSI K9A2 Platinum", 765 .matches = { 766 DMI_MATCH(DMI_BOARD_VENDOR, 767 "MICRO-STAR INTER"), 768 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 769 }, 770 }, 771 /* 772 * All BIOS versions for the Asus M3A support 64bit DMA. 773 * (all release versions from 0301 to 1206 were tested) 774 */ 775 { 776 .ident = "ASUS M3A", 777 .matches = { 778 DMI_MATCH(DMI_BOARD_VENDOR, 779 "ASUSTeK Computer INC."), 780 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 781 }, 782 }, 783 { } 784 }; 785 const struct dmi_system_id *match; 786 int year, month, date; 787 char buf[9]; 788 789 match = dmi_first_match(sysids); 790 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 791 !match) 792 return false; 793 794 if (!match->driver_data) 795 goto enable_64bit; 796 797 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 798 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 799 800 if (strcmp(buf, match->driver_data) >= 0) 801 goto enable_64bit; 802 else { 803 dev_warn(&pdev->dev, 804 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 805 match->ident); 806 return false; 807 } 808 809 enable_64bit: 810 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 811 return true; 812 } 813 814 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 815 { 816 static const struct dmi_system_id broken_systems[] = { 817 { 818 .ident = "HP Compaq nx6310", 819 .matches = { 820 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 821 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 822 }, 823 /* PCI slot number of the controller */ 824 .driver_data = (void *)0x1FUL, 825 }, 826 { 827 .ident = "HP Compaq 6720s", 828 .matches = { 829 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 830 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 831 }, 832 /* PCI slot number of the controller */ 833 .driver_data = (void *)0x1FUL, 834 }, 835 836 { } /* terminate list */ 837 }; 838 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 839 840 if (dmi) { 841 unsigned long slot = (unsigned long)dmi->driver_data; 842 /* apply the quirk only to on-board controllers */ 843 return slot == PCI_SLOT(pdev->devfn); 844 } 845 846 return false; 847 } 848 849 static bool ahci_broken_suspend(struct pci_dev *pdev) 850 { 851 static const struct dmi_system_id sysids[] = { 852 /* 853 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 854 * to the harddisk doesn't become online after 855 * resuming from STR. Warn and fail suspend. 856 * 857 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 858 * 859 * Use dates instead of versions to match as HP is 860 * apparently recycling both product and version 861 * strings. 862 * 863 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 864 */ 865 { 866 .ident = "dv4", 867 .matches = { 868 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 869 DMI_MATCH(DMI_PRODUCT_NAME, 870 "HP Pavilion dv4 Notebook PC"), 871 }, 872 .driver_data = "20090105", /* F.30 */ 873 }, 874 { 875 .ident = "dv5", 876 .matches = { 877 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 878 DMI_MATCH(DMI_PRODUCT_NAME, 879 "HP Pavilion dv5 Notebook PC"), 880 }, 881 .driver_data = "20090506", /* F.16 */ 882 }, 883 { 884 .ident = "dv6", 885 .matches = { 886 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 887 DMI_MATCH(DMI_PRODUCT_NAME, 888 "HP Pavilion dv6 Notebook PC"), 889 }, 890 .driver_data = "20090423", /* F.21 */ 891 }, 892 { 893 .ident = "HDX18", 894 .matches = { 895 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 896 DMI_MATCH(DMI_PRODUCT_NAME, 897 "HP HDX18 Notebook PC"), 898 }, 899 .driver_data = "20090430", /* F.23 */ 900 }, 901 /* 902 * Acer eMachines G725 has the same problem. BIOS 903 * V1.03 is known to be broken. V3.04 is known to 904 * work. Between, there are V1.06, V2.06 and V3.03 905 * that we don't have much idea about. For now, 906 * blacklist anything older than V3.04. 907 * 908 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 909 */ 910 { 911 .ident = "G725", 912 .matches = { 913 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 914 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 915 }, 916 .driver_data = "20091216", /* V3.04 */ 917 }, 918 { } /* terminate list */ 919 }; 920 const struct dmi_system_id *dmi = dmi_first_match(sysids); 921 int year, month, date; 922 char buf[9]; 923 924 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 925 return false; 926 927 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 928 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 929 930 return strcmp(buf, dmi->driver_data) < 0; 931 } 932 933 static bool ahci_broken_online(struct pci_dev *pdev) 934 { 935 #define ENCODE_BUSDEVFN(bus, slot, func) \ 936 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 937 static const struct dmi_system_id sysids[] = { 938 /* 939 * There are several gigabyte boards which use 940 * SIMG5723s configured as hardware RAID. Certain 941 * 5723 firmware revisions shipped there keep the link 942 * online but fail to answer properly to SRST or 943 * IDENTIFY when no device is attached downstream 944 * causing libata to retry quite a few times leading 945 * to excessive detection delay. 946 * 947 * As these firmwares respond to the second reset try 948 * with invalid device signature, considering unknown 949 * sig as offline works around the problem acceptably. 950 */ 951 { 952 .ident = "EP45-DQ6", 953 .matches = { 954 DMI_MATCH(DMI_BOARD_VENDOR, 955 "Gigabyte Technology Co., Ltd."), 956 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 957 }, 958 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 959 }, 960 { 961 .ident = "EP45-DS5", 962 .matches = { 963 DMI_MATCH(DMI_BOARD_VENDOR, 964 "Gigabyte Technology Co., Ltd."), 965 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 966 }, 967 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 968 }, 969 { } /* terminate list */ 970 }; 971 #undef ENCODE_BUSDEVFN 972 const struct dmi_system_id *dmi = dmi_first_match(sysids); 973 unsigned int val; 974 975 if (!dmi) 976 return false; 977 978 val = (unsigned long)dmi->driver_data; 979 980 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 981 } 982 983 #ifdef CONFIG_ATA_ACPI 984 static void ahci_gtf_filter_workaround(struct ata_host *host) 985 { 986 static const struct dmi_system_id sysids[] = { 987 /* 988 * Aspire 3810T issues a bunch of SATA enable commands 989 * via _GTF including an invalid one and one which is 990 * rejected by the device. Among the successful ones 991 * is FPDMA non-zero offset enable which when enabled 992 * only on the drive side leads to NCQ command 993 * failures. Filter it out. 994 */ 995 { 996 .ident = "Aspire 3810T", 997 .matches = { 998 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 999 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1000 }, 1001 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1002 }, 1003 { } 1004 }; 1005 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1006 unsigned int filter; 1007 int i; 1008 1009 if (!dmi) 1010 return; 1011 1012 filter = (unsigned long)dmi->driver_data; 1013 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1014 filter, dmi->ident); 1015 1016 for (i = 0; i < host->n_ports; i++) { 1017 struct ata_port *ap = host->ports[i]; 1018 struct ata_link *link; 1019 struct ata_device *dev; 1020 1021 ata_for_each_link(link, ap, EDGE) 1022 ata_for_each_dev(dev, link, ALL) 1023 dev->gtf_filter |= filter; 1024 } 1025 } 1026 #else 1027 static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1028 {} 1029 #endif 1030 1031 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1032 { 1033 unsigned int board_id = ent->driver_data; 1034 struct ata_port_info pi = ahci_port_info[board_id]; 1035 const struct ata_port_info *ppi[] = { &pi, NULL }; 1036 struct device *dev = &pdev->dev; 1037 struct ahci_host_priv *hpriv; 1038 struct ata_host *host; 1039 int n_ports, i, rc; 1040 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1041 1042 VPRINTK("ENTER\n"); 1043 1044 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1045 1046 ata_print_version_once(&pdev->dev, DRV_VERSION); 1047 1048 /* The AHCI driver can only drive the SATA ports, the PATA driver 1049 can drive them all so if both drivers are selected make sure 1050 AHCI stays out of the way */ 1051 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1052 return -ENODEV; 1053 1054 /* 1055 * For some reason, MCP89 on MacBook 7,1 doesn't work with 1056 * ahci, use ata_generic instead. 1057 */ 1058 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1059 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1060 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1061 pdev->subsystem_device == 0xcb89) 1062 return -ENODEV; 1063 1064 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1065 * At the moment, we can only use the AHCI mode. Let the users know 1066 * that for SAS drives they're out of luck. 1067 */ 1068 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1069 dev_info(&pdev->dev, 1070 "PDC42819 can only drive SATA devices with this driver\n"); 1071 1072 /* The Connext uses non-standard BAR */ 1073 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1074 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1075 1076 /* acquire resources */ 1077 rc = pcim_enable_device(pdev); 1078 if (rc) 1079 return rc; 1080 1081 /* AHCI controllers often implement SFF compatible interface. 1082 * Grab all PCI BARs just in case. 1083 */ 1084 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1085 if (rc == -EBUSY) 1086 pcim_pin_device(pdev); 1087 if (rc) 1088 return rc; 1089 1090 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1091 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1092 u8 map; 1093 1094 /* ICH6s share the same PCI ID for both piix and ahci 1095 * modes. Enabling ahci mode while MAP indicates 1096 * combined mode is a bad idea. Yield to ata_piix. 1097 */ 1098 pci_read_config_byte(pdev, ICH_MAP, &map); 1099 if (map & 0x3) { 1100 dev_info(&pdev->dev, 1101 "controller is in combined mode, can't enable AHCI mode\n"); 1102 return -ENODEV; 1103 } 1104 } 1105 1106 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1107 if (!hpriv) 1108 return -ENOMEM; 1109 hpriv->flags |= (unsigned long)pi.private_data; 1110 1111 /* MCP65 revision A1 and A2 can't do MSI */ 1112 if (board_id == board_ahci_mcp65 && 1113 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1114 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1115 1116 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1117 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1118 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1119 1120 /* only some SB600s can do 64bit DMA */ 1121 if (ahci_sb600_enable_64bit(pdev)) 1122 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1123 1124 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev)) 1125 pci_intx(pdev, 1); 1126 1127 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1128 1129 /* save initial config */ 1130 ahci_pci_save_initial_config(pdev, hpriv); 1131 1132 /* prepare host */ 1133 if (hpriv->cap & HOST_CAP_NCQ) { 1134 pi.flags |= ATA_FLAG_NCQ; 1135 /* 1136 * Auto-activate optimization is supposed to be 1137 * supported on all AHCI controllers indicating NCQ 1138 * capability, but it seems to be broken on some 1139 * chipsets including NVIDIAs. 1140 */ 1141 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1142 pi.flags |= ATA_FLAG_FPDMA_AA; 1143 } 1144 1145 if (hpriv->cap & HOST_CAP_PMP) 1146 pi.flags |= ATA_FLAG_PMP; 1147 1148 ahci_set_em_messages(hpriv, &pi); 1149 1150 if (ahci_broken_system_poweroff(pdev)) { 1151 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1152 dev_info(&pdev->dev, 1153 "quirky BIOS, skipping spindown on poweroff\n"); 1154 } 1155 1156 if (ahci_broken_suspend(pdev)) { 1157 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1158 dev_warn(&pdev->dev, 1159 "BIOS update required for suspend/resume\n"); 1160 } 1161 1162 if (ahci_broken_online(pdev)) { 1163 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1164 dev_info(&pdev->dev, 1165 "online status unreliable, applying workaround\n"); 1166 } 1167 1168 /* CAP.NP sometimes indicate the index of the last enabled 1169 * port, at other times, that of the last possible port, so 1170 * determining the maximum port number requires looking at 1171 * both CAP.NP and port_map. 1172 */ 1173 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1174 1175 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1176 if (!host) 1177 return -ENOMEM; 1178 host->private_data = hpriv; 1179 1180 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1181 host->flags |= ATA_HOST_PARALLEL_SCAN; 1182 else 1183 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n"); 1184 1185 if (pi.flags & ATA_FLAG_EM) 1186 ahci_reset_em(host); 1187 1188 for (i = 0; i < host->n_ports; i++) { 1189 struct ata_port *ap = host->ports[i]; 1190 1191 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1192 ata_port_pbar_desc(ap, ahci_pci_bar, 1193 0x100 + ap->port_no * 0x80, "port"); 1194 1195 /* set enclosure management message type */ 1196 if (ap->flags & ATA_FLAG_EM) 1197 ap->em_message_type = hpriv->em_msg_type; 1198 1199 1200 /* disabled/not-implemented port */ 1201 if (!(hpriv->port_map & (1 << i))) 1202 ap->ops = &ata_dummy_port_ops; 1203 } 1204 1205 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1206 ahci_p5wdh_workaround(host); 1207 1208 /* apply gtf filter quirk */ 1209 ahci_gtf_filter_workaround(host); 1210 1211 /* initialize adapter */ 1212 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 1213 if (rc) 1214 return rc; 1215 1216 rc = ahci_pci_reset_controller(host); 1217 if (rc) 1218 return rc; 1219 1220 ahci_pci_init_controller(host); 1221 ahci_pci_print_info(host); 1222 1223 pci_set_master(pdev); 1224 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, 1225 &ahci_sht); 1226 } 1227 1228 static int __init ahci_init(void) 1229 { 1230 return pci_register_driver(&ahci_pci_driver); 1231 } 1232 1233 static void __exit ahci_exit(void) 1234 { 1235 pci_unregister_driver(&ahci_pci_driver); 1236 } 1237 1238 1239 MODULE_AUTHOR("Jeff Garzik"); 1240 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1241 MODULE_LICENSE("GPL"); 1242 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1243 MODULE_VERSION(DRV_VERSION); 1244 1245 module_init(ahci_init); 1246 module_exit(ahci_exit); 1247