1 /* 2 * ahci.c - AHCI SATA support 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/init.h> 39 #include <linux/blkdev.h> 40 #include <linux/delay.h> 41 #include <linux/interrupt.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/device.h> 44 #include <linux/dmi.h> 45 #include <scsi/scsi_host.h> 46 #include <scsi/scsi_cmnd.h> 47 #include <linux/libata.h> 48 49 #define DRV_NAME "ahci" 50 #define DRV_VERSION "3.0" 51 52 static int ahci_enable_alpm(struct ata_port *ap, 53 enum link_pm policy); 54 static void ahci_disable_alpm(struct ata_port *ap); 55 56 enum { 57 AHCI_PCI_BAR = 5, 58 AHCI_MAX_PORTS = 32, 59 AHCI_MAX_SG = 168, /* hardware max is 64K */ 60 AHCI_DMA_BOUNDARY = 0xffffffff, 61 AHCI_USE_CLUSTERING = 1, 62 AHCI_MAX_CMDS = 32, 63 AHCI_CMD_SZ = 32, 64 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, 65 AHCI_RX_FIS_SZ = 256, 66 AHCI_CMD_TBL_CDB = 0x40, 67 AHCI_CMD_TBL_HDR_SZ = 0x80, 68 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), 69 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, 70 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + 71 AHCI_RX_FIS_SZ, 72 AHCI_IRQ_ON_SG = (1 << 31), 73 AHCI_CMD_ATAPI = (1 << 5), 74 AHCI_CMD_WRITE = (1 << 6), 75 AHCI_CMD_PREFETCH = (1 << 7), 76 AHCI_CMD_RESET = (1 << 8), 77 AHCI_CMD_CLR_BUSY = (1 << 10), 78 79 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ 80 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ 81 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ 82 83 board_ahci = 0, 84 board_ahci_vt8251 = 1, 85 board_ahci_ign_iferr = 2, 86 board_ahci_sb600 = 3, 87 board_ahci_mv = 4, 88 89 /* global controller registers */ 90 HOST_CAP = 0x00, /* host capabilities */ 91 HOST_CTL = 0x04, /* global host control */ 92 HOST_IRQ_STAT = 0x08, /* interrupt status */ 93 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ 94 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ 95 96 /* HOST_CTL bits */ 97 HOST_RESET = (1 << 0), /* reset controller; self-clear */ 98 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ 99 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ 100 101 /* HOST_CAP bits */ 102 HOST_CAP_SSC = (1 << 14), /* Slumber capable */ 103 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ 104 HOST_CAP_CLO = (1 << 24), /* Command List Override support */ 105 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ 106 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ 107 HOST_CAP_SNTF = (1 << 29), /* SNotification register */ 108 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ 109 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ 110 111 /* registers for each SATA port */ 112 PORT_LST_ADDR = 0x00, /* command list DMA addr */ 113 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ 114 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ 115 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ 116 PORT_IRQ_STAT = 0x10, /* interrupt status */ 117 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ 118 PORT_CMD = 0x18, /* port command */ 119 PORT_TFDATA = 0x20, /* taskfile data */ 120 PORT_SIG = 0x24, /* device TF signature */ 121 PORT_CMD_ISSUE = 0x38, /* command issue */ 122 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ 123 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ 124 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ 125 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ 126 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ 127 128 /* PORT_IRQ_{STAT,MASK} bits */ 129 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ 130 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ 131 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ 132 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ 133 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ 134 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ 135 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ 136 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ 137 138 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ 139 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ 140 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ 141 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ 142 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ 143 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ 144 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ 145 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ 146 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ 147 148 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | 149 PORT_IRQ_IF_ERR | 150 PORT_IRQ_CONNECT | 151 PORT_IRQ_PHYRDY | 152 PORT_IRQ_UNK_FIS | 153 PORT_IRQ_BAD_PMP, 154 PORT_IRQ_ERROR = PORT_IRQ_FREEZE | 155 PORT_IRQ_TF_ERR | 156 PORT_IRQ_HBUS_DATA_ERR, 157 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | 158 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | 159 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, 160 161 /* PORT_CMD bits */ 162 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ 163 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ 164 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ 165 PORT_CMD_PMP = (1 << 17), /* PMP attached */ 166 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ 167 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ 168 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ 169 PORT_CMD_CLO = (1 << 3), /* Command list override */ 170 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ 171 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ 172 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ 173 174 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ 175 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ 176 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ 177 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ 178 179 /* hpriv->flags bits */ 180 AHCI_HFLAG_NO_NCQ = (1 << 0), 181 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ 182 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ 183 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ 184 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ 185 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ 186 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ 187 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */ 188 189 /* ap->flags bits */ 190 191 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 192 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 193 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | 194 ATA_FLAG_IPM, 195 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY, 196 }; 197 198 struct ahci_cmd_hdr { 199 u32 opts; 200 u32 status; 201 u32 tbl_addr; 202 u32 tbl_addr_hi; 203 u32 reserved[4]; 204 }; 205 206 struct ahci_sg { 207 u32 addr; 208 u32 addr_hi; 209 u32 reserved; 210 u32 flags_size; 211 }; 212 213 struct ahci_host_priv { 214 unsigned int flags; /* AHCI_HFLAG_* */ 215 u32 cap; /* cap to use */ 216 u32 port_map; /* port map to use */ 217 u32 saved_cap; /* saved initial cap */ 218 u32 saved_port_map; /* saved initial port_map */ 219 }; 220 221 struct ahci_port_priv { 222 struct ata_link *active_link; 223 struct ahci_cmd_hdr *cmd_slot; 224 dma_addr_t cmd_slot_dma; 225 void *cmd_tbl; 226 dma_addr_t cmd_tbl_dma; 227 void *rx_fis; 228 dma_addr_t rx_fis_dma; 229 /* for NCQ spurious interrupt analysis */ 230 unsigned int ncq_saw_d2h:1; 231 unsigned int ncq_saw_dmas:1; 232 unsigned int ncq_saw_sdb:1; 233 u32 intr_mask; /* interrupts to enable */ 234 }; 235 236 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); 237 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); 238 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 239 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); 240 static void ahci_irq_clear(struct ata_port *ap); 241 static int ahci_port_start(struct ata_port *ap); 242 static void ahci_port_stop(struct ata_port *ap); 243 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); 244 static void ahci_qc_prep(struct ata_queued_cmd *qc); 245 static u8 ahci_check_status(struct ata_port *ap); 246 static void ahci_freeze(struct ata_port *ap); 247 static void ahci_thaw(struct ata_port *ap); 248 static void ahci_pmp_attach(struct ata_port *ap); 249 static void ahci_pmp_detach(struct ata_port *ap); 250 static void ahci_error_handler(struct ata_port *ap); 251 static void ahci_vt8251_error_handler(struct ata_port *ap); 252 static void ahci_p5wdh_error_handler(struct ata_port *ap); 253 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 254 static int ahci_port_resume(struct ata_port *ap); 255 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl); 256 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 257 u32 opts); 258 #ifdef CONFIG_PM 259 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 260 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 261 static int ahci_pci_device_resume(struct pci_dev *pdev); 262 #endif 263 264 static struct class_device_attribute *ahci_shost_attrs[] = { 265 &class_device_attr_link_power_management_policy, 266 NULL 267 }; 268 269 static struct scsi_host_template ahci_sht = { 270 .module = THIS_MODULE, 271 .name = DRV_NAME, 272 .ioctl = ata_scsi_ioctl, 273 .queuecommand = ata_scsi_queuecmd, 274 .change_queue_depth = ata_scsi_change_queue_depth, 275 .can_queue = AHCI_MAX_CMDS - 1, 276 .this_id = ATA_SHT_THIS_ID, 277 .sg_tablesize = AHCI_MAX_SG, 278 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 279 .emulated = ATA_SHT_EMULATED, 280 .use_clustering = AHCI_USE_CLUSTERING, 281 .proc_name = DRV_NAME, 282 .dma_boundary = AHCI_DMA_BOUNDARY, 283 .slave_configure = ata_scsi_slave_config, 284 .slave_destroy = ata_scsi_slave_destroy, 285 .bios_param = ata_std_bios_param, 286 .shost_attrs = ahci_shost_attrs, 287 }; 288 289 static const struct ata_port_operations ahci_ops = { 290 .check_status = ahci_check_status, 291 .check_altstatus = ahci_check_status, 292 .dev_select = ata_noop_dev_select, 293 294 .tf_read = ahci_tf_read, 295 296 .qc_defer = sata_pmp_qc_defer_cmd_switch, 297 .qc_prep = ahci_qc_prep, 298 .qc_issue = ahci_qc_issue, 299 300 .irq_clear = ahci_irq_clear, 301 302 .scr_read = ahci_scr_read, 303 .scr_write = ahci_scr_write, 304 305 .freeze = ahci_freeze, 306 .thaw = ahci_thaw, 307 308 .error_handler = ahci_error_handler, 309 .post_internal_cmd = ahci_post_internal_cmd, 310 311 .pmp_attach = ahci_pmp_attach, 312 .pmp_detach = ahci_pmp_detach, 313 314 #ifdef CONFIG_PM 315 .port_suspend = ahci_port_suspend, 316 .port_resume = ahci_port_resume, 317 #endif 318 .enable_pm = ahci_enable_alpm, 319 .disable_pm = ahci_disable_alpm, 320 321 .port_start = ahci_port_start, 322 .port_stop = ahci_port_stop, 323 }; 324 325 static const struct ata_port_operations ahci_vt8251_ops = { 326 .check_status = ahci_check_status, 327 .check_altstatus = ahci_check_status, 328 .dev_select = ata_noop_dev_select, 329 330 .tf_read = ahci_tf_read, 331 332 .qc_defer = sata_pmp_qc_defer_cmd_switch, 333 .qc_prep = ahci_qc_prep, 334 .qc_issue = ahci_qc_issue, 335 336 .irq_clear = ahci_irq_clear, 337 338 .scr_read = ahci_scr_read, 339 .scr_write = ahci_scr_write, 340 341 .freeze = ahci_freeze, 342 .thaw = ahci_thaw, 343 344 .error_handler = ahci_vt8251_error_handler, 345 .post_internal_cmd = ahci_post_internal_cmd, 346 347 .pmp_attach = ahci_pmp_attach, 348 .pmp_detach = ahci_pmp_detach, 349 350 #ifdef CONFIG_PM 351 .port_suspend = ahci_port_suspend, 352 .port_resume = ahci_port_resume, 353 #endif 354 355 .port_start = ahci_port_start, 356 .port_stop = ahci_port_stop, 357 }; 358 359 static const struct ata_port_operations ahci_p5wdh_ops = { 360 .check_status = ahci_check_status, 361 .check_altstatus = ahci_check_status, 362 .dev_select = ata_noop_dev_select, 363 364 .tf_read = ahci_tf_read, 365 366 .qc_defer = sata_pmp_qc_defer_cmd_switch, 367 .qc_prep = ahci_qc_prep, 368 .qc_issue = ahci_qc_issue, 369 370 .irq_clear = ahci_irq_clear, 371 372 .scr_read = ahci_scr_read, 373 .scr_write = ahci_scr_write, 374 375 .freeze = ahci_freeze, 376 .thaw = ahci_thaw, 377 378 .error_handler = ahci_p5wdh_error_handler, 379 .post_internal_cmd = ahci_post_internal_cmd, 380 381 .pmp_attach = ahci_pmp_attach, 382 .pmp_detach = ahci_pmp_detach, 383 384 #ifdef CONFIG_PM 385 .port_suspend = ahci_port_suspend, 386 .port_resume = ahci_port_resume, 387 #endif 388 389 .port_start = ahci_port_start, 390 .port_stop = ahci_port_stop, 391 }; 392 393 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) 394 395 static const struct ata_port_info ahci_port_info[] = { 396 /* board_ahci */ 397 { 398 .flags = AHCI_FLAG_COMMON, 399 .link_flags = AHCI_LFLAG_COMMON, 400 .pio_mask = 0x1f, /* pio0-4 */ 401 .udma_mask = ATA_UDMA6, 402 .port_ops = &ahci_ops, 403 }, 404 /* board_ahci_vt8251 */ 405 { 406 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 407 .flags = AHCI_FLAG_COMMON, 408 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME, 409 .pio_mask = 0x1f, /* pio0-4 */ 410 .udma_mask = ATA_UDMA6, 411 .port_ops = &ahci_vt8251_ops, 412 }, 413 /* board_ahci_ign_iferr */ 414 { 415 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 416 .flags = AHCI_FLAG_COMMON, 417 .link_flags = AHCI_LFLAG_COMMON, 418 .pio_mask = 0x1f, /* pio0-4 */ 419 .udma_mask = ATA_UDMA6, 420 .port_ops = &ahci_ops, 421 }, 422 /* board_ahci_sb600 */ 423 { 424 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 425 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP), 426 .flags = AHCI_FLAG_COMMON, 427 .link_flags = AHCI_LFLAG_COMMON, 428 .pio_mask = 0x1f, /* pio0-4 */ 429 .udma_mask = ATA_UDMA6, 430 .port_ops = &ahci_ops, 431 }, 432 /* board_ahci_mv */ 433 { 434 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 435 AHCI_HFLAG_MV_PATA), 436 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 437 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, 438 .link_flags = AHCI_LFLAG_COMMON, 439 .pio_mask = 0x1f, /* pio0-4 */ 440 .udma_mask = ATA_UDMA6, 441 .port_ops = &ahci_ops, 442 }, 443 }; 444 445 static const struct pci_device_id ahci_pci_tbl[] = { 446 /* Intel */ 447 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 448 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 449 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 450 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 451 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 452 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 453 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 454 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 455 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 456 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 457 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 458 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */ 459 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 460 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 461 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 462 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 463 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 464 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 465 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 466 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 467 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ 468 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ 469 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ 470 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ 471 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ 472 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 473 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ 474 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 475 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 476 477 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 478 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 479 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 480 481 /* ATI */ 482 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 483 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */ 484 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */ 485 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */ 486 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */ 487 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */ 488 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */ 489 490 /* VIA */ 491 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 492 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 493 494 /* NVIDIA */ 495 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ 496 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ 497 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ 498 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ 499 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ 500 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ 501 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ 502 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ 503 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ 504 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ 505 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ 506 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ 507 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ 508 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ 509 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ 510 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ 511 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ 512 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ 513 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ 514 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ 515 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */ 516 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */ 517 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */ 518 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */ 519 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */ 520 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */ 521 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */ 522 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */ 523 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */ 524 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */ 525 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */ 526 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */ 527 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ 528 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ 529 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ 530 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ 531 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ 532 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ 533 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ 534 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ 535 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ 536 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ 537 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ 538 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ 539 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */ 540 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */ 541 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */ 542 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */ 543 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */ 544 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ 545 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ 546 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ 547 548 /* SiS */ 549 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 550 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ 551 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 552 553 /* Marvell */ 554 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 555 556 /* Generic, PCI class code for AHCI */ 557 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 558 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 559 560 { } /* terminate list */ 561 }; 562 563 564 static struct pci_driver ahci_pci_driver = { 565 .name = DRV_NAME, 566 .id_table = ahci_pci_tbl, 567 .probe = ahci_init_one, 568 .remove = ata_pci_remove_one, 569 #ifdef CONFIG_PM 570 .suspend = ahci_pci_device_suspend, 571 .resume = ahci_pci_device_resume, 572 #endif 573 }; 574 575 576 static inline int ahci_nr_ports(u32 cap) 577 { 578 return (cap & 0x1f) + 1; 579 } 580 581 static inline void __iomem *__ahci_port_base(struct ata_host *host, 582 unsigned int port_no) 583 { 584 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 585 586 return mmio + 0x100 + (port_no * 0x80); 587 } 588 589 static inline void __iomem *ahci_port_base(struct ata_port *ap) 590 { 591 return __ahci_port_base(ap->host, ap->port_no); 592 } 593 594 /** 595 * ahci_save_initial_config - Save and fixup initial config values 596 * @pdev: target PCI device 597 * @hpriv: host private area to store config values 598 * 599 * Some registers containing configuration info might be setup by 600 * BIOS and might be cleared on reset. This function saves the 601 * initial values of those registers into @hpriv such that they 602 * can be restored after controller reset. 603 * 604 * If inconsistent, config values are fixed up by this function. 605 * 606 * LOCKING: 607 * None. 608 */ 609 static void ahci_save_initial_config(struct pci_dev *pdev, 610 struct ahci_host_priv *hpriv) 611 { 612 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; 613 u32 cap, port_map; 614 int i; 615 616 /* Values prefixed with saved_ are written back to host after 617 * reset. Values without are used for driver operation. 618 */ 619 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 620 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 621 622 /* some chips have errata preventing 64bit use */ 623 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 624 dev_printk(KERN_INFO, &pdev->dev, 625 "controller can't do 64bit DMA, forcing 32bit\n"); 626 cap &= ~HOST_CAP_64; 627 } 628 629 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 630 dev_printk(KERN_INFO, &pdev->dev, 631 "controller can't do NCQ, turning off CAP_NCQ\n"); 632 cap &= ~HOST_CAP_NCQ; 633 } 634 635 if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 636 dev_printk(KERN_INFO, &pdev->dev, 637 "controller can't do PMP, turning off CAP_PMP\n"); 638 cap &= ~HOST_CAP_PMP; 639 } 640 641 /* 642 * Temporary Marvell 6145 hack: PATA port presence 643 * is asserted through the standard AHCI port 644 * presence register, as bit 4 (counting from 0) 645 */ 646 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 647 dev_printk(KERN_ERR, &pdev->dev, 648 "MV_AHCI HACK: port_map %x -> %x\n", 649 hpriv->port_map, 650 hpriv->port_map & 0xf); 651 652 port_map &= 0xf; 653 } 654 655 /* cross check port_map and cap.n_ports */ 656 if (port_map) { 657 u32 tmp_port_map = port_map; 658 int n_ports = ahci_nr_ports(cap); 659 660 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { 661 if (tmp_port_map & (1 << i)) { 662 n_ports--; 663 tmp_port_map &= ~(1 << i); 664 } 665 } 666 667 /* If n_ports and port_map are inconsistent, whine and 668 * clear port_map and let it be generated from n_ports. 669 */ 670 if (n_ports || tmp_port_map) { 671 dev_printk(KERN_WARNING, &pdev->dev, 672 "nr_ports (%u) and implemented port map " 673 "(0x%x) don't match, using nr_ports\n", 674 ahci_nr_ports(cap), port_map); 675 port_map = 0; 676 } 677 } 678 679 /* fabricate port_map from cap.nr_ports */ 680 if (!port_map) { 681 port_map = (1 << ahci_nr_ports(cap)) - 1; 682 dev_printk(KERN_WARNING, &pdev->dev, 683 "forcing PORTS_IMPL to 0x%x\n", port_map); 684 685 /* write the fixed up value to the PI register */ 686 hpriv->saved_port_map = port_map; 687 } 688 689 /* record values to use during operation */ 690 hpriv->cap = cap; 691 hpriv->port_map = port_map; 692 } 693 694 /** 695 * ahci_restore_initial_config - Restore initial config 696 * @host: target ATA host 697 * 698 * Restore initial config stored by ahci_save_initial_config(). 699 * 700 * LOCKING: 701 * None. 702 */ 703 static void ahci_restore_initial_config(struct ata_host *host) 704 { 705 struct ahci_host_priv *hpriv = host->private_data; 706 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 707 708 writel(hpriv->saved_cap, mmio + HOST_CAP); 709 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 710 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 711 } 712 713 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 714 { 715 static const int offset[] = { 716 [SCR_STATUS] = PORT_SCR_STAT, 717 [SCR_CONTROL] = PORT_SCR_CTL, 718 [SCR_ERROR] = PORT_SCR_ERR, 719 [SCR_ACTIVE] = PORT_SCR_ACT, 720 [SCR_NOTIFICATION] = PORT_SCR_NTF, 721 }; 722 struct ahci_host_priv *hpriv = ap->host->private_data; 723 724 if (sc_reg < ARRAY_SIZE(offset) && 725 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 726 return offset[sc_reg]; 727 return 0; 728 } 729 730 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) 731 { 732 void __iomem *port_mmio = ahci_port_base(ap); 733 int offset = ahci_scr_offset(ap, sc_reg); 734 735 if (offset) { 736 *val = readl(port_mmio + offset); 737 return 0; 738 } 739 return -EINVAL; 740 } 741 742 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) 743 { 744 void __iomem *port_mmio = ahci_port_base(ap); 745 int offset = ahci_scr_offset(ap, sc_reg); 746 747 if (offset) { 748 writel(val, port_mmio + offset); 749 return 0; 750 } 751 return -EINVAL; 752 } 753 754 static void ahci_start_engine(struct ata_port *ap) 755 { 756 void __iomem *port_mmio = ahci_port_base(ap); 757 u32 tmp; 758 759 /* start DMA */ 760 tmp = readl(port_mmio + PORT_CMD); 761 tmp |= PORT_CMD_START; 762 writel(tmp, port_mmio + PORT_CMD); 763 readl(port_mmio + PORT_CMD); /* flush */ 764 } 765 766 static int ahci_stop_engine(struct ata_port *ap) 767 { 768 void __iomem *port_mmio = ahci_port_base(ap); 769 u32 tmp; 770 771 tmp = readl(port_mmio + PORT_CMD); 772 773 /* check if the HBA is idle */ 774 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 775 return 0; 776 777 /* setting HBA to idle */ 778 tmp &= ~PORT_CMD_START; 779 writel(tmp, port_mmio + PORT_CMD); 780 781 /* wait for engine to stop. This could be as long as 500 msec */ 782 tmp = ata_wait_register(port_mmio + PORT_CMD, 783 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 784 if (tmp & PORT_CMD_LIST_ON) 785 return -EIO; 786 787 return 0; 788 } 789 790 static void ahci_start_fis_rx(struct ata_port *ap) 791 { 792 void __iomem *port_mmio = ahci_port_base(ap); 793 struct ahci_host_priv *hpriv = ap->host->private_data; 794 struct ahci_port_priv *pp = ap->private_data; 795 u32 tmp; 796 797 /* set FIS registers */ 798 if (hpriv->cap & HOST_CAP_64) 799 writel((pp->cmd_slot_dma >> 16) >> 16, 800 port_mmio + PORT_LST_ADDR_HI); 801 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 802 803 if (hpriv->cap & HOST_CAP_64) 804 writel((pp->rx_fis_dma >> 16) >> 16, 805 port_mmio + PORT_FIS_ADDR_HI); 806 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 807 808 /* enable FIS reception */ 809 tmp = readl(port_mmio + PORT_CMD); 810 tmp |= PORT_CMD_FIS_RX; 811 writel(tmp, port_mmio + PORT_CMD); 812 813 /* flush */ 814 readl(port_mmio + PORT_CMD); 815 } 816 817 static int ahci_stop_fis_rx(struct ata_port *ap) 818 { 819 void __iomem *port_mmio = ahci_port_base(ap); 820 u32 tmp; 821 822 /* disable FIS reception */ 823 tmp = readl(port_mmio + PORT_CMD); 824 tmp &= ~PORT_CMD_FIS_RX; 825 writel(tmp, port_mmio + PORT_CMD); 826 827 /* wait for completion, spec says 500ms, give it 1000 */ 828 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 829 PORT_CMD_FIS_ON, 10, 1000); 830 if (tmp & PORT_CMD_FIS_ON) 831 return -EBUSY; 832 833 return 0; 834 } 835 836 static void ahci_power_up(struct ata_port *ap) 837 { 838 struct ahci_host_priv *hpriv = ap->host->private_data; 839 void __iomem *port_mmio = ahci_port_base(ap); 840 u32 cmd; 841 842 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 843 844 /* spin up device */ 845 if (hpriv->cap & HOST_CAP_SSS) { 846 cmd |= PORT_CMD_SPIN_UP; 847 writel(cmd, port_mmio + PORT_CMD); 848 } 849 850 /* wake up link */ 851 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 852 } 853 854 static void ahci_disable_alpm(struct ata_port *ap) 855 { 856 struct ahci_host_priv *hpriv = ap->host->private_data; 857 void __iomem *port_mmio = ahci_port_base(ap); 858 u32 cmd; 859 struct ahci_port_priv *pp = ap->private_data; 860 861 /* IPM bits should be disabled by libata-core */ 862 /* get the existing command bits */ 863 cmd = readl(port_mmio + PORT_CMD); 864 865 /* disable ALPM and ASP */ 866 cmd &= ~PORT_CMD_ASP; 867 cmd &= ~PORT_CMD_ALPE; 868 869 /* force the interface back to active */ 870 cmd |= PORT_CMD_ICC_ACTIVE; 871 872 /* write out new cmd value */ 873 writel(cmd, port_mmio + PORT_CMD); 874 cmd = readl(port_mmio + PORT_CMD); 875 876 /* wait 10ms to be sure we've come out of any low power state */ 877 msleep(10); 878 879 /* clear out any PhyRdy stuff from interrupt status */ 880 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT); 881 882 /* go ahead and clean out PhyRdy Change from Serror too */ 883 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18))); 884 885 /* 886 * Clear flag to indicate that we should ignore all PhyRdy 887 * state changes 888 */ 889 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG; 890 891 /* 892 * Enable interrupts on Phy Ready. 893 */ 894 pp->intr_mask |= PORT_IRQ_PHYRDY; 895 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 896 897 /* 898 * don't change the link pm policy - we can be called 899 * just to turn of link pm temporarily 900 */ 901 } 902 903 static int ahci_enable_alpm(struct ata_port *ap, 904 enum link_pm policy) 905 { 906 struct ahci_host_priv *hpriv = ap->host->private_data; 907 void __iomem *port_mmio = ahci_port_base(ap); 908 u32 cmd; 909 struct ahci_port_priv *pp = ap->private_data; 910 u32 asp; 911 912 /* Make sure the host is capable of link power management */ 913 if (!(hpriv->cap & HOST_CAP_ALPM)) 914 return -EINVAL; 915 916 switch (policy) { 917 case MAX_PERFORMANCE: 918 case NOT_AVAILABLE: 919 /* 920 * if we came here with NOT_AVAILABLE, 921 * it just means this is the first time we 922 * have tried to enable - default to max performance, 923 * and let the user go to lower power modes on request. 924 */ 925 ahci_disable_alpm(ap); 926 return 0; 927 case MIN_POWER: 928 /* configure HBA to enter SLUMBER */ 929 asp = PORT_CMD_ASP; 930 break; 931 case MEDIUM_POWER: 932 /* configure HBA to enter PARTIAL */ 933 asp = 0; 934 break; 935 default: 936 return -EINVAL; 937 } 938 939 /* 940 * Disable interrupts on Phy Ready. This keeps us from 941 * getting woken up due to spurious phy ready interrupts 942 * TBD - Hot plug should be done via polling now, is 943 * that even supported? 944 */ 945 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 946 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 947 948 /* 949 * Set a flag to indicate that we should ignore all PhyRdy 950 * state changes since these can happen now whenever we 951 * change link state 952 */ 953 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG; 954 955 /* get the existing command bits */ 956 cmd = readl(port_mmio + PORT_CMD); 957 958 /* 959 * Set ASP based on Policy 960 */ 961 cmd |= asp; 962 963 /* 964 * Setting this bit will instruct the HBA to aggressively 965 * enter a lower power link state when it's appropriate and 966 * based on the value set above for ASP 967 */ 968 cmd |= PORT_CMD_ALPE; 969 970 /* write out new cmd value */ 971 writel(cmd, port_mmio + PORT_CMD); 972 cmd = readl(port_mmio + PORT_CMD); 973 974 /* IPM bits should be set by libata-core */ 975 return 0; 976 } 977 978 #ifdef CONFIG_PM 979 static void ahci_power_down(struct ata_port *ap) 980 { 981 struct ahci_host_priv *hpriv = ap->host->private_data; 982 void __iomem *port_mmio = ahci_port_base(ap); 983 u32 cmd, scontrol; 984 985 if (!(hpriv->cap & HOST_CAP_SSS)) 986 return; 987 988 /* put device into listen mode, first set PxSCTL.DET to 0 */ 989 scontrol = readl(port_mmio + PORT_SCR_CTL); 990 scontrol &= ~0xf; 991 writel(scontrol, port_mmio + PORT_SCR_CTL); 992 993 /* then set PxCMD.SUD to 0 */ 994 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 995 cmd &= ~PORT_CMD_SPIN_UP; 996 writel(cmd, port_mmio + PORT_CMD); 997 } 998 #endif 999 1000 static void ahci_start_port(struct ata_port *ap) 1001 { 1002 /* enable FIS reception */ 1003 ahci_start_fis_rx(ap); 1004 1005 /* enable DMA */ 1006 ahci_start_engine(ap); 1007 } 1008 1009 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 1010 { 1011 int rc; 1012 1013 /* disable DMA */ 1014 rc = ahci_stop_engine(ap); 1015 if (rc) { 1016 *emsg = "failed to stop engine"; 1017 return rc; 1018 } 1019 1020 /* disable FIS reception */ 1021 rc = ahci_stop_fis_rx(ap); 1022 if (rc) { 1023 *emsg = "failed stop FIS RX"; 1024 return rc; 1025 } 1026 1027 return 0; 1028 } 1029 1030 static int ahci_reset_controller(struct ata_host *host) 1031 { 1032 struct pci_dev *pdev = to_pci_dev(host->dev); 1033 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 1034 u32 tmp; 1035 1036 /* we must be in AHCI mode, before using anything 1037 * AHCI-specific, such as HOST_RESET. 1038 */ 1039 tmp = readl(mmio + HOST_CTL); 1040 if (!(tmp & HOST_AHCI_EN)) { 1041 tmp |= HOST_AHCI_EN; 1042 writel(tmp, mmio + HOST_CTL); 1043 } 1044 1045 /* global controller reset */ 1046 if ((tmp & HOST_RESET) == 0) { 1047 writel(tmp | HOST_RESET, mmio + HOST_CTL); 1048 readl(mmio + HOST_CTL); /* flush */ 1049 } 1050 1051 /* reset must complete within 1 second, or 1052 * the hardware should be considered fried. 1053 */ 1054 ssleep(1); 1055 1056 tmp = readl(mmio + HOST_CTL); 1057 if (tmp & HOST_RESET) { 1058 dev_printk(KERN_ERR, host->dev, 1059 "controller reset failed (0x%x)\n", tmp); 1060 return -EIO; 1061 } 1062 1063 /* turn on AHCI mode */ 1064 writel(HOST_AHCI_EN, mmio + HOST_CTL); 1065 (void) readl(mmio + HOST_CTL); /* flush */ 1066 1067 /* some registers might be cleared on reset. restore initial values */ 1068 ahci_restore_initial_config(host); 1069 1070 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 1071 u16 tmp16; 1072 1073 /* configure PCS */ 1074 pci_read_config_word(pdev, 0x92, &tmp16); 1075 tmp16 |= 0xf; 1076 pci_write_config_word(pdev, 0x92, tmp16); 1077 } 1078 1079 return 0; 1080 } 1081 1082 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, 1083 int port_no, void __iomem *mmio, 1084 void __iomem *port_mmio) 1085 { 1086 const char *emsg = NULL; 1087 int rc; 1088 u32 tmp; 1089 1090 /* make sure port is not active */ 1091 rc = ahci_deinit_port(ap, &emsg); 1092 if (rc) 1093 dev_printk(KERN_WARNING, &pdev->dev, 1094 "%s (%d)\n", emsg, rc); 1095 1096 /* clear SError */ 1097 tmp = readl(port_mmio + PORT_SCR_ERR); 1098 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1099 writel(tmp, port_mmio + PORT_SCR_ERR); 1100 1101 /* clear port IRQ */ 1102 tmp = readl(port_mmio + PORT_IRQ_STAT); 1103 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1104 if (tmp) 1105 writel(tmp, port_mmio + PORT_IRQ_STAT); 1106 1107 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1108 } 1109 1110 static void ahci_init_controller(struct ata_host *host) 1111 { 1112 struct ahci_host_priv *hpriv = host->private_data; 1113 struct pci_dev *pdev = to_pci_dev(host->dev); 1114 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 1115 int i; 1116 void __iomem *port_mmio; 1117 u32 tmp; 1118 1119 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 1120 port_mmio = __ahci_port_base(host, 4); 1121 1122 writel(0, port_mmio + PORT_IRQ_MASK); 1123 1124 /* clear port IRQ */ 1125 tmp = readl(port_mmio + PORT_IRQ_STAT); 1126 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1127 if (tmp) 1128 writel(tmp, port_mmio + PORT_IRQ_STAT); 1129 } 1130 1131 for (i = 0; i < host->n_ports; i++) { 1132 struct ata_port *ap = host->ports[i]; 1133 1134 port_mmio = ahci_port_base(ap); 1135 if (ata_port_is_dummy(ap)) 1136 continue; 1137 1138 ahci_port_init(pdev, ap, i, mmio, port_mmio); 1139 } 1140 1141 tmp = readl(mmio + HOST_CTL); 1142 VPRINTK("HOST_CTL 0x%x\n", tmp); 1143 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1144 tmp = readl(mmio + HOST_CTL); 1145 VPRINTK("HOST_CTL 0x%x\n", tmp); 1146 } 1147 1148 static unsigned int ahci_dev_classify(struct ata_port *ap) 1149 { 1150 void __iomem *port_mmio = ahci_port_base(ap); 1151 struct ata_taskfile tf; 1152 u32 tmp; 1153 1154 tmp = readl(port_mmio + PORT_SIG); 1155 tf.lbah = (tmp >> 24) & 0xff; 1156 tf.lbam = (tmp >> 16) & 0xff; 1157 tf.lbal = (tmp >> 8) & 0xff; 1158 tf.nsect = (tmp) & 0xff; 1159 1160 return ata_dev_classify(&tf); 1161 } 1162 1163 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1164 u32 opts) 1165 { 1166 dma_addr_t cmd_tbl_dma; 1167 1168 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1169 1170 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1171 pp->cmd_slot[tag].status = 0; 1172 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1173 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1174 } 1175 1176 static int ahci_kick_engine(struct ata_port *ap, int force_restart) 1177 { 1178 void __iomem *port_mmio = ap->ioaddr.cmd_addr; 1179 struct ahci_host_priv *hpriv = ap->host->private_data; 1180 u32 tmp; 1181 int busy, rc; 1182 1183 /* do we need to kick the port? */ 1184 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ); 1185 if (!busy && !force_restart) 1186 return 0; 1187 1188 /* stop engine */ 1189 rc = ahci_stop_engine(ap); 1190 if (rc) 1191 goto out_restart; 1192 1193 /* need to do CLO? */ 1194 if (!busy) { 1195 rc = 0; 1196 goto out_restart; 1197 } 1198 1199 if (!(hpriv->cap & HOST_CAP_CLO)) { 1200 rc = -EOPNOTSUPP; 1201 goto out_restart; 1202 } 1203 1204 /* perform CLO */ 1205 tmp = readl(port_mmio + PORT_CMD); 1206 tmp |= PORT_CMD_CLO; 1207 writel(tmp, port_mmio + PORT_CMD); 1208 1209 rc = 0; 1210 tmp = ata_wait_register(port_mmio + PORT_CMD, 1211 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1212 if (tmp & PORT_CMD_CLO) 1213 rc = -EIO; 1214 1215 /* restart engine */ 1216 out_restart: 1217 ahci_start_engine(ap); 1218 return rc; 1219 } 1220 1221 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1222 struct ata_taskfile *tf, int is_cmd, u16 flags, 1223 unsigned long timeout_msec) 1224 { 1225 const u32 cmd_fis_len = 5; /* five dwords */ 1226 struct ahci_port_priv *pp = ap->private_data; 1227 void __iomem *port_mmio = ahci_port_base(ap); 1228 u8 *fis = pp->cmd_tbl; 1229 u32 tmp; 1230 1231 /* prep the command */ 1232 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1233 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1234 1235 /* issue & wait */ 1236 writel(1, port_mmio + PORT_CMD_ISSUE); 1237 1238 if (timeout_msec) { 1239 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1240 1, timeout_msec); 1241 if (tmp & 0x1) { 1242 ahci_kick_engine(ap, 1); 1243 return -EBUSY; 1244 } 1245 } else 1246 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1247 1248 return 0; 1249 } 1250 1251 static int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1252 int pmp, unsigned long deadline) 1253 { 1254 struct ata_port *ap = link->ap; 1255 const char *reason = NULL; 1256 unsigned long now, msecs; 1257 struct ata_taskfile tf; 1258 int rc; 1259 1260 DPRINTK("ENTER\n"); 1261 1262 if (ata_link_offline(link)) { 1263 DPRINTK("PHY reports no device\n"); 1264 *class = ATA_DEV_NONE; 1265 return 0; 1266 } 1267 1268 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1269 rc = ahci_kick_engine(ap, 1); 1270 if (rc) 1271 ata_link_printk(link, KERN_WARNING, 1272 "failed to reset engine (errno=%d)", rc); 1273 1274 ata_tf_init(link->device, &tf); 1275 1276 /* issue the first D2H Register FIS */ 1277 msecs = 0; 1278 now = jiffies; 1279 if (time_after(now, deadline)) 1280 msecs = jiffies_to_msecs(deadline - now); 1281 1282 tf.ctl |= ATA_SRST; 1283 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1284 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1285 rc = -EIO; 1286 reason = "1st FIS failed"; 1287 goto fail; 1288 } 1289 1290 /* spec says at least 5us, but be generous and sleep for 1ms */ 1291 msleep(1); 1292 1293 /* issue the second D2H Register FIS */ 1294 tf.ctl &= ~ATA_SRST; 1295 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1296 1297 /* wait a while before checking status */ 1298 ata_wait_after_reset(ap, deadline); 1299 1300 rc = ata_wait_ready(ap, deadline); 1301 /* link occupied, -ENODEV too is an error */ 1302 if (rc) { 1303 reason = "device not ready"; 1304 goto fail; 1305 } 1306 *class = ahci_dev_classify(ap); 1307 1308 DPRINTK("EXIT, class=%u\n", *class); 1309 return 0; 1310 1311 fail: 1312 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); 1313 return rc; 1314 } 1315 1316 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1317 unsigned long deadline) 1318 { 1319 int pmp = 0; 1320 1321 if (link->ap->flags & ATA_FLAG_PMP) 1322 pmp = SATA_PMP_CTRL_PORT; 1323 1324 return ahci_do_softreset(link, class, pmp, deadline); 1325 } 1326 1327 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1328 unsigned long deadline) 1329 { 1330 struct ata_port *ap = link->ap; 1331 struct ahci_port_priv *pp = ap->private_data; 1332 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1333 struct ata_taskfile tf; 1334 int rc; 1335 1336 DPRINTK("ENTER\n"); 1337 1338 ahci_stop_engine(ap); 1339 1340 /* clear D2H reception area to properly wait for D2H FIS */ 1341 ata_tf_init(link->device, &tf); 1342 tf.command = 0x80; 1343 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1344 1345 rc = sata_std_hardreset(link, class, deadline); 1346 1347 ahci_start_engine(ap); 1348 1349 if (rc == 0 && ata_link_online(link)) 1350 *class = ahci_dev_classify(ap); 1351 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN) 1352 *class = ATA_DEV_NONE; 1353 1354 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1355 return rc; 1356 } 1357 1358 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 1359 unsigned long deadline) 1360 { 1361 struct ata_port *ap = link->ap; 1362 u32 serror; 1363 int rc; 1364 1365 DPRINTK("ENTER\n"); 1366 1367 ahci_stop_engine(ap); 1368 1369 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 1370 deadline); 1371 1372 /* vt8251 needs SError cleared for the port to operate */ 1373 ahci_scr_read(ap, SCR_ERROR, &serror); 1374 ahci_scr_write(ap, SCR_ERROR, serror); 1375 1376 ahci_start_engine(ap); 1377 1378 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1379 1380 /* vt8251 doesn't clear BSY on signature FIS reception, 1381 * request follow-up softreset. 1382 */ 1383 return rc ?: -EAGAIN; 1384 } 1385 1386 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 1387 unsigned long deadline) 1388 { 1389 struct ata_port *ap = link->ap; 1390 struct ahci_port_priv *pp = ap->private_data; 1391 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1392 struct ata_taskfile tf; 1393 int rc; 1394 1395 ahci_stop_engine(ap); 1396 1397 /* clear D2H reception area to properly wait for D2H FIS */ 1398 ata_tf_init(link->device, &tf); 1399 tf.command = 0x80; 1400 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1401 1402 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 1403 deadline); 1404 1405 ahci_start_engine(ap); 1406 1407 if (rc || ata_link_offline(link)) 1408 return rc; 1409 1410 /* spec mandates ">= 2ms" before checking status */ 1411 msleep(150); 1412 1413 /* The pseudo configuration device on SIMG4726 attached to 1414 * ASUS P5W-DH Deluxe doesn't send signature FIS after 1415 * hardreset if no device is attached to the first downstream 1416 * port && the pseudo device locks up on SRST w/ PMP==0. To 1417 * work around this, wait for !BSY only briefly. If BSY isn't 1418 * cleared, perform CLO and proceed to IDENTIFY (achieved by 1419 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 1420 * 1421 * Wait for two seconds. Devices attached to downstream port 1422 * which can't process the following IDENTIFY after this will 1423 * have to be reset again. For most cases, this should 1424 * suffice while making probing snappish enough. 1425 */ 1426 rc = ata_wait_ready(ap, jiffies + 2 * HZ); 1427 if (rc) 1428 ahci_kick_engine(ap, 0); 1429 1430 return 0; 1431 } 1432 1433 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1434 { 1435 struct ata_port *ap = link->ap; 1436 void __iomem *port_mmio = ahci_port_base(ap); 1437 u32 new_tmp, tmp; 1438 1439 ata_std_postreset(link, class); 1440 1441 /* Make sure port's ATAPI bit is set appropriately */ 1442 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1443 if (*class == ATA_DEV_ATAPI) 1444 new_tmp |= PORT_CMD_ATAPI; 1445 else 1446 new_tmp &= ~PORT_CMD_ATAPI; 1447 if (new_tmp != tmp) { 1448 writel(new_tmp, port_mmio + PORT_CMD); 1449 readl(port_mmio + PORT_CMD); /* flush */ 1450 } 1451 } 1452 1453 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class, 1454 unsigned long deadline) 1455 { 1456 return ahci_do_softreset(link, class, link->pmp, deadline); 1457 } 1458 1459 static u8 ahci_check_status(struct ata_port *ap) 1460 { 1461 void __iomem *mmio = ap->ioaddr.cmd_addr; 1462 1463 return readl(mmio + PORT_TFDATA) & 0xFF; 1464 } 1465 1466 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 1467 { 1468 struct ahci_port_priv *pp = ap->private_data; 1469 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1470 1471 ata_tf_from_fis(d2h_fis, tf); 1472 } 1473 1474 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1475 { 1476 struct scatterlist *sg; 1477 struct ahci_sg *ahci_sg; 1478 unsigned int n_sg = 0; 1479 1480 VPRINTK("ENTER\n"); 1481 1482 /* 1483 * Next, the S/G list. 1484 */ 1485 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1486 ata_for_each_sg(sg, qc) { 1487 dma_addr_t addr = sg_dma_address(sg); 1488 u32 sg_len = sg_dma_len(sg); 1489 1490 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); 1491 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 1492 ahci_sg->flags_size = cpu_to_le32(sg_len - 1); 1493 1494 ahci_sg++; 1495 n_sg++; 1496 } 1497 1498 return n_sg; 1499 } 1500 1501 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1502 { 1503 struct ata_port *ap = qc->ap; 1504 struct ahci_port_priv *pp = ap->private_data; 1505 int is_atapi = is_atapi_taskfile(&qc->tf); 1506 void *cmd_tbl; 1507 u32 opts; 1508 const u32 cmd_fis_len = 5; /* five dwords */ 1509 unsigned int n_elem; 1510 1511 /* 1512 * Fill in command table information. First, the header, 1513 * a SATA Register - Host to Device command FIS. 1514 */ 1515 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1516 1517 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1518 if (is_atapi) { 1519 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1520 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1521 } 1522 1523 n_elem = 0; 1524 if (qc->flags & ATA_QCFLAG_DMAMAP) 1525 n_elem = ahci_fill_sg(qc, cmd_tbl); 1526 1527 /* 1528 * Fill in command slot information. 1529 */ 1530 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1531 if (qc->tf.flags & ATA_TFLAG_WRITE) 1532 opts |= AHCI_CMD_WRITE; 1533 if (is_atapi) 1534 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1535 1536 ahci_fill_cmd_slot(pp, qc->tag, opts); 1537 } 1538 1539 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1540 { 1541 struct ahci_host_priv *hpriv = ap->host->private_data; 1542 struct ahci_port_priv *pp = ap->private_data; 1543 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1544 struct ata_link *link = NULL; 1545 struct ata_queued_cmd *active_qc; 1546 struct ata_eh_info *active_ehi; 1547 u32 serror; 1548 1549 /* determine active link */ 1550 ata_port_for_each_link(link, ap) 1551 if (ata_link_active(link)) 1552 break; 1553 if (!link) 1554 link = &ap->link; 1555 1556 active_qc = ata_qc_from_tag(ap, link->active_tag); 1557 active_ehi = &link->eh_info; 1558 1559 /* record irq stat */ 1560 ata_ehi_clear_desc(host_ehi); 1561 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1562 1563 /* AHCI needs SError cleared; otherwise, it might lock up */ 1564 ahci_scr_read(ap, SCR_ERROR, &serror); 1565 ahci_scr_write(ap, SCR_ERROR, serror); 1566 host_ehi->serror |= serror; 1567 1568 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1569 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1570 irq_stat &= ~PORT_IRQ_IF_ERR; 1571 1572 if (irq_stat & PORT_IRQ_TF_ERR) { 1573 /* If qc is active, charge it; otherwise, the active 1574 * link. There's no active qc on NCQ errors. It will 1575 * be determined by EH by reading log page 10h. 1576 */ 1577 if (active_qc) 1578 active_qc->err_mask |= AC_ERR_DEV; 1579 else 1580 active_ehi->err_mask |= AC_ERR_DEV; 1581 1582 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1583 host_ehi->serror &= ~SERR_INTERNAL; 1584 } 1585 1586 if (irq_stat & PORT_IRQ_UNK_FIS) { 1587 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); 1588 1589 active_ehi->err_mask |= AC_ERR_HSM; 1590 active_ehi->action |= ATA_EH_SOFTRESET; 1591 ata_ehi_push_desc(active_ehi, 1592 "unknown FIS %08x %08x %08x %08x" , 1593 unk[0], unk[1], unk[2], unk[3]); 1594 } 1595 1596 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) { 1597 active_ehi->err_mask |= AC_ERR_HSM; 1598 active_ehi->action |= ATA_EH_SOFTRESET; 1599 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1600 } 1601 1602 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1603 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1604 host_ehi->action |= ATA_EH_SOFTRESET; 1605 ata_ehi_push_desc(host_ehi, "host bus error"); 1606 } 1607 1608 if (irq_stat & PORT_IRQ_IF_ERR) { 1609 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1610 host_ehi->action |= ATA_EH_SOFTRESET; 1611 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1612 } 1613 1614 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1615 ata_ehi_hotplugged(host_ehi); 1616 ata_ehi_push_desc(host_ehi, "%s", 1617 irq_stat & PORT_IRQ_CONNECT ? 1618 "connection status changed" : "PHY RDY changed"); 1619 } 1620 1621 /* okay, let's hand over to EH */ 1622 1623 if (irq_stat & PORT_IRQ_FREEZE) 1624 ata_port_freeze(ap); 1625 else 1626 ata_port_abort(ap); 1627 } 1628 1629 static void ahci_port_intr(struct ata_port *ap) 1630 { 1631 void __iomem *port_mmio = ap->ioaddr.cmd_addr; 1632 struct ata_eh_info *ehi = &ap->link.eh_info; 1633 struct ahci_port_priv *pp = ap->private_data; 1634 struct ahci_host_priv *hpriv = ap->host->private_data; 1635 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1636 u32 status, qc_active; 1637 int rc, known_irq = 0; 1638 1639 status = readl(port_mmio + PORT_IRQ_STAT); 1640 writel(status, port_mmio + PORT_IRQ_STAT); 1641 1642 /* ignore BAD_PMP while resetting */ 1643 if (unlikely(resetting)) 1644 status &= ~PORT_IRQ_BAD_PMP; 1645 1646 /* If we are getting PhyRdy, this is 1647 * just a power state change, we should 1648 * clear out this, plus the PhyRdy/Comm 1649 * Wake bits from Serror 1650 */ 1651 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) && 1652 (status & PORT_IRQ_PHYRDY)) { 1653 status &= ~PORT_IRQ_PHYRDY; 1654 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18))); 1655 } 1656 1657 if (unlikely(status & PORT_IRQ_ERROR)) { 1658 ahci_error_intr(ap, status); 1659 return; 1660 } 1661 1662 if (status & PORT_IRQ_SDB_FIS) { 1663 /* If SNotification is available, leave notification 1664 * handling to sata_async_notification(). If not, 1665 * emulate it by snooping SDB FIS RX area. 1666 * 1667 * Snooping FIS RX area is probably cheaper than 1668 * poking SNotification but some constrollers which 1669 * implement SNotification, ICH9 for example, don't 1670 * store AN SDB FIS into receive area. 1671 */ 1672 if (hpriv->cap & HOST_CAP_SNTF) 1673 sata_async_notification(ap); 1674 else { 1675 /* If the 'N' bit in word 0 of the FIS is set, 1676 * we just received asynchronous notification. 1677 * Tell libata about it. 1678 */ 1679 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1680 u32 f0 = le32_to_cpu(f[0]); 1681 1682 if (f0 & (1 << 15)) 1683 sata_async_notification(ap); 1684 } 1685 } 1686 1687 /* pp->active_link is valid iff any command is in flight */ 1688 if (ap->qc_active && pp->active_link->sactive) 1689 qc_active = readl(port_mmio + PORT_SCR_ACT); 1690 else 1691 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1692 1693 rc = ata_qc_complete_multiple(ap, qc_active, NULL); 1694 1695 /* If resetting, spurious or invalid completions are expected, 1696 * return unconditionally. 1697 */ 1698 if (resetting) 1699 return; 1700 1701 if (rc > 0) 1702 return; 1703 if (rc < 0) { 1704 ehi->err_mask |= AC_ERR_HSM; 1705 ehi->action |= ATA_EH_SOFTRESET; 1706 ata_port_freeze(ap); 1707 return; 1708 } 1709 1710 /* hmmm... a spurious interrupt */ 1711 1712 /* if !NCQ, ignore. No modern ATA device has broken HSM 1713 * implementation for non-NCQ commands. 1714 */ 1715 if (!ap->link.sactive) 1716 return; 1717 1718 if (status & PORT_IRQ_D2H_REG_FIS) { 1719 if (!pp->ncq_saw_d2h) 1720 ata_port_printk(ap, KERN_INFO, 1721 "D2H reg with I during NCQ, " 1722 "this message won't be printed again\n"); 1723 pp->ncq_saw_d2h = 1; 1724 known_irq = 1; 1725 } 1726 1727 if (status & PORT_IRQ_DMAS_FIS) { 1728 if (!pp->ncq_saw_dmas) 1729 ata_port_printk(ap, KERN_INFO, 1730 "DMAS FIS during NCQ, " 1731 "this message won't be printed again\n"); 1732 pp->ncq_saw_dmas = 1; 1733 known_irq = 1; 1734 } 1735 1736 if (status & PORT_IRQ_SDB_FIS) { 1737 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1738 1739 if (le32_to_cpu(f[1])) { 1740 /* SDB FIS containing spurious completions 1741 * might be dangerous, whine and fail commands 1742 * with HSM violation. EH will turn off NCQ 1743 * after several such failures. 1744 */ 1745 ata_ehi_push_desc(ehi, 1746 "spurious completions during NCQ " 1747 "issue=0x%x SAct=0x%x FIS=%08x:%08x", 1748 readl(port_mmio + PORT_CMD_ISSUE), 1749 readl(port_mmio + PORT_SCR_ACT), 1750 le32_to_cpu(f[0]), le32_to_cpu(f[1])); 1751 ehi->err_mask |= AC_ERR_HSM; 1752 ehi->action |= ATA_EH_SOFTRESET; 1753 ata_port_freeze(ap); 1754 } else { 1755 if (!pp->ncq_saw_sdb) 1756 ata_port_printk(ap, KERN_INFO, 1757 "spurious SDB FIS %08x:%08x during NCQ, " 1758 "this message won't be printed again\n", 1759 le32_to_cpu(f[0]), le32_to_cpu(f[1])); 1760 pp->ncq_saw_sdb = 1; 1761 } 1762 known_irq = 1; 1763 } 1764 1765 if (!known_irq) 1766 ata_port_printk(ap, KERN_INFO, "spurious interrupt " 1767 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n", 1768 status, ap->link.active_tag, ap->link.sactive); 1769 } 1770 1771 static void ahci_irq_clear(struct ata_port *ap) 1772 { 1773 /* TODO */ 1774 } 1775 1776 static irqreturn_t ahci_interrupt(int irq, void *dev_instance) 1777 { 1778 struct ata_host *host = dev_instance; 1779 struct ahci_host_priv *hpriv; 1780 unsigned int i, handled = 0; 1781 void __iomem *mmio; 1782 u32 irq_stat, irq_ack = 0; 1783 1784 VPRINTK("ENTER\n"); 1785 1786 hpriv = host->private_data; 1787 mmio = host->iomap[AHCI_PCI_BAR]; 1788 1789 /* sigh. 0xffffffff is a valid return from h/w */ 1790 irq_stat = readl(mmio + HOST_IRQ_STAT); 1791 irq_stat &= hpriv->port_map; 1792 if (!irq_stat) 1793 return IRQ_NONE; 1794 1795 spin_lock(&host->lock); 1796 1797 for (i = 0; i < host->n_ports; i++) { 1798 struct ata_port *ap; 1799 1800 if (!(irq_stat & (1 << i))) 1801 continue; 1802 1803 ap = host->ports[i]; 1804 if (ap) { 1805 ahci_port_intr(ap); 1806 VPRINTK("port %u\n", i); 1807 } else { 1808 VPRINTK("port %u (no irq)\n", i); 1809 if (ata_ratelimit()) 1810 dev_printk(KERN_WARNING, host->dev, 1811 "interrupt on disabled port %u\n", i); 1812 } 1813 1814 irq_ack |= (1 << i); 1815 } 1816 1817 if (irq_ack) { 1818 writel(irq_ack, mmio + HOST_IRQ_STAT); 1819 handled = 1; 1820 } 1821 1822 spin_unlock(&host->lock); 1823 1824 VPRINTK("EXIT\n"); 1825 1826 return IRQ_RETVAL(handled); 1827 } 1828 1829 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1830 { 1831 struct ata_port *ap = qc->ap; 1832 void __iomem *port_mmio = ahci_port_base(ap); 1833 struct ahci_port_priv *pp = ap->private_data; 1834 1835 /* Keep track of the currently active link. It will be used 1836 * in completion path to determine whether NCQ phase is in 1837 * progress. 1838 */ 1839 pp->active_link = qc->dev->link; 1840 1841 if (qc->tf.protocol == ATA_PROT_NCQ) 1842 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 1843 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 1844 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1845 1846 return 0; 1847 } 1848 1849 static void ahci_freeze(struct ata_port *ap) 1850 { 1851 void __iomem *port_mmio = ahci_port_base(ap); 1852 1853 /* turn IRQ off */ 1854 writel(0, port_mmio + PORT_IRQ_MASK); 1855 } 1856 1857 static void ahci_thaw(struct ata_port *ap) 1858 { 1859 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1860 void __iomem *port_mmio = ahci_port_base(ap); 1861 u32 tmp; 1862 struct ahci_port_priv *pp = ap->private_data; 1863 1864 /* clear IRQ */ 1865 tmp = readl(port_mmio + PORT_IRQ_STAT); 1866 writel(tmp, port_mmio + PORT_IRQ_STAT); 1867 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 1868 1869 /* turn IRQ back on */ 1870 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1871 } 1872 1873 static void ahci_error_handler(struct ata_port *ap) 1874 { 1875 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 1876 /* restart engine */ 1877 ahci_stop_engine(ap); 1878 ahci_start_engine(ap); 1879 } 1880 1881 /* perform recovery */ 1882 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset, 1883 ahci_hardreset, ahci_postreset, 1884 sata_pmp_std_prereset, ahci_pmp_softreset, 1885 sata_pmp_std_hardreset, sata_pmp_std_postreset); 1886 } 1887 1888 static void ahci_vt8251_error_handler(struct ata_port *ap) 1889 { 1890 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 1891 /* restart engine */ 1892 ahci_stop_engine(ap); 1893 ahci_start_engine(ap); 1894 } 1895 1896 /* perform recovery */ 1897 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset, 1898 ahci_postreset); 1899 } 1900 1901 static void ahci_p5wdh_error_handler(struct ata_port *ap) 1902 { 1903 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 1904 /* restart engine */ 1905 ahci_stop_engine(ap); 1906 ahci_start_engine(ap); 1907 } 1908 1909 /* perform recovery */ 1910 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset, 1911 ahci_postreset); 1912 } 1913 1914 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 1915 { 1916 struct ata_port *ap = qc->ap; 1917 1918 /* make DMA engine forget about the failed command */ 1919 if (qc->flags & ATA_QCFLAG_FAILED) 1920 ahci_kick_engine(ap, 1); 1921 } 1922 1923 static void ahci_pmp_attach(struct ata_port *ap) 1924 { 1925 void __iomem *port_mmio = ahci_port_base(ap); 1926 struct ahci_port_priv *pp = ap->private_data; 1927 u32 cmd; 1928 1929 cmd = readl(port_mmio + PORT_CMD); 1930 cmd |= PORT_CMD_PMP; 1931 writel(cmd, port_mmio + PORT_CMD); 1932 1933 pp->intr_mask |= PORT_IRQ_BAD_PMP; 1934 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1935 } 1936 1937 static void ahci_pmp_detach(struct ata_port *ap) 1938 { 1939 void __iomem *port_mmio = ahci_port_base(ap); 1940 struct ahci_port_priv *pp = ap->private_data; 1941 u32 cmd; 1942 1943 cmd = readl(port_mmio + PORT_CMD); 1944 cmd &= ~PORT_CMD_PMP; 1945 writel(cmd, port_mmio + PORT_CMD); 1946 1947 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 1948 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1949 } 1950 1951 static int ahci_port_resume(struct ata_port *ap) 1952 { 1953 ahci_power_up(ap); 1954 ahci_start_port(ap); 1955 1956 if (ap->nr_pmp_links) 1957 ahci_pmp_attach(ap); 1958 else 1959 ahci_pmp_detach(ap); 1960 1961 return 0; 1962 } 1963 1964 #ifdef CONFIG_PM 1965 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 1966 { 1967 const char *emsg = NULL; 1968 int rc; 1969 1970 rc = ahci_deinit_port(ap, &emsg); 1971 if (rc == 0) 1972 ahci_power_down(ap); 1973 else { 1974 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); 1975 ahci_start_port(ap); 1976 } 1977 1978 return rc; 1979 } 1980 1981 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 1982 { 1983 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1984 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 1985 u32 ctl; 1986 1987 if (mesg.event == PM_EVENT_SUSPEND) { 1988 /* AHCI spec rev1.1 section 8.3.3: 1989 * Software must disable interrupts prior to requesting a 1990 * transition of the HBA to D3 state. 1991 */ 1992 ctl = readl(mmio + HOST_CTL); 1993 ctl &= ~HOST_IRQ_EN; 1994 writel(ctl, mmio + HOST_CTL); 1995 readl(mmio + HOST_CTL); /* flush */ 1996 } 1997 1998 return ata_pci_device_suspend(pdev, mesg); 1999 } 2000 2001 static int ahci_pci_device_resume(struct pci_dev *pdev) 2002 { 2003 struct ata_host *host = dev_get_drvdata(&pdev->dev); 2004 int rc; 2005 2006 rc = ata_pci_device_do_resume(pdev); 2007 if (rc) 2008 return rc; 2009 2010 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 2011 rc = ahci_reset_controller(host); 2012 if (rc) 2013 return rc; 2014 2015 ahci_init_controller(host); 2016 } 2017 2018 ata_host_resume(host); 2019 2020 return 0; 2021 } 2022 #endif 2023 2024 static int ahci_port_start(struct ata_port *ap) 2025 { 2026 struct device *dev = ap->host->dev; 2027 struct ahci_port_priv *pp; 2028 void *mem; 2029 dma_addr_t mem_dma; 2030 int rc; 2031 2032 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2033 if (!pp) 2034 return -ENOMEM; 2035 2036 rc = ata_pad_alloc(ap, dev); 2037 if (rc) 2038 return rc; 2039 2040 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, 2041 GFP_KERNEL); 2042 if (!mem) 2043 return -ENOMEM; 2044 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); 2045 2046 /* 2047 * First item in chunk of DMA memory: 32-slot command table, 2048 * 32 bytes each in size 2049 */ 2050 pp->cmd_slot = mem; 2051 pp->cmd_slot_dma = mem_dma; 2052 2053 mem += AHCI_CMD_SLOT_SZ; 2054 mem_dma += AHCI_CMD_SLOT_SZ; 2055 2056 /* 2057 * Second item: Received-FIS area 2058 */ 2059 pp->rx_fis = mem; 2060 pp->rx_fis_dma = mem_dma; 2061 2062 mem += AHCI_RX_FIS_SZ; 2063 mem_dma += AHCI_RX_FIS_SZ; 2064 2065 /* 2066 * Third item: data area for storing a single command 2067 * and its scatter-gather table 2068 */ 2069 pp->cmd_tbl = mem; 2070 pp->cmd_tbl_dma = mem_dma; 2071 2072 /* 2073 * Save off initial list of interrupts to be enabled. 2074 * This could be changed later 2075 */ 2076 pp->intr_mask = DEF_PORT_IRQ; 2077 2078 ap->private_data = pp; 2079 2080 /* engage engines, captain */ 2081 return ahci_port_resume(ap); 2082 } 2083 2084 static void ahci_port_stop(struct ata_port *ap) 2085 { 2086 const char *emsg = NULL; 2087 int rc; 2088 2089 /* de-initialize port */ 2090 rc = ahci_deinit_port(ap, &emsg); 2091 if (rc) 2092 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); 2093 } 2094 2095 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 2096 { 2097 int rc; 2098 2099 if (using_dac && 2100 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 2101 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 2102 if (rc) { 2103 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 2104 if (rc) { 2105 dev_printk(KERN_ERR, &pdev->dev, 2106 "64-bit DMA enable failed\n"); 2107 return rc; 2108 } 2109 } 2110 } else { 2111 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 2112 if (rc) { 2113 dev_printk(KERN_ERR, &pdev->dev, 2114 "32-bit DMA enable failed\n"); 2115 return rc; 2116 } 2117 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 2118 if (rc) { 2119 dev_printk(KERN_ERR, &pdev->dev, 2120 "32-bit consistent DMA enable failed\n"); 2121 return rc; 2122 } 2123 } 2124 return 0; 2125 } 2126 2127 static void ahci_print_info(struct ata_host *host) 2128 { 2129 struct ahci_host_priv *hpriv = host->private_data; 2130 struct pci_dev *pdev = to_pci_dev(host->dev); 2131 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 2132 u32 vers, cap, impl, speed; 2133 const char *speed_s; 2134 u16 cc; 2135 const char *scc_s; 2136 2137 vers = readl(mmio + HOST_VERSION); 2138 cap = hpriv->cap; 2139 impl = hpriv->port_map; 2140 2141 speed = (cap >> 20) & 0xf; 2142 if (speed == 1) 2143 speed_s = "1.5"; 2144 else if (speed == 2) 2145 speed_s = "3"; 2146 else 2147 speed_s = "?"; 2148 2149 pci_read_config_word(pdev, 0x0a, &cc); 2150 if (cc == PCI_CLASS_STORAGE_IDE) 2151 scc_s = "IDE"; 2152 else if (cc == PCI_CLASS_STORAGE_SATA) 2153 scc_s = "SATA"; 2154 else if (cc == PCI_CLASS_STORAGE_RAID) 2155 scc_s = "RAID"; 2156 else 2157 scc_s = "unknown"; 2158 2159 dev_printk(KERN_INFO, &pdev->dev, 2160 "AHCI %02x%02x.%02x%02x " 2161 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2162 , 2163 2164 (vers >> 24) & 0xff, 2165 (vers >> 16) & 0xff, 2166 (vers >> 8) & 0xff, 2167 vers & 0xff, 2168 2169 ((cap >> 8) & 0x1f) + 1, 2170 (cap & 0x1f) + 1, 2171 speed_s, 2172 impl, 2173 scc_s); 2174 2175 dev_printk(KERN_INFO, &pdev->dev, 2176 "flags: " 2177 "%s%s%s%s%s%s%s" 2178 "%s%s%s%s%s%s%s\n" 2179 , 2180 2181 cap & (1 << 31) ? "64bit " : "", 2182 cap & (1 << 30) ? "ncq " : "", 2183 cap & (1 << 29) ? "sntf " : "", 2184 cap & (1 << 28) ? "ilck " : "", 2185 cap & (1 << 27) ? "stag " : "", 2186 cap & (1 << 26) ? "pm " : "", 2187 cap & (1 << 25) ? "led " : "", 2188 2189 cap & (1 << 24) ? "clo " : "", 2190 cap & (1 << 19) ? "nz " : "", 2191 cap & (1 << 18) ? "only " : "", 2192 cap & (1 << 17) ? "pmp " : "", 2193 cap & (1 << 15) ? "pio " : "", 2194 cap & (1 << 14) ? "slum " : "", 2195 cap & (1 << 13) ? "part " : "" 2196 ); 2197 } 2198 2199 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 2200 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 2201 * support PMP and the 4726 either directly exports the device 2202 * attached to the first downstream port or acts as a hardware storage 2203 * controller and emulate a single ATA device (can be RAID 0/1 or some 2204 * other configuration). 2205 * 2206 * When there's no device attached to the first downstream port of the 2207 * 4726, "Config Disk" appears, which is a pseudo ATA device to 2208 * configure the 4726. However, ATA emulation of the device is very 2209 * lame. It doesn't send signature D2H Reg FIS after the initial 2210 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 2211 * 2212 * The following function works around the problem by always using 2213 * hardreset on the port and not depending on receiving signature FIS 2214 * afterward. If signature FIS isn't received soon, ATA class is 2215 * assumed without follow-up softreset. 2216 */ 2217 static void ahci_p5wdh_workaround(struct ata_host *host) 2218 { 2219 static struct dmi_system_id sysids[] = { 2220 { 2221 .ident = "P5W DH Deluxe", 2222 .matches = { 2223 DMI_MATCH(DMI_SYS_VENDOR, 2224 "ASUSTEK COMPUTER INC"), 2225 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 2226 }, 2227 }, 2228 { } 2229 }; 2230 struct pci_dev *pdev = to_pci_dev(host->dev); 2231 2232 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 2233 dmi_check_system(sysids)) { 2234 struct ata_port *ap = host->ports[1]; 2235 2236 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH " 2237 "Deluxe on-board SIMG4726 workaround\n"); 2238 2239 ap->ops = &ahci_p5wdh_ops; 2240 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 2241 } 2242 } 2243 2244 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 2245 { 2246 static int printed_version; 2247 struct ata_port_info pi = ahci_port_info[ent->driver_data]; 2248 const struct ata_port_info *ppi[] = { &pi, NULL }; 2249 struct device *dev = &pdev->dev; 2250 struct ahci_host_priv *hpriv; 2251 struct ata_host *host; 2252 int i, rc; 2253 2254 VPRINTK("ENTER\n"); 2255 2256 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); 2257 2258 if (!printed_version++) 2259 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 2260 2261 /* acquire resources */ 2262 rc = pcim_enable_device(pdev); 2263 if (rc) 2264 return rc; 2265 2266 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); 2267 if (rc == -EBUSY) 2268 pcim_pin_device(pdev); 2269 if (rc) 2270 return rc; 2271 2272 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 2273 if (!hpriv) 2274 return -ENOMEM; 2275 hpriv->flags |= (unsigned long)pi.private_data; 2276 2277 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev)) 2278 pci_intx(pdev, 1); 2279 2280 /* save initial config */ 2281 ahci_save_initial_config(pdev, hpriv); 2282 2283 /* prepare host */ 2284 if (hpriv->cap & HOST_CAP_NCQ) 2285 pi.flags |= ATA_FLAG_NCQ; 2286 2287 if (hpriv->cap & HOST_CAP_PMP) 2288 pi.flags |= ATA_FLAG_PMP; 2289 2290 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map)); 2291 if (!host) 2292 return -ENOMEM; 2293 host->iomap = pcim_iomap_table(pdev); 2294 host->private_data = hpriv; 2295 2296 for (i = 0; i < host->n_ports; i++) { 2297 struct ata_port *ap = host->ports[i]; 2298 void __iomem *port_mmio = ahci_port_base(ap); 2299 2300 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); 2301 ata_port_pbar_desc(ap, AHCI_PCI_BAR, 2302 0x100 + ap->port_no * 0x80, "port"); 2303 2304 /* set initial link pm policy */ 2305 ap->pm_policy = NOT_AVAILABLE; 2306 2307 /* standard SATA port setup */ 2308 if (hpriv->port_map & (1 << i)) 2309 ap->ioaddr.cmd_addr = port_mmio; 2310 2311 /* disabled/not-implemented port */ 2312 else 2313 ap->ops = &ata_dummy_port_ops; 2314 } 2315 2316 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 2317 ahci_p5wdh_workaround(host); 2318 2319 /* initialize adapter */ 2320 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 2321 if (rc) 2322 return rc; 2323 2324 rc = ahci_reset_controller(host); 2325 if (rc) 2326 return rc; 2327 2328 ahci_init_controller(host); 2329 ahci_print_info(host); 2330 2331 pci_set_master(pdev); 2332 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, 2333 &ahci_sht); 2334 } 2335 2336 static int __init ahci_init(void) 2337 { 2338 return pci_register_driver(&ahci_pci_driver); 2339 } 2340 2341 static void __exit ahci_exit(void) 2342 { 2343 pci_unregister_driver(&ahci_pci_driver); 2344 } 2345 2346 2347 MODULE_AUTHOR("Jeff Garzik"); 2348 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 2349 MODULE_LICENSE("GPL"); 2350 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 2351 MODULE_VERSION(DRV_VERSION); 2352 2353 module_init(ahci_init); 2354 module_exit(ahci_exit); 2355