1 /* 2 * ahci.c - AHCI SATA support 3 * 4 * Maintained by: Tejun Heo <tj@kernel.org> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/driver-api/libata.rst 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/blkdev.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/device.h> 43 #include <linux/dmi.h> 44 #include <linux/gfp.h> 45 #include <linux/msi.h> 46 #include <scsi/scsi_host.h> 47 #include <scsi/scsi_cmnd.h> 48 #include <linux/libata.h> 49 #include <linux/ahci-remap.h> 50 #include <linux/io-64-nonatomic-lo-hi.h> 51 #include "ahci.h" 52 53 #define DRV_NAME "ahci" 54 #define DRV_VERSION "3.0" 55 56 enum { 57 AHCI_PCI_BAR_STA2X11 = 0, 58 AHCI_PCI_BAR_CAVIUM = 0, 59 AHCI_PCI_BAR_ENMOTUS = 2, 60 AHCI_PCI_BAR_CAVIUM_GEN5 = 4, 61 AHCI_PCI_BAR_STANDARD = 5, 62 }; 63 64 enum board_ids { 65 /* board IDs by feature in alphabetical order */ 66 board_ahci, 67 board_ahci_ign_iferr, 68 board_ahci_mobile, 69 board_ahci_nomsi, 70 board_ahci_noncq, 71 board_ahci_nosntf, 72 board_ahci_yes_fbs, 73 74 /* board IDs for specific chipsets in alphabetical order */ 75 board_ahci_avn, 76 board_ahci_mcp65, 77 board_ahci_mcp77, 78 board_ahci_mcp89, 79 board_ahci_mv, 80 board_ahci_sb600, 81 board_ahci_sb700, /* for SB700 and SB800 */ 82 board_ahci_vt8251, 83 84 /* aliases */ 85 board_ahci_mcp_linux = board_ahci_mcp65, 86 board_ahci_mcp67 = board_ahci_mcp65, 87 board_ahci_mcp73 = board_ahci_mcp65, 88 board_ahci_mcp79 = board_ahci_mcp77, 89 }; 90 91 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 92 static void ahci_remove_one(struct pci_dev *dev); 93 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 94 unsigned long deadline); 95 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 96 unsigned long deadline); 97 static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 98 static bool is_mcp89_apple(struct pci_dev *pdev); 99 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 100 unsigned long deadline); 101 #ifdef CONFIG_PM 102 static int ahci_pci_device_runtime_suspend(struct device *dev); 103 static int ahci_pci_device_runtime_resume(struct device *dev); 104 #ifdef CONFIG_PM_SLEEP 105 static int ahci_pci_device_suspend(struct device *dev); 106 static int ahci_pci_device_resume(struct device *dev); 107 #endif 108 #endif /* CONFIG_PM */ 109 110 static struct scsi_host_template ahci_sht = { 111 AHCI_SHT("ahci"), 112 }; 113 114 static struct ata_port_operations ahci_vt8251_ops = { 115 .inherits = &ahci_ops, 116 .hardreset = ahci_vt8251_hardreset, 117 }; 118 119 static struct ata_port_operations ahci_p5wdh_ops = { 120 .inherits = &ahci_ops, 121 .hardreset = ahci_p5wdh_hardreset, 122 }; 123 124 static struct ata_port_operations ahci_avn_ops = { 125 .inherits = &ahci_ops, 126 .hardreset = ahci_avn_hardreset, 127 }; 128 129 static const struct ata_port_info ahci_port_info[] = { 130 /* by features */ 131 [board_ahci] = { 132 .flags = AHCI_FLAG_COMMON, 133 .pio_mask = ATA_PIO4, 134 .udma_mask = ATA_UDMA6, 135 .port_ops = &ahci_ops, 136 }, 137 [board_ahci_ign_iferr] = { 138 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 139 .flags = AHCI_FLAG_COMMON, 140 .pio_mask = ATA_PIO4, 141 .udma_mask = ATA_UDMA6, 142 .port_ops = &ahci_ops, 143 }, 144 [board_ahci_mobile] = { 145 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE), 146 .flags = AHCI_FLAG_COMMON, 147 .pio_mask = ATA_PIO4, 148 .udma_mask = ATA_UDMA6, 149 .port_ops = &ahci_ops, 150 }, 151 [board_ahci_nomsi] = { 152 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 153 .flags = AHCI_FLAG_COMMON, 154 .pio_mask = ATA_PIO4, 155 .udma_mask = ATA_UDMA6, 156 .port_ops = &ahci_ops, 157 }, 158 [board_ahci_noncq] = { 159 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 160 .flags = AHCI_FLAG_COMMON, 161 .pio_mask = ATA_PIO4, 162 .udma_mask = ATA_UDMA6, 163 .port_ops = &ahci_ops, 164 }, 165 [board_ahci_nosntf] = { 166 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 167 .flags = AHCI_FLAG_COMMON, 168 .pio_mask = ATA_PIO4, 169 .udma_mask = ATA_UDMA6, 170 .port_ops = &ahci_ops, 171 }, 172 [board_ahci_yes_fbs] = { 173 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 174 .flags = AHCI_FLAG_COMMON, 175 .pio_mask = ATA_PIO4, 176 .udma_mask = ATA_UDMA6, 177 .port_ops = &ahci_ops, 178 }, 179 /* by chipsets */ 180 [board_ahci_avn] = { 181 .flags = AHCI_FLAG_COMMON, 182 .pio_mask = ATA_PIO4, 183 .udma_mask = ATA_UDMA6, 184 .port_ops = &ahci_avn_ops, 185 }, 186 [board_ahci_mcp65] = { 187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 188 AHCI_HFLAG_YES_NCQ), 189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 190 .pio_mask = ATA_PIO4, 191 .udma_mask = ATA_UDMA6, 192 .port_ops = &ahci_ops, 193 }, 194 [board_ahci_mcp77] = { 195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 196 .flags = AHCI_FLAG_COMMON, 197 .pio_mask = ATA_PIO4, 198 .udma_mask = ATA_UDMA6, 199 .port_ops = &ahci_ops, 200 }, 201 [board_ahci_mcp89] = { 202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 203 .flags = AHCI_FLAG_COMMON, 204 .pio_mask = ATA_PIO4, 205 .udma_mask = ATA_UDMA6, 206 .port_ops = &ahci_ops, 207 }, 208 [board_ahci_mv] = { 209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 212 .pio_mask = ATA_PIO4, 213 .udma_mask = ATA_UDMA6, 214 .port_ops = &ahci_ops, 215 }, 216 [board_ahci_sb600] = { 217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 219 AHCI_HFLAG_32BIT_ONLY), 220 .flags = AHCI_FLAG_COMMON, 221 .pio_mask = ATA_PIO4, 222 .udma_mask = ATA_UDMA6, 223 .port_ops = &ahci_pmp_retry_srst_ops, 224 }, 225 [board_ahci_sb700] = { /* for SB700 and SB800 */ 226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 227 .flags = AHCI_FLAG_COMMON, 228 .pio_mask = ATA_PIO4, 229 .udma_mask = ATA_UDMA6, 230 .port_ops = &ahci_pmp_retry_srst_ops, 231 }, 232 [board_ahci_vt8251] = { 233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 234 .flags = AHCI_FLAG_COMMON, 235 .pio_mask = ATA_PIO4, 236 .udma_mask = ATA_UDMA6, 237 .port_ops = &ahci_vt8251_ops, 238 }, 239 }; 240 241 static const struct pci_device_id ahci_pci_tbl[] = { 242 /* Intel */ 243 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 244 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 245 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 246 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 247 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 248 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 249 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 250 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 251 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 252 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 253 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 254 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ 255 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 256 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 257 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 258 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 259 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 260 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 261 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 262 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 263 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */ 264 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */ 265 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */ 266 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */ 267 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */ 268 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 269 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */ 270 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 271 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 272 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 273 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 274 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 275 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 276 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 277 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 278 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 279 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */ 280 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 281 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */ 282 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 283 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */ 284 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */ 285 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */ 286 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */ 287 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */ 288 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */ 289 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */ 290 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */ 291 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */ 292 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */ 293 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */ 294 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */ 295 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */ 296 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */ 297 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */ 298 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */ 299 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */ 300 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */ 301 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */ 302 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */ 303 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 304 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */ 305 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 306 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */ 307 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 308 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 309 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 310 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 311 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 312 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ 313 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 314 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 315 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */ 316 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 317 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 318 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 319 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */ 320 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 321 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ 322 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */ 323 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ 324 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */ 325 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ 326 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */ 327 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ 328 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */ 329 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */ 330 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */ 331 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */ 332 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */ 333 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */ 334 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */ 335 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */ 336 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */ 337 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */ 338 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ 339 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ 340 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ 341 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ 342 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ 343 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 344 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 345 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 346 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 347 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 348 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 349 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 350 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 351 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 352 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 353 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 354 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ 355 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ 356 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 357 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ 358 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ 359 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ 360 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ 361 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ 362 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ 363 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ 364 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ 365 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */ 366 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */ 367 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */ 368 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */ 369 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ 370 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */ 371 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ 372 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */ 373 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ 374 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */ 375 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ 376 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */ 377 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */ 378 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */ 379 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */ 380 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ 381 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */ 382 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ 383 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ 384 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */ 385 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ 386 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/ 387 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/ 388 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/ 389 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/ 390 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ 391 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ 392 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/ 393 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/ 394 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ 395 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ 396 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/ 397 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/ 398 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ 399 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */ 400 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */ 401 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */ 402 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */ 403 404 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 405 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 406 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 407 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 408 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 409 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 410 /* May need to update quirk_jmicron_async_suspend() for additions */ 411 412 /* ATI */ 413 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 414 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 415 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 416 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 417 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 418 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 419 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 420 421 /* AMD */ 422 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 423 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 424 /* AMD is using RAID class only for ahci controllers */ 425 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 426 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 427 428 /* VIA */ 429 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 430 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 431 432 /* NVIDIA */ 433 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 434 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 435 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 436 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 437 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 438 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 439 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 440 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 441 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 442 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 443 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 444 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 445 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 446 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 447 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 448 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 449 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 450 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 451 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 452 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 453 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 454 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 455 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 456 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 457 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 458 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 459 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 460 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 461 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 462 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 463 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 464 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 465 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 466 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 467 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 468 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 469 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 470 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 471 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 472 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 473 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 474 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 475 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 476 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 477 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 478 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 479 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 480 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 481 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 482 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 483 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 484 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 485 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 486 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 487 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 488 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 489 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 490 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 491 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 492 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 493 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 494 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 495 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 496 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 497 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 498 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 499 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 500 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 501 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 502 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 503 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 504 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 505 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 506 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 507 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 508 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 509 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 510 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 511 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 512 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 513 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 514 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 515 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 516 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 517 518 /* SiS */ 519 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 520 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 521 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 522 523 /* ST Microelectronics */ 524 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 525 526 /* Marvell */ 527 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 528 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 529 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 530 .class = PCI_CLASS_STORAGE_SATA_AHCI, 531 .class_mask = 0xffffff, 532 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 533 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 534 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 535 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 536 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 537 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 538 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 539 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 540 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 541 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 542 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 543 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 544 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 545 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 546 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 547 .driver_data = board_ahci_yes_fbs }, 548 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ 549 .driver_data = board_ahci_yes_fbs }, 550 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 551 .driver_data = board_ahci_yes_fbs }, 552 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 553 .driver_data = board_ahci_yes_fbs }, 554 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ 555 .driver_data = board_ahci_yes_fbs }, 556 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ 557 .driver_data = board_ahci_yes_fbs }, 558 559 /* Promise */ 560 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 561 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 562 563 /* Asmedia */ 564 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ 565 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ 566 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ 567 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ 568 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */ 569 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */ 570 571 /* 572 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 573 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 574 */ 575 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, 576 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, 577 578 /* Enmotus */ 579 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 580 581 /* Generic, PCI class code for AHCI */ 582 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 583 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 584 585 { } /* terminate list */ 586 }; 587 588 static const struct dev_pm_ops ahci_pci_pm_ops = { 589 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) 590 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, 591 ahci_pci_device_runtime_resume, NULL) 592 }; 593 594 static struct pci_driver ahci_pci_driver = { 595 .name = DRV_NAME, 596 .id_table = ahci_pci_tbl, 597 .probe = ahci_init_one, 598 .remove = ahci_remove_one, 599 .driver = { 600 .pm = &ahci_pci_pm_ops, 601 }, 602 }; 603 604 #if IS_ENABLED(CONFIG_PATA_MARVELL) 605 static int marvell_enable; 606 #else 607 static int marvell_enable = 1; 608 #endif 609 module_param(marvell_enable, int, 0644); 610 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 611 612 static int mobile_lpm_policy = CONFIG_SATA_MOBILE_LPM_POLICY; 613 module_param(mobile_lpm_policy, int, 0644); 614 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); 615 616 static void ahci_pci_save_initial_config(struct pci_dev *pdev, 617 struct ahci_host_priv *hpriv) 618 { 619 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 620 dev_info(&pdev->dev, "JMB361 has only one port\n"); 621 hpriv->force_port_map = 1; 622 } 623 624 /* 625 * Temporary Marvell 6145 hack: PATA port presence 626 * is asserted through the standard AHCI port 627 * presence register, as bit 4 (counting from 0) 628 */ 629 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 630 if (pdev->device == 0x6121) 631 hpriv->mask_port_map = 0x3; 632 else 633 hpriv->mask_port_map = 0xf; 634 dev_info(&pdev->dev, 635 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 636 } 637 638 ahci_save_initial_config(&pdev->dev, hpriv); 639 } 640 641 static int ahci_pci_reset_controller(struct ata_host *host) 642 { 643 struct pci_dev *pdev = to_pci_dev(host->dev); 644 int rc; 645 646 rc = ahci_reset_controller(host); 647 if (rc) 648 return rc; 649 650 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 651 struct ahci_host_priv *hpriv = host->private_data; 652 u16 tmp16; 653 654 /* configure PCS */ 655 pci_read_config_word(pdev, 0x92, &tmp16); 656 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 657 tmp16 |= hpriv->port_map; 658 pci_write_config_word(pdev, 0x92, tmp16); 659 } 660 } 661 662 return 0; 663 } 664 665 static void ahci_pci_init_controller(struct ata_host *host) 666 { 667 struct ahci_host_priv *hpriv = host->private_data; 668 struct pci_dev *pdev = to_pci_dev(host->dev); 669 void __iomem *port_mmio; 670 u32 tmp; 671 int mv; 672 673 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 674 if (pdev->device == 0x6121) 675 mv = 2; 676 else 677 mv = 4; 678 port_mmio = __ahci_port_base(host, mv); 679 680 writel(0, port_mmio + PORT_IRQ_MASK); 681 682 /* clear port IRQ */ 683 tmp = readl(port_mmio + PORT_IRQ_STAT); 684 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 685 if (tmp) 686 writel(tmp, port_mmio + PORT_IRQ_STAT); 687 } 688 689 ahci_init_controller(host); 690 } 691 692 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 693 unsigned long deadline) 694 { 695 struct ata_port *ap = link->ap; 696 struct ahci_host_priv *hpriv = ap->host->private_data; 697 bool online; 698 int rc; 699 700 DPRINTK("ENTER\n"); 701 702 hpriv->stop_engine(ap); 703 704 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 705 deadline, &online, NULL); 706 707 hpriv->start_engine(ap); 708 709 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 710 711 /* vt8251 doesn't clear BSY on signature FIS reception, 712 * request follow-up softreset. 713 */ 714 return online ? -EAGAIN : rc; 715 } 716 717 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 718 unsigned long deadline) 719 { 720 struct ata_port *ap = link->ap; 721 struct ahci_port_priv *pp = ap->private_data; 722 struct ahci_host_priv *hpriv = ap->host->private_data; 723 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 724 struct ata_taskfile tf; 725 bool online; 726 int rc; 727 728 hpriv->stop_engine(ap); 729 730 /* clear D2H reception area to properly wait for D2H FIS */ 731 ata_tf_init(link->device, &tf); 732 tf.command = ATA_BUSY; 733 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 734 735 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 736 deadline, &online, NULL); 737 738 hpriv->start_engine(ap); 739 740 /* The pseudo configuration device on SIMG4726 attached to 741 * ASUS P5W-DH Deluxe doesn't send signature FIS after 742 * hardreset if no device is attached to the first downstream 743 * port && the pseudo device locks up on SRST w/ PMP==0. To 744 * work around this, wait for !BSY only briefly. If BSY isn't 745 * cleared, perform CLO and proceed to IDENTIFY (achieved by 746 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 747 * 748 * Wait for two seconds. Devices attached to downstream port 749 * which can't process the following IDENTIFY after this will 750 * have to be reset again. For most cases, this should 751 * suffice while making probing snappish enough. 752 */ 753 if (online) { 754 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 755 ahci_check_ready); 756 if (rc) 757 ahci_kick_engine(ap); 758 } 759 return rc; 760 } 761 762 /* 763 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 764 * 765 * It has been observed with some SSDs that the timing of events in the 766 * link synchronization phase can leave the port in a state that can not 767 * be recovered by a SATA-hard-reset alone. The failing signature is 768 * SStatus.DET stuck at 1 ("Device presence detected but Phy 769 * communication not established"). It was found that unloading and 770 * reloading the driver when this problem occurs allows the drive 771 * connection to be recovered (DET advanced to 0x3). The critical 772 * component of reloading the driver is that the port state machines are 773 * reset by bouncing "port enable" in the AHCI PCS configuration 774 * register. So, reproduce that effect by bouncing a port whenever we 775 * see DET==1 after a reset. 776 */ 777 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 778 unsigned long deadline) 779 { 780 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 781 struct ata_port *ap = link->ap; 782 struct ahci_port_priv *pp = ap->private_data; 783 struct ahci_host_priv *hpriv = ap->host->private_data; 784 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 785 unsigned long tmo = deadline - jiffies; 786 struct ata_taskfile tf; 787 bool online; 788 int rc, i; 789 790 DPRINTK("ENTER\n"); 791 792 hpriv->stop_engine(ap); 793 794 for (i = 0; i < 2; i++) { 795 u16 val; 796 u32 sstatus; 797 int port = ap->port_no; 798 struct ata_host *host = ap->host; 799 struct pci_dev *pdev = to_pci_dev(host->dev); 800 801 /* clear D2H reception area to properly wait for D2H FIS */ 802 ata_tf_init(link->device, &tf); 803 tf.command = ATA_BUSY; 804 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 805 806 rc = sata_link_hardreset(link, timing, deadline, &online, 807 ahci_check_ready); 808 809 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 810 (sstatus & 0xf) != 1) 811 break; 812 813 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n", 814 port); 815 816 pci_read_config_word(pdev, 0x92, &val); 817 val &= ~(1 << port); 818 pci_write_config_word(pdev, 0x92, val); 819 ata_msleep(ap, 1000); 820 val |= 1 << port; 821 pci_write_config_word(pdev, 0x92, val); 822 deadline += tmo; 823 } 824 825 hpriv->start_engine(ap); 826 827 if (online) 828 *class = ahci_dev_classify(ap); 829 830 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 831 return rc; 832 } 833 834 835 #ifdef CONFIG_PM 836 static void ahci_pci_disable_interrupts(struct ata_host *host) 837 { 838 struct ahci_host_priv *hpriv = host->private_data; 839 void __iomem *mmio = hpriv->mmio; 840 u32 ctl; 841 842 /* AHCI spec rev1.1 section 8.3.3: 843 * Software must disable interrupts prior to requesting a 844 * transition of the HBA to D3 state. 845 */ 846 ctl = readl(mmio + HOST_CTL); 847 ctl &= ~HOST_IRQ_EN; 848 writel(ctl, mmio + HOST_CTL); 849 readl(mmio + HOST_CTL); /* flush */ 850 } 851 852 static int ahci_pci_device_runtime_suspend(struct device *dev) 853 { 854 struct pci_dev *pdev = to_pci_dev(dev); 855 struct ata_host *host = pci_get_drvdata(pdev); 856 857 ahci_pci_disable_interrupts(host); 858 return 0; 859 } 860 861 static int ahci_pci_device_runtime_resume(struct device *dev) 862 { 863 struct pci_dev *pdev = to_pci_dev(dev); 864 struct ata_host *host = pci_get_drvdata(pdev); 865 int rc; 866 867 rc = ahci_pci_reset_controller(host); 868 if (rc) 869 return rc; 870 ahci_pci_init_controller(host); 871 return 0; 872 } 873 874 #ifdef CONFIG_PM_SLEEP 875 static int ahci_pci_device_suspend(struct device *dev) 876 { 877 struct pci_dev *pdev = to_pci_dev(dev); 878 struct ata_host *host = pci_get_drvdata(pdev); 879 struct ahci_host_priv *hpriv = host->private_data; 880 881 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 882 dev_err(&pdev->dev, 883 "BIOS update required for suspend/resume\n"); 884 return -EIO; 885 } 886 887 ahci_pci_disable_interrupts(host); 888 return ata_host_suspend(host, PMSG_SUSPEND); 889 } 890 891 static int ahci_pci_device_resume(struct device *dev) 892 { 893 struct pci_dev *pdev = to_pci_dev(dev); 894 struct ata_host *host = pci_get_drvdata(pdev); 895 int rc; 896 897 /* Apple BIOS helpfully mangles the registers on resume */ 898 if (is_mcp89_apple(pdev)) 899 ahci_mcp89_apple_enable(pdev); 900 901 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 902 rc = ahci_pci_reset_controller(host); 903 if (rc) 904 return rc; 905 906 ahci_pci_init_controller(host); 907 } 908 909 ata_host_resume(host); 910 911 return 0; 912 } 913 #endif 914 915 #endif /* CONFIG_PM */ 916 917 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 918 { 919 int rc; 920 921 /* 922 * If the device fixup already set the dma_mask to some non-standard 923 * value, don't extend it here. This happens on STA2X11, for example. 924 */ 925 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 926 return 0; 927 928 if (using_dac && 929 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { 930 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); 931 if (rc) { 932 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 933 if (rc) { 934 dev_err(&pdev->dev, 935 "64-bit DMA enable failed\n"); 936 return rc; 937 } 938 } 939 } else { 940 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 941 if (rc) { 942 dev_err(&pdev->dev, "32-bit DMA enable failed\n"); 943 return rc; 944 } 945 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 946 if (rc) { 947 dev_err(&pdev->dev, 948 "32-bit consistent DMA enable failed\n"); 949 return rc; 950 } 951 } 952 return 0; 953 } 954 955 static void ahci_pci_print_info(struct ata_host *host) 956 { 957 struct pci_dev *pdev = to_pci_dev(host->dev); 958 u16 cc; 959 const char *scc_s; 960 961 pci_read_config_word(pdev, 0x0a, &cc); 962 if (cc == PCI_CLASS_STORAGE_IDE) 963 scc_s = "IDE"; 964 else if (cc == PCI_CLASS_STORAGE_SATA) 965 scc_s = "SATA"; 966 else if (cc == PCI_CLASS_STORAGE_RAID) 967 scc_s = "RAID"; 968 else 969 scc_s = "unknown"; 970 971 ahci_print_info(host, scc_s); 972 } 973 974 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 975 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 976 * support PMP and the 4726 either directly exports the device 977 * attached to the first downstream port or acts as a hardware storage 978 * controller and emulate a single ATA device (can be RAID 0/1 or some 979 * other configuration). 980 * 981 * When there's no device attached to the first downstream port of the 982 * 4726, "Config Disk" appears, which is a pseudo ATA device to 983 * configure the 4726. However, ATA emulation of the device is very 984 * lame. It doesn't send signature D2H Reg FIS after the initial 985 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 986 * 987 * The following function works around the problem by always using 988 * hardreset on the port and not depending on receiving signature FIS 989 * afterward. If signature FIS isn't received soon, ATA class is 990 * assumed without follow-up softreset. 991 */ 992 static void ahci_p5wdh_workaround(struct ata_host *host) 993 { 994 static const struct dmi_system_id sysids[] = { 995 { 996 .ident = "P5W DH Deluxe", 997 .matches = { 998 DMI_MATCH(DMI_SYS_VENDOR, 999 "ASUSTEK COMPUTER INC"), 1000 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 1001 }, 1002 }, 1003 { } 1004 }; 1005 struct pci_dev *pdev = to_pci_dev(host->dev); 1006 1007 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 1008 dmi_check_system(sysids)) { 1009 struct ata_port *ap = host->ports[1]; 1010 1011 dev_info(&pdev->dev, 1012 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 1013 1014 ap->ops = &ahci_p5wdh_ops; 1015 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 1016 } 1017 } 1018 1019 /* 1020 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 1021 * booting in BIOS compatibility mode. We restore the registers but not ID. 1022 */ 1023 static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 1024 { 1025 u32 val; 1026 1027 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 1028 1029 pci_read_config_dword(pdev, 0xf8, &val); 1030 val |= 1 << 0x1b; 1031 /* the following changes the device ID, but appears not to affect function */ 1032 /* val = (val & ~0xf0000000) | 0x80000000; */ 1033 pci_write_config_dword(pdev, 0xf8, val); 1034 1035 pci_read_config_dword(pdev, 0x54c, &val); 1036 val |= 1 << 0xc; 1037 pci_write_config_dword(pdev, 0x54c, val); 1038 1039 pci_read_config_dword(pdev, 0x4a4, &val); 1040 val &= 0xff; 1041 val |= 0x01060100; 1042 pci_write_config_dword(pdev, 0x4a4, val); 1043 1044 pci_read_config_dword(pdev, 0x54c, &val); 1045 val &= ~(1 << 0xc); 1046 pci_write_config_dword(pdev, 0x54c, val); 1047 1048 pci_read_config_dword(pdev, 0xf8, &val); 1049 val &= ~(1 << 0x1b); 1050 pci_write_config_dword(pdev, 0xf8, val); 1051 } 1052 1053 static bool is_mcp89_apple(struct pci_dev *pdev) 1054 { 1055 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1056 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1057 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1058 pdev->subsystem_device == 0xcb89; 1059 } 1060 1061 /* only some SB600 ahci controllers can do 64bit DMA */ 1062 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 1063 { 1064 static const struct dmi_system_id sysids[] = { 1065 /* 1066 * The oldest version known to be broken is 0901 and 1067 * working is 1501 which was released on 2007-10-26. 1068 * Enable 64bit DMA on 1501 and anything newer. 1069 * 1070 * Please read bko#9412 for more info. 1071 */ 1072 { 1073 .ident = "ASUS M2A-VM", 1074 .matches = { 1075 DMI_MATCH(DMI_BOARD_VENDOR, 1076 "ASUSTeK Computer INC."), 1077 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 1078 }, 1079 .driver_data = "20071026", /* yyyymmdd */ 1080 }, 1081 /* 1082 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 1083 * support 64bit DMA. 1084 * 1085 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1086 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1087 * This spelling mistake was fixed in BIOS version 1.5, so 1088 * 1.5 and later have the Manufacturer as 1089 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1090 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1091 * 1092 * BIOS versions earlier than 1.9 had a Board Product Name 1093 * DMI field of "MS-7376". This was changed to be 1094 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1095 * match on DMI_BOARD_NAME of "MS-7376". 1096 */ 1097 { 1098 .ident = "MSI K9A2 Platinum", 1099 .matches = { 1100 DMI_MATCH(DMI_BOARD_VENDOR, 1101 "MICRO-STAR INTER"), 1102 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1103 }, 1104 }, 1105 /* 1106 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1107 * 64bit DMA. 1108 * 1109 * This board also had the typo mentioned above in the 1110 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1111 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1112 */ 1113 { 1114 .ident = "MSI K9AGM2", 1115 .matches = { 1116 DMI_MATCH(DMI_BOARD_VENDOR, 1117 "MICRO-STAR INTER"), 1118 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1119 }, 1120 }, 1121 /* 1122 * All BIOS versions for the Asus M3A support 64bit DMA. 1123 * (all release versions from 0301 to 1206 were tested) 1124 */ 1125 { 1126 .ident = "ASUS M3A", 1127 .matches = { 1128 DMI_MATCH(DMI_BOARD_VENDOR, 1129 "ASUSTeK Computer INC."), 1130 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1131 }, 1132 }, 1133 { } 1134 }; 1135 const struct dmi_system_id *match; 1136 int year, month, date; 1137 char buf[9]; 1138 1139 match = dmi_first_match(sysids); 1140 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1141 !match) 1142 return false; 1143 1144 if (!match->driver_data) 1145 goto enable_64bit; 1146 1147 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1148 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1149 1150 if (strcmp(buf, match->driver_data) >= 0) 1151 goto enable_64bit; 1152 else { 1153 dev_warn(&pdev->dev, 1154 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1155 match->ident); 1156 return false; 1157 } 1158 1159 enable_64bit: 1160 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1161 return true; 1162 } 1163 1164 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1165 { 1166 static const struct dmi_system_id broken_systems[] = { 1167 { 1168 .ident = "HP Compaq nx6310", 1169 .matches = { 1170 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1171 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1172 }, 1173 /* PCI slot number of the controller */ 1174 .driver_data = (void *)0x1FUL, 1175 }, 1176 { 1177 .ident = "HP Compaq 6720s", 1178 .matches = { 1179 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1180 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1181 }, 1182 /* PCI slot number of the controller */ 1183 .driver_data = (void *)0x1FUL, 1184 }, 1185 1186 { } /* terminate list */ 1187 }; 1188 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1189 1190 if (dmi) { 1191 unsigned long slot = (unsigned long)dmi->driver_data; 1192 /* apply the quirk only to on-board controllers */ 1193 return slot == PCI_SLOT(pdev->devfn); 1194 } 1195 1196 return false; 1197 } 1198 1199 static bool ahci_broken_suspend(struct pci_dev *pdev) 1200 { 1201 static const struct dmi_system_id sysids[] = { 1202 /* 1203 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1204 * to the harddisk doesn't become online after 1205 * resuming from STR. Warn and fail suspend. 1206 * 1207 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1208 * 1209 * Use dates instead of versions to match as HP is 1210 * apparently recycling both product and version 1211 * strings. 1212 * 1213 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1214 */ 1215 { 1216 .ident = "dv4", 1217 .matches = { 1218 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1219 DMI_MATCH(DMI_PRODUCT_NAME, 1220 "HP Pavilion dv4 Notebook PC"), 1221 }, 1222 .driver_data = "20090105", /* F.30 */ 1223 }, 1224 { 1225 .ident = "dv5", 1226 .matches = { 1227 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1228 DMI_MATCH(DMI_PRODUCT_NAME, 1229 "HP Pavilion dv5 Notebook PC"), 1230 }, 1231 .driver_data = "20090506", /* F.16 */ 1232 }, 1233 { 1234 .ident = "dv6", 1235 .matches = { 1236 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1237 DMI_MATCH(DMI_PRODUCT_NAME, 1238 "HP Pavilion dv6 Notebook PC"), 1239 }, 1240 .driver_data = "20090423", /* F.21 */ 1241 }, 1242 { 1243 .ident = "HDX18", 1244 .matches = { 1245 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1246 DMI_MATCH(DMI_PRODUCT_NAME, 1247 "HP HDX18 Notebook PC"), 1248 }, 1249 .driver_data = "20090430", /* F.23 */ 1250 }, 1251 /* 1252 * Acer eMachines G725 has the same problem. BIOS 1253 * V1.03 is known to be broken. V3.04 is known to 1254 * work. Between, there are V1.06, V2.06 and V3.03 1255 * that we don't have much idea about. For now, 1256 * blacklist anything older than V3.04. 1257 * 1258 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1259 */ 1260 { 1261 .ident = "G725", 1262 .matches = { 1263 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1264 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1265 }, 1266 .driver_data = "20091216", /* V3.04 */ 1267 }, 1268 { } /* terminate list */ 1269 }; 1270 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1271 int year, month, date; 1272 char buf[9]; 1273 1274 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1275 return false; 1276 1277 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1278 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1279 1280 return strcmp(buf, dmi->driver_data) < 0; 1281 } 1282 1283 static bool ahci_broken_online(struct pci_dev *pdev) 1284 { 1285 #define ENCODE_BUSDEVFN(bus, slot, func) \ 1286 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1287 static const struct dmi_system_id sysids[] = { 1288 /* 1289 * There are several gigabyte boards which use 1290 * SIMG5723s configured as hardware RAID. Certain 1291 * 5723 firmware revisions shipped there keep the link 1292 * online but fail to answer properly to SRST or 1293 * IDENTIFY when no device is attached downstream 1294 * causing libata to retry quite a few times leading 1295 * to excessive detection delay. 1296 * 1297 * As these firmwares respond to the second reset try 1298 * with invalid device signature, considering unknown 1299 * sig as offline works around the problem acceptably. 1300 */ 1301 { 1302 .ident = "EP45-DQ6", 1303 .matches = { 1304 DMI_MATCH(DMI_BOARD_VENDOR, 1305 "Gigabyte Technology Co., Ltd."), 1306 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1307 }, 1308 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1309 }, 1310 { 1311 .ident = "EP45-DS5", 1312 .matches = { 1313 DMI_MATCH(DMI_BOARD_VENDOR, 1314 "Gigabyte Technology Co., Ltd."), 1315 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1316 }, 1317 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1318 }, 1319 { } /* terminate list */ 1320 }; 1321 #undef ENCODE_BUSDEVFN 1322 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1323 unsigned int val; 1324 1325 if (!dmi) 1326 return false; 1327 1328 val = (unsigned long)dmi->driver_data; 1329 1330 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1331 } 1332 1333 static bool ahci_broken_devslp(struct pci_dev *pdev) 1334 { 1335 /* device with broken DEVSLP but still showing SDS capability */ 1336 static const struct pci_device_id ids[] = { 1337 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ 1338 {} 1339 }; 1340 1341 return pci_match_id(ids, pdev); 1342 } 1343 1344 #ifdef CONFIG_ATA_ACPI 1345 static void ahci_gtf_filter_workaround(struct ata_host *host) 1346 { 1347 static const struct dmi_system_id sysids[] = { 1348 /* 1349 * Aspire 3810T issues a bunch of SATA enable commands 1350 * via _GTF including an invalid one and one which is 1351 * rejected by the device. Among the successful ones 1352 * is FPDMA non-zero offset enable which when enabled 1353 * only on the drive side leads to NCQ command 1354 * failures. Filter it out. 1355 */ 1356 { 1357 .ident = "Aspire 3810T", 1358 .matches = { 1359 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1360 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1361 }, 1362 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1363 }, 1364 { } 1365 }; 1366 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1367 unsigned int filter; 1368 int i; 1369 1370 if (!dmi) 1371 return; 1372 1373 filter = (unsigned long)dmi->driver_data; 1374 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1375 filter, dmi->ident); 1376 1377 for (i = 0; i < host->n_ports; i++) { 1378 struct ata_port *ap = host->ports[i]; 1379 struct ata_link *link; 1380 struct ata_device *dev; 1381 1382 ata_for_each_link(link, ap, EDGE) 1383 ata_for_each_dev(dev, link, ALL) 1384 dev->gtf_filter |= filter; 1385 } 1386 } 1387 #else 1388 static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1389 {} 1390 #endif 1391 1392 /* 1393 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected 1394 * as DUMMY, or detected but eventually get a "link down" and never get up 1395 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the 1396 * port_map may hold a value of 0x00. 1397 * 1398 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports 1399 * and can significantly reduce the occurrence of the problem. 1400 * 1401 * https://bugzilla.kernel.org/show_bug.cgi?id=189471 1402 */ 1403 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, 1404 struct pci_dev *pdev) 1405 { 1406 static const struct dmi_system_id sysids[] = { 1407 { 1408 .ident = "Acer Switch Alpha 12", 1409 .matches = { 1410 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1411 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") 1412 }, 1413 }, 1414 { } 1415 }; 1416 1417 if (dmi_check_system(sysids)) { 1418 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); 1419 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { 1420 hpriv->port_map = 0x7; 1421 hpriv->cap = 0xC734FF02; 1422 } 1423 } 1424 } 1425 1426 #ifdef CONFIG_ARM64 1427 /* 1428 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. 1429 * Workaround is to make sure all pending IRQs are served before leaving 1430 * handler. 1431 */ 1432 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) 1433 { 1434 struct ata_host *host = dev_instance; 1435 struct ahci_host_priv *hpriv; 1436 unsigned int rc = 0; 1437 void __iomem *mmio; 1438 u32 irq_stat, irq_masked; 1439 unsigned int handled = 1; 1440 1441 VPRINTK("ENTER\n"); 1442 hpriv = host->private_data; 1443 mmio = hpriv->mmio; 1444 irq_stat = readl(mmio + HOST_IRQ_STAT); 1445 if (!irq_stat) 1446 return IRQ_NONE; 1447 1448 do { 1449 irq_masked = irq_stat & hpriv->port_map; 1450 spin_lock(&host->lock); 1451 rc = ahci_handle_port_intr(host, irq_masked); 1452 if (!rc) 1453 handled = 0; 1454 writel(irq_stat, mmio + HOST_IRQ_STAT); 1455 irq_stat = readl(mmio + HOST_IRQ_STAT); 1456 spin_unlock(&host->lock); 1457 } while (irq_stat); 1458 VPRINTK("EXIT\n"); 1459 1460 return IRQ_RETVAL(handled); 1461 } 1462 #endif 1463 1464 static void ahci_remap_check(struct pci_dev *pdev, int bar, 1465 struct ahci_host_priv *hpriv) 1466 { 1467 int i, count = 0; 1468 u32 cap; 1469 1470 /* 1471 * Check if this device might have remapped nvme devices. 1472 */ 1473 if (pdev->vendor != PCI_VENDOR_ID_INTEL || 1474 pci_resource_len(pdev, bar) < SZ_512K || 1475 bar != AHCI_PCI_BAR_STANDARD || 1476 !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) 1477 return; 1478 1479 cap = readq(hpriv->mmio + AHCI_REMAP_CAP); 1480 for (i = 0; i < AHCI_MAX_REMAP; i++) { 1481 if ((cap & (1 << i)) == 0) 1482 continue; 1483 if (readl(hpriv->mmio + ahci_remap_dcc(i)) 1484 != PCI_CLASS_STORAGE_EXPRESS) 1485 continue; 1486 1487 /* We've found a remapped device */ 1488 count++; 1489 } 1490 1491 if (!count) 1492 return; 1493 1494 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count); 1495 dev_warn(&pdev->dev, 1496 "Switch your BIOS from RAID to AHCI mode to use them.\n"); 1497 1498 /* 1499 * Don't rely on the msi-x capability in the remap case, 1500 * share the legacy interrupt across ahci and remapped devices. 1501 */ 1502 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1503 } 1504 1505 static int ahci_get_irq_vector(struct ata_host *host, int port) 1506 { 1507 return pci_irq_vector(to_pci_dev(host->dev), port); 1508 } 1509 1510 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, 1511 struct ahci_host_priv *hpriv) 1512 { 1513 int nvec; 1514 1515 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1516 return -ENODEV; 1517 1518 /* 1519 * If number of MSIs is less than number of ports then Sharing Last 1520 * Message mode could be enforced. In this case assume that advantage 1521 * of multipe MSIs is negated and use single MSI mode instead. 1522 */ 1523 if (n_ports > 1) { 1524 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, 1525 PCI_IRQ_MSIX | PCI_IRQ_MSI); 1526 if (nvec > 0) { 1527 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { 1528 hpriv->get_irq_vector = ahci_get_irq_vector; 1529 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1530 return nvec; 1531 } 1532 1533 /* 1534 * Fallback to single MSI mode if the controller 1535 * enforced MRSM mode. 1536 */ 1537 printk(KERN_INFO 1538 "ahci: MRSM is on, fallback to single MSI\n"); 1539 pci_free_irq_vectors(pdev); 1540 } 1541 } 1542 1543 /* 1544 * If the host is not capable of supporting per-port vectors, fall 1545 * back to single MSI before finally attempting single MSI-X. 1546 */ 1547 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1548 if (nvec == 1) 1549 return nvec; 1550 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); 1551 } 1552 1553 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1554 { 1555 unsigned int board_id = ent->driver_data; 1556 struct ata_port_info pi = ahci_port_info[board_id]; 1557 const struct ata_port_info *ppi[] = { &pi, NULL }; 1558 struct device *dev = &pdev->dev; 1559 struct ahci_host_priv *hpriv; 1560 struct ata_host *host; 1561 int n_ports, i, rc; 1562 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1563 1564 VPRINTK("ENTER\n"); 1565 1566 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1567 1568 ata_print_version_once(&pdev->dev, DRV_VERSION); 1569 1570 /* The AHCI driver can only drive the SATA ports, the PATA driver 1571 can drive them all so if both drivers are selected make sure 1572 AHCI stays out of the way */ 1573 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1574 return -ENODEV; 1575 1576 /* Apple BIOS on MCP89 prevents us using AHCI */ 1577 if (is_mcp89_apple(pdev)) 1578 ahci_mcp89_apple_enable(pdev); 1579 1580 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1581 * At the moment, we can only use the AHCI mode. Let the users know 1582 * that for SAS drives they're out of luck. 1583 */ 1584 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1585 dev_info(&pdev->dev, 1586 "PDC42819 can only drive SATA devices with this driver\n"); 1587 1588 /* Some devices use non-standard BARs */ 1589 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1590 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1591 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1592 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1593 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { 1594 if (pdev->device == 0xa01c) 1595 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; 1596 if (pdev->device == 0xa084) 1597 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; 1598 } 1599 1600 /* acquire resources */ 1601 rc = pcim_enable_device(pdev); 1602 if (rc) 1603 return rc; 1604 1605 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1606 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1607 u8 map; 1608 1609 /* ICH6s share the same PCI ID for both piix and ahci 1610 * modes. Enabling ahci mode while MAP indicates 1611 * combined mode is a bad idea. Yield to ata_piix. 1612 */ 1613 pci_read_config_byte(pdev, ICH_MAP, &map); 1614 if (map & 0x3) { 1615 dev_info(&pdev->dev, 1616 "controller is in combined mode, can't enable AHCI mode\n"); 1617 return -ENODEV; 1618 } 1619 } 1620 1621 /* AHCI controllers often implement SFF compatible interface. 1622 * Grab all PCI BARs just in case. 1623 */ 1624 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1625 if (rc == -EBUSY) 1626 pcim_pin_device(pdev); 1627 if (rc) 1628 return rc; 1629 1630 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1631 if (!hpriv) 1632 return -ENOMEM; 1633 hpriv->flags |= (unsigned long)pi.private_data; 1634 1635 /* MCP65 revision A1 and A2 can't do MSI */ 1636 if (board_id == board_ahci_mcp65 && 1637 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1638 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1639 1640 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1641 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1642 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1643 1644 /* only some SB600s can do 64bit DMA */ 1645 if (ahci_sb600_enable_64bit(pdev)) 1646 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1647 1648 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1649 1650 /* detect remapped nvme devices */ 1651 ahci_remap_check(pdev, ahci_pci_bar, hpriv); 1652 1653 /* must set flag prior to save config in order to take effect */ 1654 if (ahci_broken_devslp(pdev)) 1655 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; 1656 1657 #ifdef CONFIG_ARM64 1658 if (pdev->vendor == 0x177d && pdev->device == 0xa01c) 1659 hpriv->irq_handler = ahci_thunderx_irq_handler; 1660 #endif 1661 1662 /* save initial config */ 1663 ahci_pci_save_initial_config(pdev, hpriv); 1664 1665 /* prepare host */ 1666 if (hpriv->cap & HOST_CAP_NCQ) { 1667 pi.flags |= ATA_FLAG_NCQ; 1668 /* 1669 * Auto-activate optimization is supposed to be 1670 * supported on all AHCI controllers indicating NCQ 1671 * capability, but it seems to be broken on some 1672 * chipsets including NVIDIAs. 1673 */ 1674 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1675 pi.flags |= ATA_FLAG_FPDMA_AA; 1676 1677 /* 1678 * All AHCI controllers should be forward-compatible 1679 * with the new auxiliary field. This code should be 1680 * conditionalized if any buggy AHCI controllers are 1681 * encountered. 1682 */ 1683 pi.flags |= ATA_FLAG_FPDMA_AUX; 1684 } 1685 1686 if (hpriv->cap & HOST_CAP_PMP) 1687 pi.flags |= ATA_FLAG_PMP; 1688 1689 ahci_set_em_messages(hpriv, &pi); 1690 1691 if (ahci_broken_system_poweroff(pdev)) { 1692 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1693 dev_info(&pdev->dev, 1694 "quirky BIOS, skipping spindown on poweroff\n"); 1695 } 1696 1697 if (ahci_broken_suspend(pdev)) { 1698 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1699 dev_warn(&pdev->dev, 1700 "BIOS update required for suspend/resume\n"); 1701 } 1702 1703 if (ahci_broken_online(pdev)) { 1704 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1705 dev_info(&pdev->dev, 1706 "online status unreliable, applying workaround\n"); 1707 } 1708 1709 1710 /* Acer SA5-271 workaround modifies private_data */ 1711 acer_sa5_271_workaround(hpriv, pdev); 1712 1713 /* CAP.NP sometimes indicate the index of the last enabled 1714 * port, at other times, that of the last possible port, so 1715 * determining the maximum port number requires looking at 1716 * both CAP.NP and port_map. 1717 */ 1718 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1719 1720 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1721 if (!host) 1722 return -ENOMEM; 1723 host->private_data = hpriv; 1724 1725 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { 1726 /* legacy intx interrupts */ 1727 pci_intx(pdev, 1); 1728 } 1729 hpriv->irq = pci_irq_vector(pdev, 0); 1730 1731 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1732 host->flags |= ATA_HOST_PARALLEL_SCAN; 1733 else 1734 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1735 1736 if (pi.flags & ATA_FLAG_EM) 1737 ahci_reset_em(host); 1738 1739 for (i = 0; i < host->n_ports; i++) { 1740 struct ata_port *ap = host->ports[i]; 1741 1742 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1743 ata_port_pbar_desc(ap, ahci_pci_bar, 1744 0x100 + ap->port_no * 0x80, "port"); 1745 1746 /* set enclosure management message type */ 1747 if (ap->flags & ATA_FLAG_EM) 1748 ap->em_message_type = hpriv->em_msg_type; 1749 1750 if ((hpriv->flags & AHCI_HFLAG_IS_MOBILE) && 1751 mobile_lpm_policy >= ATA_LPM_UNKNOWN && 1752 mobile_lpm_policy <= ATA_LPM_MIN_POWER) 1753 ap->target_lpm_policy = mobile_lpm_policy; 1754 1755 /* disabled/not-implemented port */ 1756 if (!(hpriv->port_map & (1 << i))) 1757 ap->ops = &ata_dummy_port_ops; 1758 } 1759 1760 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1761 ahci_p5wdh_workaround(host); 1762 1763 /* apply gtf filter quirk */ 1764 ahci_gtf_filter_workaround(host); 1765 1766 /* initialize adapter */ 1767 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 1768 if (rc) 1769 return rc; 1770 1771 rc = ahci_pci_reset_controller(host); 1772 if (rc) 1773 return rc; 1774 1775 ahci_pci_init_controller(host); 1776 ahci_pci_print_info(host); 1777 1778 pci_set_master(pdev); 1779 1780 rc = ahci_host_activate(host, &ahci_sht); 1781 if (rc) 1782 return rc; 1783 1784 pm_runtime_put_noidle(&pdev->dev); 1785 return 0; 1786 } 1787 1788 static void ahci_remove_one(struct pci_dev *pdev) 1789 { 1790 pm_runtime_get_noresume(&pdev->dev); 1791 ata_pci_remove_one(pdev); 1792 } 1793 1794 module_pci_driver(ahci_pci_driver); 1795 1796 MODULE_AUTHOR("Jeff Garzik"); 1797 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1798 MODULE_LICENSE("GPL"); 1799 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1800 MODULE_VERSION(DRV_VERSION); 1801