1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ahci.c - AHCI SATA support 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/device.h> 27 #include <linux/dmi.h> 28 #include <linux/gfp.h> 29 #include <linux/msi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_cmnd.h> 32 #include <linux/libata.h> 33 #include <linux/ahci-remap.h> 34 #include <linux/io-64-nonatomic-lo-hi.h> 35 #include "ahci.h" 36 37 #define DRV_NAME "ahci" 38 #define DRV_VERSION "3.0" 39 40 enum { 41 AHCI_PCI_BAR_STA2X11 = 0, 42 AHCI_PCI_BAR_CAVIUM = 0, 43 AHCI_PCI_BAR_LOONGSON = 0, 44 AHCI_PCI_BAR_ENMOTUS = 2, 45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4, 46 AHCI_PCI_BAR_STANDARD = 5, 47 }; 48 49 enum board_ids { 50 /* board IDs by feature in alphabetical order */ 51 board_ahci, 52 board_ahci_ign_iferr, 53 board_ahci_mobile, 54 board_ahci_nomsi, 55 board_ahci_noncq, 56 board_ahci_nosntf, 57 board_ahci_yes_fbs, 58 59 /* board IDs for specific chipsets in alphabetical order */ 60 board_ahci_al, 61 board_ahci_avn, 62 board_ahci_mcp65, 63 board_ahci_mcp77, 64 board_ahci_mcp89, 65 board_ahci_mv, 66 board_ahci_sb600, 67 board_ahci_sb700, /* for SB700 and SB800 */ 68 board_ahci_vt8251, 69 70 /* 71 * board IDs for Intel chipsets that support more than 6 ports 72 * *and* end up needing the PCS quirk. 73 */ 74 board_ahci_pcs7, 75 76 /* aliases */ 77 board_ahci_mcp_linux = board_ahci_mcp65, 78 board_ahci_mcp67 = board_ahci_mcp65, 79 board_ahci_mcp73 = board_ahci_mcp65, 80 board_ahci_mcp79 = board_ahci_mcp77, 81 }; 82 83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 84 static void ahci_remove_one(struct pci_dev *dev); 85 static void ahci_shutdown_one(struct pci_dev *dev); 86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90 static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 91 static bool is_mcp89_apple(struct pci_dev *pdev); 92 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 93 unsigned long deadline); 94 #ifdef CONFIG_PM 95 static int ahci_pci_device_runtime_suspend(struct device *dev); 96 static int ahci_pci_device_runtime_resume(struct device *dev); 97 #ifdef CONFIG_PM_SLEEP 98 static int ahci_pci_device_suspend(struct device *dev); 99 static int ahci_pci_device_resume(struct device *dev); 100 #endif 101 #endif /* CONFIG_PM */ 102 103 static struct scsi_host_template ahci_sht = { 104 AHCI_SHT("ahci"), 105 }; 106 107 static struct ata_port_operations ahci_vt8251_ops = { 108 .inherits = &ahci_ops, 109 .hardreset = ahci_vt8251_hardreset, 110 }; 111 112 static struct ata_port_operations ahci_p5wdh_ops = { 113 .inherits = &ahci_ops, 114 .hardreset = ahci_p5wdh_hardreset, 115 }; 116 117 static struct ata_port_operations ahci_avn_ops = { 118 .inherits = &ahci_ops, 119 .hardreset = ahci_avn_hardreset, 120 }; 121 122 static const struct ata_port_info ahci_port_info[] = { 123 /* by features */ 124 [board_ahci] = { 125 .flags = AHCI_FLAG_COMMON, 126 .pio_mask = ATA_PIO4, 127 .udma_mask = ATA_UDMA6, 128 .port_ops = &ahci_ops, 129 }, 130 [board_ahci_ign_iferr] = { 131 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 132 .flags = AHCI_FLAG_COMMON, 133 .pio_mask = ATA_PIO4, 134 .udma_mask = ATA_UDMA6, 135 .port_ops = &ahci_ops, 136 }, 137 [board_ahci_mobile] = { 138 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE), 139 .flags = AHCI_FLAG_COMMON, 140 .pio_mask = ATA_PIO4, 141 .udma_mask = ATA_UDMA6, 142 .port_ops = &ahci_ops, 143 }, 144 [board_ahci_nomsi] = { 145 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 146 .flags = AHCI_FLAG_COMMON, 147 .pio_mask = ATA_PIO4, 148 .udma_mask = ATA_UDMA6, 149 .port_ops = &ahci_ops, 150 }, 151 [board_ahci_noncq] = { 152 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 153 .flags = AHCI_FLAG_COMMON, 154 .pio_mask = ATA_PIO4, 155 .udma_mask = ATA_UDMA6, 156 .port_ops = &ahci_ops, 157 }, 158 [board_ahci_nosntf] = { 159 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 160 .flags = AHCI_FLAG_COMMON, 161 .pio_mask = ATA_PIO4, 162 .udma_mask = ATA_UDMA6, 163 .port_ops = &ahci_ops, 164 }, 165 [board_ahci_yes_fbs] = { 166 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 167 .flags = AHCI_FLAG_COMMON, 168 .pio_mask = ATA_PIO4, 169 .udma_mask = ATA_UDMA6, 170 .port_ops = &ahci_ops, 171 }, 172 /* by chipsets */ 173 [board_ahci_al] = { 174 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI), 175 .flags = AHCI_FLAG_COMMON, 176 .pio_mask = ATA_PIO4, 177 .udma_mask = ATA_UDMA6, 178 .port_ops = &ahci_ops, 179 }, 180 [board_ahci_avn] = { 181 .flags = AHCI_FLAG_COMMON, 182 .pio_mask = ATA_PIO4, 183 .udma_mask = ATA_UDMA6, 184 .port_ops = &ahci_avn_ops, 185 }, 186 [board_ahci_mcp65] = { 187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 188 AHCI_HFLAG_YES_NCQ), 189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 190 .pio_mask = ATA_PIO4, 191 .udma_mask = ATA_UDMA6, 192 .port_ops = &ahci_ops, 193 }, 194 [board_ahci_mcp77] = { 195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 196 .flags = AHCI_FLAG_COMMON, 197 .pio_mask = ATA_PIO4, 198 .udma_mask = ATA_UDMA6, 199 .port_ops = &ahci_ops, 200 }, 201 [board_ahci_mcp89] = { 202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 203 .flags = AHCI_FLAG_COMMON, 204 .pio_mask = ATA_PIO4, 205 .udma_mask = ATA_UDMA6, 206 .port_ops = &ahci_ops, 207 }, 208 [board_ahci_mv] = { 209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 212 .pio_mask = ATA_PIO4, 213 .udma_mask = ATA_UDMA6, 214 .port_ops = &ahci_ops, 215 }, 216 [board_ahci_sb600] = { 217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 219 AHCI_HFLAG_32BIT_ONLY), 220 .flags = AHCI_FLAG_COMMON, 221 .pio_mask = ATA_PIO4, 222 .udma_mask = ATA_UDMA6, 223 .port_ops = &ahci_pmp_retry_srst_ops, 224 }, 225 [board_ahci_sb700] = { /* for SB700 and SB800 */ 226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 227 .flags = AHCI_FLAG_COMMON, 228 .pio_mask = ATA_PIO4, 229 .udma_mask = ATA_UDMA6, 230 .port_ops = &ahci_pmp_retry_srst_ops, 231 }, 232 [board_ahci_vt8251] = { 233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 234 .flags = AHCI_FLAG_COMMON, 235 .pio_mask = ATA_PIO4, 236 .udma_mask = ATA_UDMA6, 237 .port_ops = &ahci_vt8251_ops, 238 }, 239 [board_ahci_pcs7] = { 240 .flags = AHCI_FLAG_COMMON, 241 .pio_mask = ATA_PIO4, 242 .udma_mask = ATA_UDMA6, 243 .port_ops = &ahci_ops, 244 }, 245 }; 246 247 static const struct pci_device_id ahci_pci_tbl[] = { 248 /* Intel */ 249 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */ 250 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 251 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 252 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 253 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 254 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 255 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 256 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 257 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 258 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 259 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 260 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 261 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ 262 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 263 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 264 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 265 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 266 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 267 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 268 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 269 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 270 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */ 271 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */ 272 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */ 273 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */ 274 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */ 275 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 276 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */ 277 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 278 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 279 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 280 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 281 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 282 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 283 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 284 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 285 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 286 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */ 287 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 288 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */ 289 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 290 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */ 291 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */ 292 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */ 293 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */ 294 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */ 295 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */ 296 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */ 297 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */ 298 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */ 299 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */ 300 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */ 301 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */ 302 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */ 303 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */ 304 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */ 305 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */ 306 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */ 307 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */ 308 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */ 309 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */ 310 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 311 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */ 312 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 313 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */ 314 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 315 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 316 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 317 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 318 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 319 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ 320 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 321 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 322 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */ 323 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 324 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 325 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 326 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */ 327 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 328 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ 329 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */ 330 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ 331 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */ 332 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ 333 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */ 334 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ 335 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */ 336 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */ 337 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */ 338 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */ 339 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */ 340 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */ 341 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */ 342 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */ 343 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */ 344 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */ 345 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ 346 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ 347 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ 348 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ 349 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ 350 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 351 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 352 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 353 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 354 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 355 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 356 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 357 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 358 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 359 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 360 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 361 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ 362 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ 363 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 364 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ 365 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ 366 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ 367 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ 368 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ 369 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ 370 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ 371 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ 372 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */ 373 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */ 374 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */ 375 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */ 376 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ 377 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */ 378 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ 379 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */ 380 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ 381 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */ 382 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ 383 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */ 384 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */ 385 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */ 386 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */ 387 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ 388 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */ 389 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ 390 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ 391 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */ 392 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ 393 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/ 394 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/ 395 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/ 396 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/ 397 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ 398 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ 399 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/ 400 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/ 401 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ 402 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ 403 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/ 404 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/ 405 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ 406 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */ 407 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */ 408 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */ 409 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */ 410 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */ 411 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */ 412 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */ 413 414 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 415 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 416 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 417 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 418 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 419 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 420 /* May need to update quirk_jmicron_async_suspend() for additions */ 421 422 /* ATI */ 423 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 424 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 425 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 426 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 427 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 428 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 429 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 430 431 /* Amazon's Annapurna Labs support */ 432 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031), 433 .class = PCI_CLASS_STORAGE_SATA_AHCI, 434 .class_mask = 0xffffff, 435 board_ahci_al }, 436 /* AMD */ 437 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 438 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 439 /* AMD is using RAID class only for ahci controllers */ 440 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 441 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 442 443 /* VIA */ 444 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 445 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 446 447 /* NVIDIA */ 448 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 449 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 450 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 451 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 452 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 453 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 454 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 455 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 456 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 457 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 458 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 459 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 460 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 461 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 462 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 463 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 464 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 465 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 466 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 467 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 468 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 469 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 470 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 471 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 472 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 473 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 474 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 475 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 476 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 477 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 478 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 479 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 480 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 481 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 482 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 483 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 484 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 485 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 486 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 487 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 488 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 489 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 490 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 491 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 492 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 493 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 494 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 495 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 496 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 497 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 498 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 499 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 500 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 501 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 502 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 503 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 504 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 505 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 506 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 507 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 508 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 509 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 510 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 511 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 512 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 513 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 514 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 515 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 516 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 517 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 518 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 519 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 520 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 521 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 522 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 523 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 524 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 525 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 526 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 527 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 528 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 529 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 530 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 531 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 532 533 /* SiS */ 534 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 535 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 536 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 537 538 /* ST Microelectronics */ 539 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 540 541 /* Marvell */ 542 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 543 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 544 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 545 .class = PCI_CLASS_STORAGE_SATA_AHCI, 546 .class_mask = 0xffffff, 547 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 548 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 549 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 550 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 551 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 552 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 553 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 554 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 555 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 556 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 557 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 558 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 559 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 560 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 561 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 562 .driver_data = board_ahci_yes_fbs }, 563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ 564 .driver_data = board_ahci_yes_fbs }, 565 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 566 .driver_data = board_ahci_yes_fbs }, 567 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 568 .driver_data = board_ahci_yes_fbs }, 569 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ 570 .driver_data = board_ahci_yes_fbs }, 571 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ 572 .driver_data = board_ahci_yes_fbs }, 573 574 /* Promise */ 575 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 576 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 577 578 /* Asmedia */ 579 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ 580 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ 581 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ 582 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ 583 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */ 584 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */ 585 586 /* 587 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 588 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 589 */ 590 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, 591 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, 592 593 /* Enmotus */ 594 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 595 596 /* Loongson */ 597 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci }, 598 599 /* Generic, PCI class code for AHCI */ 600 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 601 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 602 603 { } /* terminate list */ 604 }; 605 606 static const struct dev_pm_ops ahci_pci_pm_ops = { 607 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) 608 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, 609 ahci_pci_device_runtime_resume, NULL) 610 }; 611 612 static struct pci_driver ahci_pci_driver = { 613 .name = DRV_NAME, 614 .id_table = ahci_pci_tbl, 615 .probe = ahci_init_one, 616 .remove = ahci_remove_one, 617 .shutdown = ahci_shutdown_one, 618 .driver = { 619 .pm = &ahci_pci_pm_ops, 620 }, 621 }; 622 623 #if IS_ENABLED(CONFIG_PATA_MARVELL) 624 static int marvell_enable; 625 #else 626 static int marvell_enable = 1; 627 #endif 628 module_param(marvell_enable, int, 0644); 629 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 630 631 static int mobile_lpm_policy = -1; 632 module_param(mobile_lpm_policy, int, 0644); 633 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); 634 635 static void ahci_pci_save_initial_config(struct pci_dev *pdev, 636 struct ahci_host_priv *hpriv) 637 { 638 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 639 dev_info(&pdev->dev, "JMB361 has only one port\n"); 640 hpriv->force_port_map = 1; 641 } 642 643 /* 644 * Temporary Marvell 6145 hack: PATA port presence 645 * is asserted through the standard AHCI port 646 * presence register, as bit 4 (counting from 0) 647 */ 648 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 649 if (pdev->device == 0x6121) 650 hpriv->mask_port_map = 0x3; 651 else 652 hpriv->mask_port_map = 0xf; 653 dev_info(&pdev->dev, 654 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 655 } 656 657 ahci_save_initial_config(&pdev->dev, hpriv); 658 } 659 660 static void ahci_pci_init_controller(struct ata_host *host) 661 { 662 struct ahci_host_priv *hpriv = host->private_data; 663 struct pci_dev *pdev = to_pci_dev(host->dev); 664 void __iomem *port_mmio; 665 u32 tmp; 666 int mv; 667 668 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 669 if (pdev->device == 0x6121) 670 mv = 2; 671 else 672 mv = 4; 673 port_mmio = __ahci_port_base(host, mv); 674 675 writel(0, port_mmio + PORT_IRQ_MASK); 676 677 /* clear port IRQ */ 678 tmp = readl(port_mmio + PORT_IRQ_STAT); 679 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 680 if (tmp) 681 writel(tmp, port_mmio + PORT_IRQ_STAT); 682 } 683 684 ahci_init_controller(host); 685 } 686 687 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 688 unsigned long deadline) 689 { 690 struct ata_port *ap = link->ap; 691 struct ahci_host_priv *hpriv = ap->host->private_data; 692 bool online; 693 int rc; 694 695 DPRINTK("ENTER\n"); 696 697 hpriv->stop_engine(ap); 698 699 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 700 deadline, &online, NULL); 701 702 hpriv->start_engine(ap); 703 704 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 705 706 /* vt8251 doesn't clear BSY on signature FIS reception, 707 * request follow-up softreset. 708 */ 709 return online ? -EAGAIN : rc; 710 } 711 712 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 713 unsigned long deadline) 714 { 715 struct ata_port *ap = link->ap; 716 struct ahci_port_priv *pp = ap->private_data; 717 struct ahci_host_priv *hpriv = ap->host->private_data; 718 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 719 struct ata_taskfile tf; 720 bool online; 721 int rc; 722 723 hpriv->stop_engine(ap); 724 725 /* clear D2H reception area to properly wait for D2H FIS */ 726 ata_tf_init(link->device, &tf); 727 tf.command = ATA_BUSY; 728 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 729 730 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 731 deadline, &online, NULL); 732 733 hpriv->start_engine(ap); 734 735 /* The pseudo configuration device on SIMG4726 attached to 736 * ASUS P5W-DH Deluxe doesn't send signature FIS after 737 * hardreset if no device is attached to the first downstream 738 * port && the pseudo device locks up on SRST w/ PMP==0. To 739 * work around this, wait for !BSY only briefly. If BSY isn't 740 * cleared, perform CLO and proceed to IDENTIFY (achieved by 741 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 742 * 743 * Wait for two seconds. Devices attached to downstream port 744 * which can't process the following IDENTIFY after this will 745 * have to be reset again. For most cases, this should 746 * suffice while making probing snappish enough. 747 */ 748 if (online) { 749 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 750 ahci_check_ready); 751 if (rc) 752 ahci_kick_engine(ap); 753 } 754 return rc; 755 } 756 757 /* 758 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 759 * 760 * It has been observed with some SSDs that the timing of events in the 761 * link synchronization phase can leave the port in a state that can not 762 * be recovered by a SATA-hard-reset alone. The failing signature is 763 * SStatus.DET stuck at 1 ("Device presence detected but Phy 764 * communication not established"). It was found that unloading and 765 * reloading the driver when this problem occurs allows the drive 766 * connection to be recovered (DET advanced to 0x3). The critical 767 * component of reloading the driver is that the port state machines are 768 * reset by bouncing "port enable" in the AHCI PCS configuration 769 * register. So, reproduce that effect by bouncing a port whenever we 770 * see DET==1 after a reset. 771 */ 772 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 773 unsigned long deadline) 774 { 775 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 776 struct ata_port *ap = link->ap; 777 struct ahci_port_priv *pp = ap->private_data; 778 struct ahci_host_priv *hpriv = ap->host->private_data; 779 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 780 unsigned long tmo = deadline - jiffies; 781 struct ata_taskfile tf; 782 bool online; 783 int rc, i; 784 785 DPRINTK("ENTER\n"); 786 787 hpriv->stop_engine(ap); 788 789 for (i = 0; i < 2; i++) { 790 u16 val; 791 u32 sstatus; 792 int port = ap->port_no; 793 struct ata_host *host = ap->host; 794 struct pci_dev *pdev = to_pci_dev(host->dev); 795 796 /* clear D2H reception area to properly wait for D2H FIS */ 797 ata_tf_init(link->device, &tf); 798 tf.command = ATA_BUSY; 799 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 800 801 rc = sata_link_hardreset(link, timing, deadline, &online, 802 ahci_check_ready); 803 804 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 805 (sstatus & 0xf) != 1) 806 break; 807 808 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n", 809 port); 810 811 pci_read_config_word(pdev, 0x92, &val); 812 val &= ~(1 << port); 813 pci_write_config_word(pdev, 0x92, val); 814 ata_msleep(ap, 1000); 815 val |= 1 << port; 816 pci_write_config_word(pdev, 0x92, val); 817 deadline += tmo; 818 } 819 820 hpriv->start_engine(ap); 821 822 if (online) 823 *class = ahci_dev_classify(ap); 824 825 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 826 return rc; 827 } 828 829 830 #ifdef CONFIG_PM 831 static void ahci_pci_disable_interrupts(struct ata_host *host) 832 { 833 struct ahci_host_priv *hpriv = host->private_data; 834 void __iomem *mmio = hpriv->mmio; 835 u32 ctl; 836 837 /* AHCI spec rev1.1 section 8.3.3: 838 * Software must disable interrupts prior to requesting a 839 * transition of the HBA to D3 state. 840 */ 841 ctl = readl(mmio + HOST_CTL); 842 ctl &= ~HOST_IRQ_EN; 843 writel(ctl, mmio + HOST_CTL); 844 readl(mmio + HOST_CTL); /* flush */ 845 } 846 847 static int ahci_pci_device_runtime_suspend(struct device *dev) 848 { 849 struct pci_dev *pdev = to_pci_dev(dev); 850 struct ata_host *host = pci_get_drvdata(pdev); 851 852 ahci_pci_disable_interrupts(host); 853 return 0; 854 } 855 856 static int ahci_pci_device_runtime_resume(struct device *dev) 857 { 858 struct pci_dev *pdev = to_pci_dev(dev); 859 struct ata_host *host = pci_get_drvdata(pdev); 860 int rc; 861 862 rc = ahci_reset_controller(host); 863 if (rc) 864 return rc; 865 ahci_pci_init_controller(host); 866 return 0; 867 } 868 869 #ifdef CONFIG_PM_SLEEP 870 static int ahci_pci_device_suspend(struct device *dev) 871 { 872 struct pci_dev *pdev = to_pci_dev(dev); 873 struct ata_host *host = pci_get_drvdata(pdev); 874 struct ahci_host_priv *hpriv = host->private_data; 875 876 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 877 dev_err(&pdev->dev, 878 "BIOS update required for suspend/resume\n"); 879 return -EIO; 880 } 881 882 ahci_pci_disable_interrupts(host); 883 return ata_host_suspend(host, PMSG_SUSPEND); 884 } 885 886 static int ahci_pci_device_resume(struct device *dev) 887 { 888 struct pci_dev *pdev = to_pci_dev(dev); 889 struct ata_host *host = pci_get_drvdata(pdev); 890 int rc; 891 892 /* Apple BIOS helpfully mangles the registers on resume */ 893 if (is_mcp89_apple(pdev)) 894 ahci_mcp89_apple_enable(pdev); 895 896 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 897 rc = ahci_reset_controller(host); 898 if (rc) 899 return rc; 900 901 ahci_pci_init_controller(host); 902 } 903 904 ata_host_resume(host); 905 906 return 0; 907 } 908 #endif 909 910 #endif /* CONFIG_PM */ 911 912 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 913 { 914 const int dma_bits = using_dac ? 64 : 32; 915 int rc; 916 917 /* 918 * If the device fixup already set the dma_mask to some non-standard 919 * value, don't extend it here. This happens on STA2X11, for example. 920 * 921 * XXX: manipulating the DMA mask from platform code is completely 922 * bogus, platform code should use dev->bus_dma_limit instead.. 923 */ 924 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 925 return 0; 926 927 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits)); 928 if (rc) 929 dev_err(&pdev->dev, "DMA enable failed\n"); 930 return rc; 931 } 932 933 static void ahci_pci_print_info(struct ata_host *host) 934 { 935 struct pci_dev *pdev = to_pci_dev(host->dev); 936 u16 cc; 937 const char *scc_s; 938 939 pci_read_config_word(pdev, 0x0a, &cc); 940 if (cc == PCI_CLASS_STORAGE_IDE) 941 scc_s = "IDE"; 942 else if (cc == PCI_CLASS_STORAGE_SATA) 943 scc_s = "SATA"; 944 else if (cc == PCI_CLASS_STORAGE_RAID) 945 scc_s = "RAID"; 946 else 947 scc_s = "unknown"; 948 949 ahci_print_info(host, scc_s); 950 } 951 952 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 953 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 954 * support PMP and the 4726 either directly exports the device 955 * attached to the first downstream port or acts as a hardware storage 956 * controller and emulate a single ATA device (can be RAID 0/1 or some 957 * other configuration). 958 * 959 * When there's no device attached to the first downstream port of the 960 * 4726, "Config Disk" appears, which is a pseudo ATA device to 961 * configure the 4726. However, ATA emulation of the device is very 962 * lame. It doesn't send signature D2H Reg FIS after the initial 963 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 964 * 965 * The following function works around the problem by always using 966 * hardreset on the port and not depending on receiving signature FIS 967 * afterward. If signature FIS isn't received soon, ATA class is 968 * assumed without follow-up softreset. 969 */ 970 static void ahci_p5wdh_workaround(struct ata_host *host) 971 { 972 static const struct dmi_system_id sysids[] = { 973 { 974 .ident = "P5W DH Deluxe", 975 .matches = { 976 DMI_MATCH(DMI_SYS_VENDOR, 977 "ASUSTEK COMPUTER INC"), 978 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 979 }, 980 }, 981 { } 982 }; 983 struct pci_dev *pdev = to_pci_dev(host->dev); 984 985 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 986 dmi_check_system(sysids)) { 987 struct ata_port *ap = host->ports[1]; 988 989 dev_info(&pdev->dev, 990 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 991 992 ap->ops = &ahci_p5wdh_ops; 993 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 994 } 995 } 996 997 /* 998 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 999 * booting in BIOS compatibility mode. We restore the registers but not ID. 1000 */ 1001 static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 1002 { 1003 u32 val; 1004 1005 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 1006 1007 pci_read_config_dword(pdev, 0xf8, &val); 1008 val |= 1 << 0x1b; 1009 /* the following changes the device ID, but appears not to affect function */ 1010 /* val = (val & ~0xf0000000) | 0x80000000; */ 1011 pci_write_config_dword(pdev, 0xf8, val); 1012 1013 pci_read_config_dword(pdev, 0x54c, &val); 1014 val |= 1 << 0xc; 1015 pci_write_config_dword(pdev, 0x54c, val); 1016 1017 pci_read_config_dword(pdev, 0x4a4, &val); 1018 val &= 0xff; 1019 val |= 0x01060100; 1020 pci_write_config_dword(pdev, 0x4a4, val); 1021 1022 pci_read_config_dword(pdev, 0x54c, &val); 1023 val &= ~(1 << 0xc); 1024 pci_write_config_dword(pdev, 0x54c, val); 1025 1026 pci_read_config_dword(pdev, 0xf8, &val); 1027 val &= ~(1 << 0x1b); 1028 pci_write_config_dword(pdev, 0xf8, val); 1029 } 1030 1031 static bool is_mcp89_apple(struct pci_dev *pdev) 1032 { 1033 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1034 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1035 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1036 pdev->subsystem_device == 0xcb89; 1037 } 1038 1039 /* only some SB600 ahci controllers can do 64bit DMA */ 1040 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 1041 { 1042 static const struct dmi_system_id sysids[] = { 1043 /* 1044 * The oldest version known to be broken is 0901 and 1045 * working is 1501 which was released on 2007-10-26. 1046 * Enable 64bit DMA on 1501 and anything newer. 1047 * 1048 * Please read bko#9412 for more info. 1049 */ 1050 { 1051 .ident = "ASUS M2A-VM", 1052 .matches = { 1053 DMI_MATCH(DMI_BOARD_VENDOR, 1054 "ASUSTeK Computer INC."), 1055 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 1056 }, 1057 .driver_data = "20071026", /* yyyymmdd */ 1058 }, 1059 /* 1060 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 1061 * support 64bit DMA. 1062 * 1063 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1064 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1065 * This spelling mistake was fixed in BIOS version 1.5, so 1066 * 1.5 and later have the Manufacturer as 1067 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1068 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1069 * 1070 * BIOS versions earlier than 1.9 had a Board Product Name 1071 * DMI field of "MS-7376". This was changed to be 1072 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1073 * match on DMI_BOARD_NAME of "MS-7376". 1074 */ 1075 { 1076 .ident = "MSI K9A2 Platinum", 1077 .matches = { 1078 DMI_MATCH(DMI_BOARD_VENDOR, 1079 "MICRO-STAR INTER"), 1080 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1081 }, 1082 }, 1083 /* 1084 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1085 * 64bit DMA. 1086 * 1087 * This board also had the typo mentioned above in the 1088 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1089 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1090 */ 1091 { 1092 .ident = "MSI K9AGM2", 1093 .matches = { 1094 DMI_MATCH(DMI_BOARD_VENDOR, 1095 "MICRO-STAR INTER"), 1096 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1097 }, 1098 }, 1099 /* 1100 * All BIOS versions for the Asus M3A support 64bit DMA. 1101 * (all release versions from 0301 to 1206 were tested) 1102 */ 1103 { 1104 .ident = "ASUS M3A", 1105 .matches = { 1106 DMI_MATCH(DMI_BOARD_VENDOR, 1107 "ASUSTeK Computer INC."), 1108 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1109 }, 1110 }, 1111 { } 1112 }; 1113 const struct dmi_system_id *match; 1114 int year, month, date; 1115 char buf[9]; 1116 1117 match = dmi_first_match(sysids); 1118 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1119 !match) 1120 return false; 1121 1122 if (!match->driver_data) 1123 goto enable_64bit; 1124 1125 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1126 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1127 1128 if (strcmp(buf, match->driver_data) >= 0) 1129 goto enable_64bit; 1130 else { 1131 dev_warn(&pdev->dev, 1132 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1133 match->ident); 1134 return false; 1135 } 1136 1137 enable_64bit: 1138 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1139 return true; 1140 } 1141 1142 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1143 { 1144 static const struct dmi_system_id broken_systems[] = { 1145 { 1146 .ident = "HP Compaq nx6310", 1147 .matches = { 1148 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1149 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1150 }, 1151 /* PCI slot number of the controller */ 1152 .driver_data = (void *)0x1FUL, 1153 }, 1154 { 1155 .ident = "HP Compaq 6720s", 1156 .matches = { 1157 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1158 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1159 }, 1160 /* PCI slot number of the controller */ 1161 .driver_data = (void *)0x1FUL, 1162 }, 1163 1164 { } /* terminate list */ 1165 }; 1166 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1167 1168 if (dmi) { 1169 unsigned long slot = (unsigned long)dmi->driver_data; 1170 /* apply the quirk only to on-board controllers */ 1171 return slot == PCI_SLOT(pdev->devfn); 1172 } 1173 1174 return false; 1175 } 1176 1177 static bool ahci_broken_suspend(struct pci_dev *pdev) 1178 { 1179 static const struct dmi_system_id sysids[] = { 1180 /* 1181 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1182 * to the harddisk doesn't become online after 1183 * resuming from STR. Warn and fail suspend. 1184 * 1185 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1186 * 1187 * Use dates instead of versions to match as HP is 1188 * apparently recycling both product and version 1189 * strings. 1190 * 1191 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1192 */ 1193 { 1194 .ident = "dv4", 1195 .matches = { 1196 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1197 DMI_MATCH(DMI_PRODUCT_NAME, 1198 "HP Pavilion dv4 Notebook PC"), 1199 }, 1200 .driver_data = "20090105", /* F.30 */ 1201 }, 1202 { 1203 .ident = "dv5", 1204 .matches = { 1205 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1206 DMI_MATCH(DMI_PRODUCT_NAME, 1207 "HP Pavilion dv5 Notebook PC"), 1208 }, 1209 .driver_data = "20090506", /* F.16 */ 1210 }, 1211 { 1212 .ident = "dv6", 1213 .matches = { 1214 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1215 DMI_MATCH(DMI_PRODUCT_NAME, 1216 "HP Pavilion dv6 Notebook PC"), 1217 }, 1218 .driver_data = "20090423", /* F.21 */ 1219 }, 1220 { 1221 .ident = "HDX18", 1222 .matches = { 1223 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1224 DMI_MATCH(DMI_PRODUCT_NAME, 1225 "HP HDX18 Notebook PC"), 1226 }, 1227 .driver_data = "20090430", /* F.23 */ 1228 }, 1229 /* 1230 * Acer eMachines G725 has the same problem. BIOS 1231 * V1.03 is known to be broken. V3.04 is known to 1232 * work. Between, there are V1.06, V2.06 and V3.03 1233 * that we don't have much idea about. For now, 1234 * blacklist anything older than V3.04. 1235 * 1236 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1237 */ 1238 { 1239 .ident = "G725", 1240 .matches = { 1241 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1242 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1243 }, 1244 .driver_data = "20091216", /* V3.04 */ 1245 }, 1246 { } /* terminate list */ 1247 }; 1248 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1249 int year, month, date; 1250 char buf[9]; 1251 1252 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1253 return false; 1254 1255 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1256 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1257 1258 return strcmp(buf, dmi->driver_data) < 0; 1259 } 1260 1261 static bool ahci_broken_lpm(struct pci_dev *pdev) 1262 { 1263 static const struct dmi_system_id sysids[] = { 1264 /* Various Lenovo 50 series have LPM issues with older BIOSen */ 1265 { 1266 .matches = { 1267 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1268 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), 1269 }, 1270 .driver_data = "20180406", /* 1.31 */ 1271 }, 1272 { 1273 .matches = { 1274 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1275 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), 1276 }, 1277 .driver_data = "20180420", /* 1.28 */ 1278 }, 1279 { 1280 .matches = { 1281 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1282 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), 1283 }, 1284 .driver_data = "20180315", /* 1.33 */ 1285 }, 1286 { 1287 .matches = { 1288 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1289 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), 1290 }, 1291 /* 1292 * Note date based on release notes, 2.35 has been 1293 * reported to be good, but I've been unable to get 1294 * a hold of the reporter to get the DMI BIOS date. 1295 * TODO: fix this. 1296 */ 1297 .driver_data = "20180310", /* 2.35 */ 1298 }, 1299 { } /* terminate list */ 1300 }; 1301 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1302 int year, month, date; 1303 char buf[9]; 1304 1305 if (!dmi) 1306 return false; 1307 1308 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1309 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1310 1311 return strcmp(buf, dmi->driver_data) < 0; 1312 } 1313 1314 static bool ahci_broken_online(struct pci_dev *pdev) 1315 { 1316 #define ENCODE_BUSDEVFN(bus, slot, func) \ 1317 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1318 static const struct dmi_system_id sysids[] = { 1319 /* 1320 * There are several gigabyte boards which use 1321 * SIMG5723s configured as hardware RAID. Certain 1322 * 5723 firmware revisions shipped there keep the link 1323 * online but fail to answer properly to SRST or 1324 * IDENTIFY when no device is attached downstream 1325 * causing libata to retry quite a few times leading 1326 * to excessive detection delay. 1327 * 1328 * As these firmwares respond to the second reset try 1329 * with invalid device signature, considering unknown 1330 * sig as offline works around the problem acceptably. 1331 */ 1332 { 1333 .ident = "EP45-DQ6", 1334 .matches = { 1335 DMI_MATCH(DMI_BOARD_VENDOR, 1336 "Gigabyte Technology Co., Ltd."), 1337 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1338 }, 1339 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1340 }, 1341 { 1342 .ident = "EP45-DS5", 1343 .matches = { 1344 DMI_MATCH(DMI_BOARD_VENDOR, 1345 "Gigabyte Technology Co., Ltd."), 1346 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1347 }, 1348 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1349 }, 1350 { } /* terminate list */ 1351 }; 1352 #undef ENCODE_BUSDEVFN 1353 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1354 unsigned int val; 1355 1356 if (!dmi) 1357 return false; 1358 1359 val = (unsigned long)dmi->driver_data; 1360 1361 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1362 } 1363 1364 static bool ahci_broken_devslp(struct pci_dev *pdev) 1365 { 1366 /* device with broken DEVSLP but still showing SDS capability */ 1367 static const struct pci_device_id ids[] = { 1368 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ 1369 {} 1370 }; 1371 1372 return pci_match_id(ids, pdev); 1373 } 1374 1375 #ifdef CONFIG_ATA_ACPI 1376 static void ahci_gtf_filter_workaround(struct ata_host *host) 1377 { 1378 static const struct dmi_system_id sysids[] = { 1379 /* 1380 * Aspire 3810T issues a bunch of SATA enable commands 1381 * via _GTF including an invalid one and one which is 1382 * rejected by the device. Among the successful ones 1383 * is FPDMA non-zero offset enable which when enabled 1384 * only on the drive side leads to NCQ command 1385 * failures. Filter it out. 1386 */ 1387 { 1388 .ident = "Aspire 3810T", 1389 .matches = { 1390 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1391 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1392 }, 1393 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1394 }, 1395 { } 1396 }; 1397 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1398 unsigned int filter; 1399 int i; 1400 1401 if (!dmi) 1402 return; 1403 1404 filter = (unsigned long)dmi->driver_data; 1405 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1406 filter, dmi->ident); 1407 1408 for (i = 0; i < host->n_ports; i++) { 1409 struct ata_port *ap = host->ports[i]; 1410 struct ata_link *link; 1411 struct ata_device *dev; 1412 1413 ata_for_each_link(link, ap, EDGE) 1414 ata_for_each_dev(dev, link, ALL) 1415 dev->gtf_filter |= filter; 1416 } 1417 } 1418 #else 1419 static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1420 {} 1421 #endif 1422 1423 /* 1424 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected 1425 * as DUMMY, or detected but eventually get a "link down" and never get up 1426 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the 1427 * port_map may hold a value of 0x00. 1428 * 1429 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports 1430 * and can significantly reduce the occurrence of the problem. 1431 * 1432 * https://bugzilla.kernel.org/show_bug.cgi?id=189471 1433 */ 1434 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, 1435 struct pci_dev *pdev) 1436 { 1437 static const struct dmi_system_id sysids[] = { 1438 { 1439 .ident = "Acer Switch Alpha 12", 1440 .matches = { 1441 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1442 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") 1443 }, 1444 }, 1445 { } 1446 }; 1447 1448 if (dmi_check_system(sysids)) { 1449 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); 1450 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { 1451 hpriv->port_map = 0x7; 1452 hpriv->cap = 0xC734FF02; 1453 } 1454 } 1455 } 1456 1457 #ifdef CONFIG_ARM64 1458 /* 1459 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. 1460 * Workaround is to make sure all pending IRQs are served before leaving 1461 * handler. 1462 */ 1463 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) 1464 { 1465 struct ata_host *host = dev_instance; 1466 struct ahci_host_priv *hpriv; 1467 unsigned int rc = 0; 1468 void __iomem *mmio; 1469 u32 irq_stat, irq_masked; 1470 unsigned int handled = 1; 1471 1472 VPRINTK("ENTER\n"); 1473 hpriv = host->private_data; 1474 mmio = hpriv->mmio; 1475 irq_stat = readl(mmio + HOST_IRQ_STAT); 1476 if (!irq_stat) 1477 return IRQ_NONE; 1478 1479 do { 1480 irq_masked = irq_stat & hpriv->port_map; 1481 spin_lock(&host->lock); 1482 rc = ahci_handle_port_intr(host, irq_masked); 1483 if (!rc) 1484 handled = 0; 1485 writel(irq_stat, mmio + HOST_IRQ_STAT); 1486 irq_stat = readl(mmio + HOST_IRQ_STAT); 1487 spin_unlock(&host->lock); 1488 } while (irq_stat); 1489 VPRINTK("EXIT\n"); 1490 1491 return IRQ_RETVAL(handled); 1492 } 1493 #endif 1494 1495 static void ahci_remap_check(struct pci_dev *pdev, int bar, 1496 struct ahci_host_priv *hpriv) 1497 { 1498 int i, count = 0; 1499 u32 cap; 1500 1501 /* 1502 * Check if this device might have remapped nvme devices. 1503 */ 1504 if (pdev->vendor != PCI_VENDOR_ID_INTEL || 1505 pci_resource_len(pdev, bar) < SZ_512K || 1506 bar != AHCI_PCI_BAR_STANDARD || 1507 !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) 1508 return; 1509 1510 cap = readq(hpriv->mmio + AHCI_REMAP_CAP); 1511 for (i = 0; i < AHCI_MAX_REMAP; i++) { 1512 if ((cap & (1 << i)) == 0) 1513 continue; 1514 if (readl(hpriv->mmio + ahci_remap_dcc(i)) 1515 != PCI_CLASS_STORAGE_EXPRESS) 1516 continue; 1517 1518 /* We've found a remapped device */ 1519 count++; 1520 } 1521 1522 if (!count) 1523 return; 1524 1525 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count); 1526 dev_warn(&pdev->dev, 1527 "Switch your BIOS from RAID to AHCI mode to use them.\n"); 1528 1529 /* 1530 * Don't rely on the msi-x capability in the remap case, 1531 * share the legacy interrupt across ahci and remapped devices. 1532 */ 1533 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1534 } 1535 1536 static int ahci_get_irq_vector(struct ata_host *host, int port) 1537 { 1538 return pci_irq_vector(to_pci_dev(host->dev), port); 1539 } 1540 1541 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, 1542 struct ahci_host_priv *hpriv) 1543 { 1544 int nvec; 1545 1546 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1547 return -ENODEV; 1548 1549 /* 1550 * If number of MSIs is less than number of ports then Sharing Last 1551 * Message mode could be enforced. In this case assume that advantage 1552 * of multipe MSIs is negated and use single MSI mode instead. 1553 */ 1554 if (n_ports > 1) { 1555 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, 1556 PCI_IRQ_MSIX | PCI_IRQ_MSI); 1557 if (nvec > 0) { 1558 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { 1559 hpriv->get_irq_vector = ahci_get_irq_vector; 1560 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1561 return nvec; 1562 } 1563 1564 /* 1565 * Fallback to single MSI mode if the controller 1566 * enforced MRSM mode. 1567 */ 1568 printk(KERN_INFO 1569 "ahci: MRSM is on, fallback to single MSI\n"); 1570 pci_free_irq_vectors(pdev); 1571 } 1572 } 1573 1574 /* 1575 * If the host is not capable of supporting per-port vectors, fall 1576 * back to single MSI before finally attempting single MSI-X. 1577 */ 1578 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1579 if (nvec == 1) 1580 return nvec; 1581 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); 1582 } 1583 1584 static void ahci_update_initial_lpm_policy(struct ata_port *ap, 1585 struct ahci_host_priv *hpriv) 1586 { 1587 int policy = CONFIG_SATA_MOBILE_LPM_POLICY; 1588 1589 1590 /* Ignore processing for non mobile platforms */ 1591 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE)) 1592 return; 1593 1594 /* user modified policy via module param */ 1595 if (mobile_lpm_policy != -1) { 1596 policy = mobile_lpm_policy; 1597 goto update_policy; 1598 } 1599 1600 #ifdef CONFIG_ACPI 1601 if (policy > ATA_LPM_MED_POWER && 1602 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) { 1603 if (hpriv->cap & HOST_CAP_PART) 1604 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL; 1605 else if (hpriv->cap & HOST_CAP_SSC) 1606 policy = ATA_LPM_MIN_POWER; 1607 } 1608 #endif 1609 1610 update_policy: 1611 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER) 1612 ap->target_lpm_policy = policy; 1613 } 1614 1615 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv) 1616 { 1617 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev); 1618 u16 tmp16; 1619 1620 /* 1621 * Only apply the 6-port PCS quirk for known legacy platforms. 1622 */ 1623 if (!id || id->vendor != PCI_VENDOR_ID_INTEL) 1624 return; 1625 1626 /* Skip applying the quirk on Denverton and beyond */ 1627 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7) 1628 return; 1629 1630 /* 1631 * port_map is determined from PORTS_IMPL PCI register which is 1632 * implemented as write or write-once register. If the register 1633 * isn't programmed, ahci automatically generates it from number 1634 * of ports, which is good enough for PCS programming. It is 1635 * otherwise expected that platform firmware enables the ports 1636 * before the OS boots. 1637 */ 1638 pci_read_config_word(pdev, PCS_6, &tmp16); 1639 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 1640 tmp16 |= hpriv->port_map; 1641 pci_write_config_word(pdev, PCS_6, tmp16); 1642 } 1643 } 1644 1645 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1646 { 1647 unsigned int board_id = ent->driver_data; 1648 struct ata_port_info pi = ahci_port_info[board_id]; 1649 const struct ata_port_info *ppi[] = { &pi, NULL }; 1650 struct device *dev = &pdev->dev; 1651 struct ahci_host_priv *hpriv; 1652 struct ata_host *host; 1653 int n_ports, i, rc; 1654 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1655 1656 VPRINTK("ENTER\n"); 1657 1658 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1659 1660 ata_print_version_once(&pdev->dev, DRV_VERSION); 1661 1662 /* The AHCI driver can only drive the SATA ports, the PATA driver 1663 can drive them all so if both drivers are selected make sure 1664 AHCI stays out of the way */ 1665 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1666 return -ENODEV; 1667 1668 /* Apple BIOS on MCP89 prevents us using AHCI */ 1669 if (is_mcp89_apple(pdev)) 1670 ahci_mcp89_apple_enable(pdev); 1671 1672 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1673 * At the moment, we can only use the AHCI mode. Let the users know 1674 * that for SAS drives they're out of luck. 1675 */ 1676 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1677 dev_info(&pdev->dev, 1678 "PDC42819 can only drive SATA devices with this driver\n"); 1679 1680 /* Some devices use non-standard BARs */ 1681 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1682 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1683 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1684 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1685 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { 1686 if (pdev->device == 0xa01c) 1687 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; 1688 if (pdev->device == 0xa084) 1689 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; 1690 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) { 1691 if (pdev->device == 0x7a08) 1692 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON; 1693 } 1694 1695 /* acquire resources */ 1696 rc = pcim_enable_device(pdev); 1697 if (rc) 1698 return rc; 1699 1700 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1701 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1702 u8 map; 1703 1704 /* ICH6s share the same PCI ID for both piix and ahci 1705 * modes. Enabling ahci mode while MAP indicates 1706 * combined mode is a bad idea. Yield to ata_piix. 1707 */ 1708 pci_read_config_byte(pdev, ICH_MAP, &map); 1709 if (map & 0x3) { 1710 dev_info(&pdev->dev, 1711 "controller is in combined mode, can't enable AHCI mode\n"); 1712 return -ENODEV; 1713 } 1714 } 1715 1716 /* AHCI controllers often implement SFF compatible interface. 1717 * Grab all PCI BARs just in case. 1718 */ 1719 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1720 if (rc == -EBUSY) 1721 pcim_pin_device(pdev); 1722 if (rc) 1723 return rc; 1724 1725 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1726 if (!hpriv) 1727 return -ENOMEM; 1728 hpriv->flags |= (unsigned long)pi.private_data; 1729 1730 /* MCP65 revision A1 and A2 can't do MSI */ 1731 if (board_id == board_ahci_mcp65 && 1732 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1733 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1734 1735 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1736 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1737 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1738 1739 /* only some SB600s can do 64bit DMA */ 1740 if (ahci_sb600_enable_64bit(pdev)) 1741 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1742 1743 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1744 1745 /* detect remapped nvme devices */ 1746 ahci_remap_check(pdev, ahci_pci_bar, hpriv); 1747 1748 /* must set flag prior to save config in order to take effect */ 1749 if (ahci_broken_devslp(pdev)) 1750 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; 1751 1752 #ifdef CONFIG_ARM64 1753 if (pdev->vendor == 0x177d && pdev->device == 0xa01c) 1754 hpriv->irq_handler = ahci_thunderx_irq_handler; 1755 #endif 1756 1757 /* save initial config */ 1758 ahci_pci_save_initial_config(pdev, hpriv); 1759 1760 /* 1761 * If platform firmware failed to enable ports, try to enable 1762 * them here. 1763 */ 1764 ahci_intel_pcs_quirk(pdev, hpriv); 1765 1766 /* prepare host */ 1767 if (hpriv->cap & HOST_CAP_NCQ) { 1768 pi.flags |= ATA_FLAG_NCQ; 1769 /* 1770 * Auto-activate optimization is supposed to be 1771 * supported on all AHCI controllers indicating NCQ 1772 * capability, but it seems to be broken on some 1773 * chipsets including NVIDIAs. 1774 */ 1775 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1776 pi.flags |= ATA_FLAG_FPDMA_AA; 1777 1778 /* 1779 * All AHCI controllers should be forward-compatible 1780 * with the new auxiliary field. This code should be 1781 * conditionalized if any buggy AHCI controllers are 1782 * encountered. 1783 */ 1784 pi.flags |= ATA_FLAG_FPDMA_AUX; 1785 } 1786 1787 if (hpriv->cap & HOST_CAP_PMP) 1788 pi.flags |= ATA_FLAG_PMP; 1789 1790 ahci_set_em_messages(hpriv, &pi); 1791 1792 if (ahci_broken_system_poweroff(pdev)) { 1793 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1794 dev_info(&pdev->dev, 1795 "quirky BIOS, skipping spindown on poweroff\n"); 1796 } 1797 1798 if (ahci_broken_lpm(pdev)) { 1799 pi.flags |= ATA_FLAG_NO_LPM; 1800 dev_warn(&pdev->dev, 1801 "BIOS update required for Link Power Management support\n"); 1802 } 1803 1804 if (ahci_broken_suspend(pdev)) { 1805 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1806 dev_warn(&pdev->dev, 1807 "BIOS update required for suspend/resume\n"); 1808 } 1809 1810 if (ahci_broken_online(pdev)) { 1811 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1812 dev_info(&pdev->dev, 1813 "online status unreliable, applying workaround\n"); 1814 } 1815 1816 1817 /* Acer SA5-271 workaround modifies private_data */ 1818 acer_sa5_271_workaround(hpriv, pdev); 1819 1820 /* CAP.NP sometimes indicate the index of the last enabled 1821 * port, at other times, that of the last possible port, so 1822 * determining the maximum port number requires looking at 1823 * both CAP.NP and port_map. 1824 */ 1825 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1826 1827 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1828 if (!host) 1829 return -ENOMEM; 1830 host->private_data = hpriv; 1831 1832 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { 1833 /* legacy intx interrupts */ 1834 pci_intx(pdev, 1); 1835 } 1836 hpriv->irq = pci_irq_vector(pdev, 0); 1837 1838 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1839 host->flags |= ATA_HOST_PARALLEL_SCAN; 1840 else 1841 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1842 1843 if (pi.flags & ATA_FLAG_EM) 1844 ahci_reset_em(host); 1845 1846 for (i = 0; i < host->n_ports; i++) { 1847 struct ata_port *ap = host->ports[i]; 1848 1849 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1850 ata_port_pbar_desc(ap, ahci_pci_bar, 1851 0x100 + ap->port_no * 0x80, "port"); 1852 1853 /* set enclosure management message type */ 1854 if (ap->flags & ATA_FLAG_EM) 1855 ap->em_message_type = hpriv->em_msg_type; 1856 1857 ahci_update_initial_lpm_policy(ap, hpriv); 1858 1859 /* disabled/not-implemented port */ 1860 if (!(hpriv->port_map & (1 << i))) 1861 ap->ops = &ata_dummy_port_ops; 1862 } 1863 1864 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1865 ahci_p5wdh_workaround(host); 1866 1867 /* apply gtf filter quirk */ 1868 ahci_gtf_filter_workaround(host); 1869 1870 /* initialize adapter */ 1871 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 1872 if (rc) 1873 return rc; 1874 1875 rc = ahci_reset_controller(host); 1876 if (rc) 1877 return rc; 1878 1879 ahci_pci_init_controller(host); 1880 ahci_pci_print_info(host); 1881 1882 pci_set_master(pdev); 1883 1884 rc = ahci_host_activate(host, &ahci_sht); 1885 if (rc) 1886 return rc; 1887 1888 pm_runtime_put_noidle(&pdev->dev); 1889 return 0; 1890 } 1891 1892 static void ahci_shutdown_one(struct pci_dev *pdev) 1893 { 1894 ata_pci_shutdown_one(pdev); 1895 } 1896 1897 static void ahci_remove_one(struct pci_dev *pdev) 1898 { 1899 pm_runtime_get_noresume(&pdev->dev); 1900 ata_pci_remove_one(pdev); 1901 } 1902 1903 module_pci_driver(ahci_pci_driver); 1904 1905 MODULE_AUTHOR("Jeff Garzik"); 1906 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1907 MODULE_LICENSE("GPL"); 1908 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1909 MODULE_VERSION(DRV_VERSION); 1910