1 // SPDX-License-Identifier: GPL-2.0-or-later 2 3 /* 4 * acard-ahci.c - ACard AHCI SATA support 5 * 6 * Maintained by: Tejun Heo <tj@kernel.org> 7 * Please ALWAYS copy linux-ide@vger.kernel.org 8 * on emails. 9 * 10 * Copyright 2010 Red Hat, Inc. 11 * 12 * libata documentation is available via 'make {ps|pdf}docs', 13 * as Documentation/driver-api/libata.rst 14 * 15 * AHCI hardware documentation: 16 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 17 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/pci.h> 23 #include <linux/blkdev.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/device.h> 28 #include <linux/dmi.h> 29 #include <linux/gfp.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_cmnd.h> 32 #include <linux/libata.h> 33 #include "ahci.h" 34 35 #define DRV_NAME "acard-ahci" 36 #define DRV_VERSION "1.0" 37 38 /* 39 Received FIS structure limited to 80h. 40 */ 41 42 #define ACARD_AHCI_RX_FIS_SZ 128 43 44 enum { 45 AHCI_PCI_BAR = 5, 46 }; 47 48 enum board_ids { 49 board_acard_ahci, 50 }; 51 52 struct acard_sg { 53 __le32 addr; 54 __le32 addr_hi; 55 __le32 reserved; 56 __le32 size; /* bit 31 (EOT) max==0x10000 (64k) */ 57 }; 58 59 static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc); 60 static void acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 61 static int acard_ahci_port_start(struct ata_port *ap); 62 static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 63 64 #ifdef CONFIG_PM_SLEEP 65 static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 66 static int acard_ahci_pci_device_resume(struct pci_dev *pdev); 67 #endif 68 69 static const struct scsi_host_template acard_ahci_sht = { 70 AHCI_SHT("acard-ahci"), 71 }; 72 73 static struct ata_port_operations acard_ops = { 74 .inherits = &ahci_ops, 75 .qc_prep = acard_ahci_qc_prep, 76 .qc_fill_rtf = acard_ahci_qc_fill_rtf, 77 .port_start = acard_ahci_port_start, 78 }; 79 80 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) 81 82 static const struct ata_port_info acard_ahci_port_info[] = { 83 [board_acard_ahci] = 84 { 85 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 86 .flags = AHCI_FLAG_COMMON, 87 .pio_mask = ATA_PIO4, 88 .udma_mask = ATA_UDMA6, 89 .port_ops = &acard_ops, 90 }, 91 }; 92 93 static const struct pci_device_id acard_ahci_pci_tbl[] = { 94 { 95 /* ACard ATP8620 */ 96 PCI_VDEVICE(ARTOP, 0x000d), 97 .driver_data = board_acard_ahci, 98 }, 99 { } /* terminate list */ 100 }; 101 102 static struct pci_driver acard_ahci_pci_driver = { 103 .name = DRV_NAME, 104 .id_table = acard_ahci_pci_tbl, 105 .probe = acard_ahci_init_one, 106 .remove = ata_pci_remove_one, 107 #ifdef CONFIG_PM_SLEEP 108 .suspend = acard_ahci_pci_device_suspend, 109 .resume = acard_ahci_pci_device_resume, 110 #endif 111 }; 112 113 #ifdef CONFIG_PM_SLEEP 114 static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 115 { 116 struct ata_host *host = pci_get_drvdata(pdev); 117 struct ahci_host_priv *hpriv = host->private_data; 118 void __iomem *mmio = hpriv->mmio; 119 u32 ctl; 120 121 if (mesg.event & PM_EVENT_SUSPEND && 122 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 123 dev_err(&pdev->dev, 124 "BIOS update required for suspend/resume\n"); 125 return -EIO; 126 } 127 128 if (mesg.event & PM_EVENT_SLEEP) { 129 /* AHCI spec rev1.1 section 8.3.3: 130 * Software must disable interrupts prior to requesting a 131 * transition of the HBA to D3 state. 132 */ 133 ctl = readl(mmio + HOST_CTL); 134 ctl &= ~HOST_IRQ_EN; 135 writel(ctl, mmio + HOST_CTL); 136 readl(mmio + HOST_CTL); /* flush */ 137 } 138 139 return ata_pci_device_suspend(pdev, mesg); 140 } 141 142 static int acard_ahci_pci_device_resume(struct pci_dev *pdev) 143 { 144 struct ata_host *host = pci_get_drvdata(pdev); 145 int rc; 146 147 rc = ata_pci_device_do_resume(pdev); 148 if (rc) 149 return rc; 150 151 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 152 rc = ahci_reset_controller(host); 153 if (rc) 154 return rc; 155 156 ahci_init_controller(host); 157 } 158 159 ata_host_resume(host); 160 161 return 0; 162 } 163 #endif 164 165 static void acard_ahci_pci_print_info(struct ata_host *host) 166 { 167 struct pci_dev *pdev = to_pci_dev(host->dev); 168 u16 cc; 169 const char *scc_s; 170 171 pci_read_config_word(pdev, 0x0a, &cc); 172 if (cc == PCI_CLASS_STORAGE_IDE) 173 scc_s = "IDE"; 174 else if (cc == PCI_CLASS_STORAGE_SATA) 175 scc_s = "SATA"; 176 else if (cc == PCI_CLASS_STORAGE_RAID) 177 scc_s = "RAID"; 178 else 179 scc_s = "unknown"; 180 181 ahci_print_info(host, scc_s); 182 } 183 184 static unsigned int acard_ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 185 { 186 struct scatterlist *sg; 187 struct acard_sg *acard_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 188 unsigned int si, last_si = 0; 189 190 /* 191 * Next, the S/G list. 192 */ 193 for_each_sg(qc->sg, sg, qc->n_elem, si) { 194 dma_addr_t addr = sg_dma_address(sg); 195 u32 sg_len = sg_dma_len(sg); 196 197 /* 198 * ACard note: 199 * We must set an end-of-table (EOT) bit, 200 * and the segment cannot exceed 64k (0x10000) 201 */ 202 acard_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 203 acard_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 204 acard_sg[si].size = cpu_to_le32(sg_len); 205 last_si = si; 206 } 207 208 acard_sg[last_si].size |= cpu_to_le32(1 << 31); /* set EOT */ 209 210 return si; 211 } 212 213 static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc) 214 { 215 struct ata_port *ap = qc->ap; 216 struct ahci_port_priv *pp = ap->private_data; 217 int is_atapi = ata_is_atapi(qc->tf.protocol); 218 void *cmd_tbl; 219 u32 opts; 220 const u32 cmd_fis_len = 5; /* five dwords */ 221 222 /* 223 * Fill in command table information. First, the header, 224 * a SATA Register - Host to Device command FIS. 225 */ 226 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ; 227 228 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 229 if (is_atapi) { 230 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 231 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 232 } 233 234 if (qc->flags & ATA_QCFLAG_DMAMAP) 235 acard_ahci_fill_sg(qc, cmd_tbl); 236 237 /* 238 * Fill in command slot information. 239 * 240 * ACard note: prd table length not filled in 241 */ 242 opts = cmd_fis_len | (qc->dev->link->pmp << 12); 243 if (qc->tf.flags & ATA_TFLAG_WRITE) 244 opts |= AHCI_CMD_WRITE; 245 if (is_atapi) 246 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 247 248 ahci_fill_cmd_slot(pp, qc->hw_tag, opts); 249 250 return AC_ERR_OK; 251 } 252 253 static void acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 254 { 255 struct ahci_port_priv *pp = qc->ap->private_data; 256 u8 *rx_fis = pp->rx_fis; 257 258 if (pp->fbs_enabled) 259 rx_fis += qc->dev->link->pmp * ACARD_AHCI_RX_FIS_SZ; 260 261 /* 262 * After a successful execution of an ATA PIO data-in command, 263 * the device doesn't send D2H Reg FIS to update the TF and 264 * the host should take TF and E_Status from the preceding PIO 265 * Setup FIS. 266 */ 267 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 268 !(qc->flags & ATA_QCFLAG_EH)) { 269 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 270 qc->result_tf.status = (rx_fis + RX_FIS_PIO_SETUP)[15]; 271 } else 272 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 273 } 274 275 static int acard_ahci_port_start(struct ata_port *ap) 276 { 277 struct ahci_host_priv *hpriv = ap->host->private_data; 278 struct device *dev = ap->host->dev; 279 struct ahci_port_priv *pp; 280 void *mem; 281 dma_addr_t mem_dma; 282 size_t dma_sz, rx_fis_sz; 283 284 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 285 if (!pp) 286 return -ENOMEM; 287 288 /* check FBS capability */ 289 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 290 void __iomem *port_mmio = ahci_port_base(ap); 291 u32 cmd = readl(port_mmio + PORT_CMD); 292 if (cmd & PORT_CMD_FBSCP) 293 pp->fbs_supported = true; 294 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 295 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 296 ap->port_no); 297 pp->fbs_supported = true; 298 } else 299 dev_warn(dev, "port %d is not capable of FBS\n", 300 ap->port_no); 301 } 302 303 if (pp->fbs_supported) { 304 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 305 rx_fis_sz = ACARD_AHCI_RX_FIS_SZ * 16; 306 } else { 307 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 308 rx_fis_sz = ACARD_AHCI_RX_FIS_SZ; 309 } 310 311 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 312 if (!mem) 313 return -ENOMEM; 314 315 /* 316 * First item in chunk of DMA memory: 32-slot command table, 317 * 32 bytes each in size 318 */ 319 pp->cmd_slot = mem; 320 pp->cmd_slot_dma = mem_dma; 321 322 mem += AHCI_CMD_SLOT_SZ; 323 mem_dma += AHCI_CMD_SLOT_SZ; 324 325 /* 326 * Second item: Received-FIS area 327 */ 328 pp->rx_fis = mem; 329 pp->rx_fis_dma = mem_dma; 330 331 mem += rx_fis_sz; 332 mem_dma += rx_fis_sz; 333 334 /* 335 * Third item: data area for storing a single command 336 * and its scatter-gather table 337 */ 338 pp->cmd_tbl = mem; 339 pp->cmd_tbl_dma = mem_dma; 340 341 /* 342 * Save off initial list of interrupts to be enabled. 343 * This could be changed later 344 */ 345 pp->intr_mask = DEF_PORT_IRQ; 346 347 ap->private_data = pp; 348 349 /* engage engines, captain */ 350 return ahci_port_resume(ap); 351 } 352 353 static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 354 { 355 unsigned int board_id = ent->driver_data; 356 struct ata_port_info pi = acard_ahci_port_info[board_id]; 357 const struct ata_port_info *ppi[] = { &pi, NULL }; 358 struct device *dev = &pdev->dev; 359 struct ahci_host_priv *hpriv; 360 struct ata_host *host; 361 int n_ports, i, rc; 362 363 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 364 365 ata_print_version_once(&pdev->dev, DRV_VERSION); 366 367 /* acquire resources */ 368 rc = pcim_enable_device(pdev); 369 if (rc) 370 return rc; 371 372 /* AHCI controllers often implement SFF compatible interface. 373 * Grab all PCI BARs just in case. 374 */ 375 rc = pcim_request_all_regions(pdev, DRV_NAME); 376 if (rc == -EBUSY) 377 pcim_pin_device(pdev); 378 if (rc) 379 return rc; 380 381 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 382 if (!hpriv) 383 return -ENOMEM; 384 385 hpriv->irq = pdev->irq; 386 hpriv->flags |= (unsigned long)pi.private_data; 387 388 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) 389 pci_enable_msi(pdev); 390 391 hpriv->mmio = pcim_iomap(pdev, AHCI_PCI_BAR, 0); 392 if (!hpriv->mmio) 393 return -ENOMEM; 394 395 /* save initial config */ 396 ahci_save_initial_config(&pdev->dev, hpriv); 397 398 /* prepare host */ 399 if (hpriv->cap & HOST_CAP_NCQ) 400 pi.flags |= ATA_FLAG_NCQ; 401 402 if (hpriv->cap & HOST_CAP_PMP) 403 pi.flags |= ATA_FLAG_PMP; 404 405 ahci_set_em_messages(hpriv, &pi); 406 407 /* CAP.NP sometimes indicate the index of the last enabled 408 * port, at other times, that of the last possible port, so 409 * determining the maximum port number requires looking at 410 * both CAP.NP and port_map. 411 */ 412 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 413 414 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 415 if (!host) 416 return -ENOMEM; 417 host->private_data = hpriv; 418 419 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 420 host->flags |= ATA_HOST_PARALLEL_SCAN; 421 else 422 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n"); 423 424 for (i = 0; i < host->n_ports; i++) { 425 struct ata_port *ap = host->ports[i]; 426 427 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); 428 ata_port_pbar_desc(ap, AHCI_PCI_BAR, 429 0x100 + ap->port_no * 0x80, "port"); 430 431 /* set initial link pm policy */ 432 /* 433 ap->pm_policy = NOT_AVAILABLE; 434 */ 435 /* disabled/not-implemented port */ 436 if (!(hpriv->port_map & (1 << i))) 437 ap->ops = &ata_dummy_port_ops; 438 } 439 440 /* initialize adapter */ 441 rc = dma_set_mask_and_coherent(&pdev->dev, 442 DMA_BIT_MASK((hpriv->cap & HOST_CAP_64) ? 64 : 32)); 443 if (rc) { 444 dev_err(&pdev->dev, "DMA enable failed\n"); 445 return rc; 446 } 447 448 rc = ahci_reset_controller(host); 449 if (rc) 450 return rc; 451 452 ahci_init_controller(host); 453 acard_ahci_pci_print_info(host); 454 455 pci_set_master(pdev); 456 return ahci_host_activate(host, &acard_ahci_sht); 457 } 458 459 module_pci_driver(acard_ahci_pci_driver); 460 461 MODULE_AUTHOR("Jeff Garzik"); 462 MODULE_DESCRIPTION("ACard AHCI SATA low-level driver"); 463 MODULE_LICENSE("GPL"); 464 MODULE_DEVICE_TABLE(pci, acard_ahci_pci_tbl); 465 MODULE_VERSION(DRV_VERSION); 466