1 /* 2 * processor_idle - idle state submodule to the ACPI processor driver 3 * 4 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> 5 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 6 * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> 7 * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> 8 * - Added processor hotplug support 9 * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> 10 * - Added support for C3 on SMP 11 * 12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or (at 17 * your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, but 20 * WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 22 * General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License along 25 * with this program; if not, write to the Free Software Foundation, Inc., 26 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. 27 * 28 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 29 */ 30 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/init.h> 34 #include <linux/cpufreq.h> 35 #include <linux/proc_fs.h> 36 #include <linux/seq_file.h> 37 #include <linux/acpi.h> 38 #include <linux/dmi.h> 39 #include <linux/moduleparam.h> 40 #include <linux/sched.h> /* need_resched() */ 41 #include <linux/pm_qos_params.h> 42 #include <linux/clockchips.h> 43 #include <linux/cpuidle.h> 44 45 /* 46 * Include the apic definitions for x86 to have the APIC timer related defines 47 * available also for UP (on SMP it gets magically included via linux/smp.h). 48 * asm/acpi.h is not an option, as it would require more include magic. Also 49 * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. 50 */ 51 #ifdef CONFIG_X86 52 #include <asm/apic.h> 53 #endif 54 55 #include <asm/io.h> 56 #include <asm/uaccess.h> 57 58 #include <acpi/acpi_bus.h> 59 #include <acpi/processor.h> 60 61 #define ACPI_PROCESSOR_COMPONENT 0x01000000 62 #define ACPI_PROCESSOR_CLASS "processor" 63 #define _COMPONENT ACPI_PROCESSOR_COMPONENT 64 ACPI_MODULE_NAME("processor_idle"); 65 #define ACPI_PROCESSOR_FILE_POWER "power" 66 #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000) 67 #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) 68 #ifndef CONFIG_CPU_IDLE 69 #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */ 70 #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */ 71 static void (*pm_idle_save) (void) __read_mostly; 72 #else 73 #define C2_OVERHEAD 1 /* 1us */ 74 #define C3_OVERHEAD 1 /* 1us */ 75 #endif 76 #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) 77 78 static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; 79 #ifdef CONFIG_CPU_IDLE 80 module_param(max_cstate, uint, 0000); 81 #else 82 module_param(max_cstate, uint, 0644); 83 #endif 84 static unsigned int nocst __read_mostly; 85 module_param(nocst, uint, 0000); 86 87 #ifndef CONFIG_CPU_IDLE 88 /* 89 * bm_history -- bit-mask with a bit per jiffy of bus-master activity 90 * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms 91 * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms 92 * 100 HZ: 0x0000000F: 4 jiffies = 40ms 93 * reduce history for more aggressive entry into C3 94 */ 95 static unsigned int bm_history __read_mostly = 96 (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1)); 97 module_param(bm_history, uint, 0644); 98 99 static int acpi_processor_set_power_policy(struct acpi_processor *pr); 100 101 #else /* CONFIG_CPU_IDLE */ 102 static unsigned int latency_factor __read_mostly = 2; 103 module_param(latency_factor, uint, 0644); 104 #endif 105 106 /* 107 * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. 108 * For now disable this. Probably a bug somewhere else. 109 * 110 * To skip this limit, boot/load with a large max_cstate limit. 111 */ 112 static int set_max_cstate(const struct dmi_system_id *id) 113 { 114 if (max_cstate > ACPI_PROCESSOR_MAX_POWER) 115 return 0; 116 117 printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." 118 " Override with \"processor.max_cstate=%d\"\n", id->ident, 119 (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); 120 121 max_cstate = (long)id->driver_data; 122 123 return 0; 124 } 125 126 /* Actually this shouldn't be __cpuinitdata, would be better to fix the 127 callers to only run once -AK */ 128 static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { 129 { set_max_cstate, "IBM ThinkPad R40e", { 130 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 131 DMI_MATCH(DMI_BIOS_VERSION,"1SET70WW")}, (void *)1}, 132 { set_max_cstate, "IBM ThinkPad R40e", { 133 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 134 DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1}, 135 { set_max_cstate, "IBM ThinkPad R40e", { 136 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 137 DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1}, 138 { set_max_cstate, "IBM ThinkPad R40e", { 139 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 140 DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1}, 141 { set_max_cstate, "IBM ThinkPad R40e", { 142 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 143 DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1}, 144 { set_max_cstate, "IBM ThinkPad R40e", { 145 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 146 DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1}, 147 { set_max_cstate, "IBM ThinkPad R40e", { 148 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 149 DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1}, 150 { set_max_cstate, "IBM ThinkPad R40e", { 151 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 152 DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1}, 153 { set_max_cstate, "IBM ThinkPad R40e", { 154 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 155 DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1}, 156 { set_max_cstate, "IBM ThinkPad R40e", { 157 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 158 DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1}, 159 { set_max_cstate, "IBM ThinkPad R40e", { 160 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 161 DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1}, 162 { set_max_cstate, "IBM ThinkPad R40e", { 163 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 164 DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1}, 165 { set_max_cstate, "IBM ThinkPad R40e", { 166 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 167 DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1}, 168 { set_max_cstate, "IBM ThinkPad R40e", { 169 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 170 DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1}, 171 { set_max_cstate, "IBM ThinkPad R40e", { 172 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 173 DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1}, 174 { set_max_cstate, "IBM ThinkPad R40e", { 175 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), 176 DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1}, 177 { set_max_cstate, "Medion 41700", { 178 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), 179 DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1}, 180 { set_max_cstate, "Clevo 5600D", { 181 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), 182 DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, 183 (void *)2}, 184 {}, 185 }; 186 187 static inline u32 ticks_elapsed(u32 t1, u32 t2) 188 { 189 if (t2 >= t1) 190 return (t2 - t1); 191 else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) 192 return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); 193 else 194 return ((0xFFFFFFFF - t1) + t2); 195 } 196 197 static inline u32 ticks_elapsed_in_us(u32 t1, u32 t2) 198 { 199 if (t2 >= t1) 200 return PM_TIMER_TICKS_TO_US(t2 - t1); 201 else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) 202 return PM_TIMER_TICKS_TO_US(((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); 203 else 204 return PM_TIMER_TICKS_TO_US((0xFFFFFFFF - t1) + t2); 205 } 206 207 /* 208 * Callers should disable interrupts before the call and enable 209 * interrupts after return. 210 */ 211 static void acpi_safe_halt(void) 212 { 213 current_thread_info()->status &= ~TS_POLLING; 214 /* 215 * TS_POLLING-cleared state must be visible before we 216 * test NEED_RESCHED: 217 */ 218 smp_mb(); 219 if (!need_resched()) { 220 safe_halt(); 221 local_irq_disable(); 222 } 223 current_thread_info()->status |= TS_POLLING; 224 } 225 226 #ifndef CONFIG_CPU_IDLE 227 228 static void 229 acpi_processor_power_activate(struct acpi_processor *pr, 230 struct acpi_processor_cx *new) 231 { 232 struct acpi_processor_cx *old; 233 234 if (!pr || !new) 235 return; 236 237 old = pr->power.state; 238 239 if (old) 240 old->promotion.count = 0; 241 new->demotion.count = 0; 242 243 /* Cleanup from old state. */ 244 if (old) { 245 switch (old->type) { 246 case ACPI_STATE_C3: 247 /* Disable bus master reload */ 248 if (new->type != ACPI_STATE_C3 && pr->flags.bm_check) 249 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); 250 break; 251 } 252 } 253 254 /* Prepare to use new state. */ 255 switch (new->type) { 256 case ACPI_STATE_C3: 257 /* Enable bus master reload */ 258 if (old->type != ACPI_STATE_C3 && pr->flags.bm_check) 259 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); 260 break; 261 } 262 263 pr->power.state = new; 264 265 return; 266 } 267 268 static atomic_t c3_cpu_count; 269 270 /* Common C-state entry for C2, C3, .. */ 271 static void acpi_cstate_enter(struct acpi_processor_cx *cstate) 272 { 273 if (cstate->entry_method == ACPI_CSTATE_FFH) { 274 /* Call into architectural FFH based C-state */ 275 acpi_processor_ffh_cstate_enter(cstate); 276 } else { 277 int unused; 278 /* IO port based C-state */ 279 inb(cstate->address); 280 /* Dummy wait op - must do something useless after P_LVL2 read 281 because chipsets cannot guarantee that STPCLK# signal 282 gets asserted in time to freeze execution properly. */ 283 unused = inl(acpi_gbl_FADT.xpm_timer_block.address); 284 } 285 } 286 #endif /* !CONFIG_CPU_IDLE */ 287 288 #ifdef ARCH_APICTIMER_STOPS_ON_C3 289 290 /* 291 * Some BIOS implementations switch to C3 in the published C2 state. 292 * This seems to be a common problem on AMD boxen, but other vendors 293 * are affected too. We pick the most conservative approach: we assume 294 * that the local APIC stops in both C2 and C3. 295 */ 296 static void acpi_timer_check_state(int state, struct acpi_processor *pr, 297 struct acpi_processor_cx *cx) 298 { 299 struct acpi_processor_power *pwr = &pr->power; 300 u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; 301 302 /* 303 * Check, if one of the previous states already marked the lapic 304 * unstable 305 */ 306 if (pwr->timer_broadcast_on_state < state) 307 return; 308 309 if (cx->type >= type) 310 pr->power.timer_broadcast_on_state = state; 311 } 312 313 static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) 314 { 315 unsigned long reason; 316 317 reason = pr->power.timer_broadcast_on_state < INT_MAX ? 318 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; 319 320 clockevents_notify(reason, &pr->id); 321 } 322 323 /* Power(C) State timer broadcast control */ 324 static void acpi_state_timer_broadcast(struct acpi_processor *pr, 325 struct acpi_processor_cx *cx, 326 int broadcast) 327 { 328 int state = cx - pr->power.states; 329 330 if (state >= pr->power.timer_broadcast_on_state) { 331 unsigned long reason; 332 333 reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : 334 CLOCK_EVT_NOTIFY_BROADCAST_EXIT; 335 clockevents_notify(reason, &pr->id); 336 } 337 } 338 339 #else 340 341 static void acpi_timer_check_state(int state, struct acpi_processor *pr, 342 struct acpi_processor_cx *cstate) { } 343 static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { } 344 static void acpi_state_timer_broadcast(struct acpi_processor *pr, 345 struct acpi_processor_cx *cx, 346 int broadcast) 347 { 348 } 349 350 #endif 351 352 /* 353 * Suspend / resume control 354 */ 355 static int acpi_idle_suspend; 356 357 int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) 358 { 359 acpi_idle_suspend = 1; 360 return 0; 361 } 362 363 int acpi_processor_resume(struct acpi_device * device) 364 { 365 acpi_idle_suspend = 0; 366 return 0; 367 } 368 369 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) 370 static int tsc_halts_in_c(int state) 371 { 372 switch (boot_cpu_data.x86_vendor) { 373 case X86_VENDOR_AMD: 374 /* 375 * AMD Fam10h TSC will tick in all 376 * C/P/S0/S1 states when this bit is set. 377 */ 378 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 379 return 0; 380 /*FALL THROUGH*/ 381 case X86_VENDOR_INTEL: 382 /* Several cases known where TSC halts in C2 too */ 383 default: 384 return state > ACPI_STATE_C1; 385 } 386 } 387 #endif 388 389 #ifndef CONFIG_CPU_IDLE 390 static void acpi_processor_idle(void) 391 { 392 struct acpi_processor *pr = NULL; 393 struct acpi_processor_cx *cx = NULL; 394 struct acpi_processor_cx *next_state = NULL; 395 int sleep_ticks = 0; 396 u32 t1, t2 = 0; 397 398 /* 399 * Interrupts must be disabled during bus mastering calculations and 400 * for C2/C3 transitions. 401 */ 402 local_irq_disable(); 403 404 pr = processors[smp_processor_id()]; 405 if (!pr) { 406 local_irq_enable(); 407 return; 408 } 409 410 /* 411 * Check whether we truly need to go idle, or should 412 * reschedule: 413 */ 414 if (unlikely(need_resched())) { 415 local_irq_enable(); 416 return; 417 } 418 419 cx = pr->power.state; 420 if (!cx || acpi_idle_suspend) { 421 if (pm_idle_save) { 422 pm_idle_save(); /* enables IRQs */ 423 } else { 424 acpi_safe_halt(); 425 local_irq_enable(); 426 } 427 428 return; 429 } 430 431 /* 432 * Check BM Activity 433 * ----------------- 434 * Check for bus mastering activity (if required), record, and check 435 * for demotion. 436 */ 437 if (pr->flags.bm_check) { 438 u32 bm_status = 0; 439 unsigned long diff = jiffies - pr->power.bm_check_timestamp; 440 441 if (diff > 31) 442 diff = 31; 443 444 pr->power.bm_activity <<= diff; 445 446 acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); 447 if (bm_status) { 448 pr->power.bm_activity |= 0x1; 449 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); 450 } 451 /* 452 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect 453 * the true state of bus mastering activity; forcing us to 454 * manually check the BMIDEA bit of each IDE channel. 455 */ 456 else if (errata.piix4.bmisx) { 457 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) 458 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) 459 pr->power.bm_activity |= 0x1; 460 } 461 462 pr->power.bm_check_timestamp = jiffies; 463 464 /* 465 * If bus mastering is or was active this jiffy, demote 466 * to avoid a faulty transition. Note that the processor 467 * won't enter a low-power state during this call (to this 468 * function) but should upon the next. 469 * 470 * TBD: A better policy might be to fallback to the demotion 471 * state (use it for this quantum only) istead of 472 * demoting -- and rely on duration as our sole demotion 473 * qualification. This may, however, introduce DMA 474 * issues (e.g. floppy DMA transfer overrun/underrun). 475 */ 476 if ((pr->power.bm_activity & 0x1) && 477 cx->demotion.threshold.bm) { 478 local_irq_enable(); 479 next_state = cx->demotion.state; 480 goto end; 481 } 482 } 483 484 #ifdef CONFIG_HOTPLUG_CPU 485 /* 486 * Check for P_LVL2_UP flag before entering C2 and above on 487 * an SMP system. We do it here instead of doing it at _CST/P_LVL 488 * detection phase, to work cleanly with logical CPU hotplug. 489 */ 490 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && 491 !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) 492 cx = &pr->power.states[ACPI_STATE_C1]; 493 #endif 494 495 /* 496 * Sleep: 497 * ------ 498 * Invoke the current Cx state to put the processor to sleep. 499 */ 500 if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) { 501 current_thread_info()->status &= ~TS_POLLING; 502 /* 503 * TS_POLLING-cleared state must be visible before we 504 * test NEED_RESCHED: 505 */ 506 smp_mb(); 507 if (need_resched()) { 508 current_thread_info()->status |= TS_POLLING; 509 local_irq_enable(); 510 return; 511 } 512 } 513 514 switch (cx->type) { 515 516 case ACPI_STATE_C1: 517 /* 518 * Invoke C1. 519 * Use the appropriate idle routine, the one that would 520 * be used without acpi C-states. 521 */ 522 if (pm_idle_save) { 523 pm_idle_save(); /* enables IRQs */ 524 } else { 525 acpi_safe_halt(); 526 local_irq_enable(); 527 } 528 529 /* 530 * TBD: Can't get time duration while in C1, as resumes 531 * go to an ISR rather than here. Need to instrument 532 * base interrupt handler. 533 * 534 * Note: the TSC better not stop in C1, sched_clock() will 535 * skew otherwise. 536 */ 537 sleep_ticks = 0xFFFFFFFF; 538 539 break; 540 541 case ACPI_STATE_C2: 542 /* Get start time (ticks) */ 543 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); 544 /* Tell the scheduler that we are going deep-idle: */ 545 sched_clock_idle_sleep_event(); 546 /* Invoke C2 */ 547 acpi_state_timer_broadcast(pr, cx, 1); 548 acpi_cstate_enter(cx); 549 /* Get end time (ticks) */ 550 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); 551 552 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) 553 /* TSC halts in C2, so notify users */ 554 if (tsc_halts_in_c(ACPI_STATE_C2)) 555 mark_tsc_unstable("possible TSC halt in C2"); 556 #endif 557 /* Compute time (ticks) that we were actually asleep */ 558 sleep_ticks = ticks_elapsed(t1, t2); 559 560 /* Tell the scheduler how much we idled: */ 561 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); 562 563 /* Re-enable interrupts */ 564 local_irq_enable(); 565 /* Do not account our idle-switching overhead: */ 566 sleep_ticks -= cx->latency_ticks + C2_OVERHEAD; 567 568 current_thread_info()->status |= TS_POLLING; 569 acpi_state_timer_broadcast(pr, cx, 0); 570 break; 571 572 case ACPI_STATE_C3: 573 acpi_unlazy_tlb(smp_processor_id()); 574 /* 575 * Must be done before busmaster disable as we might 576 * need to access HPET ! 577 */ 578 acpi_state_timer_broadcast(pr, cx, 1); 579 /* 580 * disable bus master 581 * bm_check implies we need ARB_DIS 582 * !bm_check implies we need cache flush 583 * bm_control implies whether we can do ARB_DIS 584 * 585 * That leaves a case where bm_check is set and bm_control is 586 * not set. In that case we cannot do much, we enter C3 587 * without doing anything. 588 */ 589 if (pr->flags.bm_check && pr->flags.bm_control) { 590 if (atomic_inc_return(&c3_cpu_count) == 591 num_online_cpus()) { 592 /* 593 * All CPUs are trying to go to C3 594 * Disable bus master arbitration 595 */ 596 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); 597 } 598 } else if (!pr->flags.bm_check) { 599 /* SMP with no shared cache... Invalidate cache */ 600 ACPI_FLUSH_CPU_CACHE(); 601 } 602 603 /* Get start time (ticks) */ 604 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); 605 /* Invoke C3 */ 606 /* Tell the scheduler that we are going deep-idle: */ 607 sched_clock_idle_sleep_event(); 608 acpi_cstate_enter(cx); 609 /* Get end time (ticks) */ 610 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); 611 if (pr->flags.bm_check && pr->flags.bm_control) { 612 /* Enable bus master arbitration */ 613 atomic_dec(&c3_cpu_count); 614 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); 615 } 616 617 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) 618 /* TSC halts in C3, so notify users */ 619 if (tsc_halts_in_c(ACPI_STATE_C3)) 620 mark_tsc_unstable("TSC halts in C3"); 621 #endif 622 /* Compute time (ticks) that we were actually asleep */ 623 sleep_ticks = ticks_elapsed(t1, t2); 624 /* Tell the scheduler how much we idled: */ 625 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); 626 627 /* Re-enable interrupts */ 628 local_irq_enable(); 629 /* Do not account our idle-switching overhead: */ 630 sleep_ticks -= cx->latency_ticks + C3_OVERHEAD; 631 632 current_thread_info()->status |= TS_POLLING; 633 acpi_state_timer_broadcast(pr, cx, 0); 634 break; 635 636 default: 637 local_irq_enable(); 638 return; 639 } 640 cx->usage++; 641 if ((cx->type != ACPI_STATE_C1) && (sleep_ticks > 0)) 642 cx->time += sleep_ticks; 643 644 next_state = pr->power.state; 645 646 #ifdef CONFIG_HOTPLUG_CPU 647 /* Don't do promotion/demotion */ 648 if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) && 649 !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) { 650 next_state = cx; 651 goto end; 652 } 653 #endif 654 655 /* 656 * Promotion? 657 * ---------- 658 * Track the number of longs (time asleep is greater than threshold) 659 * and promote when the count threshold is reached. Note that bus 660 * mastering activity may prevent promotions. 661 * Do not promote above max_cstate. 662 */ 663 if (cx->promotion.state && 664 ((cx->promotion.state - pr->power.states) <= max_cstate)) { 665 if (sleep_ticks > cx->promotion.threshold.ticks && 666 cx->promotion.state->latency <= 667 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) { 668 cx->promotion.count++; 669 cx->demotion.count = 0; 670 if (cx->promotion.count >= 671 cx->promotion.threshold.count) { 672 if (pr->flags.bm_check) { 673 if (! 674 (pr->power.bm_activity & cx-> 675 promotion.threshold.bm)) { 676 next_state = 677 cx->promotion.state; 678 goto end; 679 } 680 } else { 681 next_state = cx->promotion.state; 682 goto end; 683 } 684 } 685 } 686 } 687 688 /* 689 * Demotion? 690 * --------- 691 * Track the number of shorts (time asleep is less than time threshold) 692 * and demote when the usage threshold is reached. 693 */ 694 if (cx->demotion.state) { 695 if (sleep_ticks < cx->demotion.threshold.ticks) { 696 cx->demotion.count++; 697 cx->promotion.count = 0; 698 if (cx->demotion.count >= cx->demotion.threshold.count) { 699 next_state = cx->demotion.state; 700 goto end; 701 } 702 } 703 } 704 705 end: 706 /* 707 * Demote if current state exceeds max_cstate 708 * or if the latency of the current state is unacceptable 709 */ 710 if ((pr->power.state - pr->power.states) > max_cstate || 711 pr->power.state->latency > 712 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) { 713 if (cx->demotion.state) 714 next_state = cx->demotion.state; 715 } 716 717 /* 718 * New Cx State? 719 * ------------- 720 * If we're going to start using a new Cx state we must clean up 721 * from the previous and prepare to use the new. 722 */ 723 if (next_state != pr->power.state) 724 acpi_processor_power_activate(pr, next_state); 725 } 726 727 static int acpi_processor_set_power_policy(struct acpi_processor *pr) 728 { 729 unsigned int i; 730 unsigned int state_is_set = 0; 731 struct acpi_processor_cx *lower = NULL; 732 struct acpi_processor_cx *higher = NULL; 733 struct acpi_processor_cx *cx; 734 735 736 if (!pr) 737 return -EINVAL; 738 739 /* 740 * This function sets the default Cx state policy (OS idle handler). 741 * Our scheme is to promote quickly to C2 but more conservatively 742 * to C3. We're favoring C2 for its characteristics of low latency 743 * (quick response), good power savings, and ability to allow bus 744 * mastering activity. Note that the Cx state policy is completely 745 * customizable and can be altered dynamically. 746 */ 747 748 /* startup state */ 749 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { 750 cx = &pr->power.states[i]; 751 if (!cx->valid) 752 continue; 753 754 if (!state_is_set) 755 pr->power.state = cx; 756 state_is_set++; 757 break; 758 } 759 760 if (!state_is_set) 761 return -ENODEV; 762 763 /* demotion */ 764 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { 765 cx = &pr->power.states[i]; 766 if (!cx->valid) 767 continue; 768 769 if (lower) { 770 cx->demotion.state = lower; 771 cx->demotion.threshold.ticks = cx->latency_ticks; 772 cx->demotion.threshold.count = 1; 773 if (cx->type == ACPI_STATE_C3) 774 cx->demotion.threshold.bm = bm_history; 775 } 776 777 lower = cx; 778 } 779 780 /* promotion */ 781 for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) { 782 cx = &pr->power.states[i]; 783 if (!cx->valid) 784 continue; 785 786 if (higher) { 787 cx->promotion.state = higher; 788 cx->promotion.threshold.ticks = cx->latency_ticks; 789 if (cx->type >= ACPI_STATE_C2) 790 cx->promotion.threshold.count = 4; 791 else 792 cx->promotion.threshold.count = 10; 793 if (higher->type == ACPI_STATE_C3) 794 cx->promotion.threshold.bm = bm_history; 795 } 796 797 higher = cx; 798 } 799 800 return 0; 801 } 802 #endif /* !CONFIG_CPU_IDLE */ 803 804 static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) 805 { 806 807 if (!pr) 808 return -EINVAL; 809 810 if (!pr->pblk) 811 return -ENODEV; 812 813 /* if info is obtained from pblk/fadt, type equals state */ 814 pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; 815 pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; 816 817 #ifndef CONFIG_HOTPLUG_CPU 818 /* 819 * Check for P_LVL2_UP flag before entering C2 and above on 820 * an SMP system. 821 */ 822 if ((num_online_cpus() > 1) && 823 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) 824 return -ENODEV; 825 #endif 826 827 /* determine C2 and C3 address from pblk */ 828 pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; 829 pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; 830 831 /* determine latencies from FADT */ 832 pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; 833 pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; 834 835 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 836 "lvl2[0x%08x] lvl3[0x%08x]\n", 837 pr->power.states[ACPI_STATE_C2].address, 838 pr->power.states[ACPI_STATE_C3].address)); 839 840 return 0; 841 } 842 843 static int acpi_processor_get_power_info_default(struct acpi_processor *pr) 844 { 845 if (!pr->power.states[ACPI_STATE_C1].valid) { 846 /* set the first C-State to C1 */ 847 /* all processors need to support C1 */ 848 pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; 849 pr->power.states[ACPI_STATE_C1].valid = 1; 850 } 851 /* the C0 state only exists as a filler in our array */ 852 pr->power.states[ACPI_STATE_C0].valid = 1; 853 return 0; 854 } 855 856 static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) 857 { 858 acpi_status status = 0; 859 acpi_integer count; 860 int current_count; 861 int i; 862 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 863 union acpi_object *cst; 864 865 866 if (nocst) 867 return -ENODEV; 868 869 current_count = 0; 870 871 status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); 872 if (ACPI_FAILURE(status)) { 873 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); 874 return -ENODEV; 875 } 876 877 cst = buffer.pointer; 878 879 /* There must be at least 2 elements */ 880 if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { 881 printk(KERN_ERR PREFIX "not enough elements in _CST\n"); 882 status = -EFAULT; 883 goto end; 884 } 885 886 count = cst->package.elements[0].integer.value; 887 888 /* Validate number of power states. */ 889 if (count < 1 || count != cst->package.count - 1) { 890 printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); 891 status = -EFAULT; 892 goto end; 893 } 894 895 /* Tell driver that at least _CST is supported. */ 896 pr->flags.has_cst = 1; 897 898 for (i = 1; i <= count; i++) { 899 union acpi_object *element; 900 union acpi_object *obj; 901 struct acpi_power_register *reg; 902 struct acpi_processor_cx cx; 903 904 memset(&cx, 0, sizeof(cx)); 905 906 element = &(cst->package.elements[i]); 907 if (element->type != ACPI_TYPE_PACKAGE) 908 continue; 909 910 if (element->package.count != 4) 911 continue; 912 913 obj = &(element->package.elements[0]); 914 915 if (obj->type != ACPI_TYPE_BUFFER) 916 continue; 917 918 reg = (struct acpi_power_register *)obj->buffer.pointer; 919 920 if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && 921 (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) 922 continue; 923 924 /* There should be an easy way to extract an integer... */ 925 obj = &(element->package.elements[1]); 926 if (obj->type != ACPI_TYPE_INTEGER) 927 continue; 928 929 cx.type = obj->integer.value; 930 /* 931 * Some buggy BIOSes won't list C1 in _CST - 932 * Let acpi_processor_get_power_info_default() handle them later 933 */ 934 if (i == 1 && cx.type != ACPI_STATE_C1) 935 current_count++; 936 937 cx.address = reg->address; 938 cx.index = current_count + 1; 939 940 cx.entry_method = ACPI_CSTATE_SYSTEMIO; 941 if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { 942 if (acpi_processor_ffh_cstate_probe 943 (pr->id, &cx, reg) == 0) { 944 cx.entry_method = ACPI_CSTATE_FFH; 945 } else if (cx.type == ACPI_STATE_C1) { 946 /* 947 * C1 is a special case where FIXED_HARDWARE 948 * can be handled in non-MWAIT way as well. 949 * In that case, save this _CST entry info. 950 * Otherwise, ignore this info and continue. 951 */ 952 cx.entry_method = ACPI_CSTATE_HALT; 953 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); 954 } else { 955 continue; 956 } 957 } else { 958 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", 959 cx.address); 960 } 961 962 963 obj = &(element->package.elements[2]); 964 if (obj->type != ACPI_TYPE_INTEGER) 965 continue; 966 967 cx.latency = obj->integer.value; 968 969 obj = &(element->package.elements[3]); 970 if (obj->type != ACPI_TYPE_INTEGER) 971 continue; 972 973 cx.power = obj->integer.value; 974 975 current_count++; 976 memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); 977 978 /* 979 * We support total ACPI_PROCESSOR_MAX_POWER - 1 980 * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) 981 */ 982 if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { 983 printk(KERN_WARNING 984 "Limiting number of power states to max (%d)\n", 985 ACPI_PROCESSOR_MAX_POWER); 986 printk(KERN_WARNING 987 "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); 988 break; 989 } 990 } 991 992 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", 993 current_count)); 994 995 /* Validate number of power states discovered */ 996 if (current_count < 2) 997 status = -EFAULT; 998 999 end: 1000 kfree(buffer.pointer); 1001 1002 return status; 1003 } 1004 1005 static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx) 1006 { 1007 1008 if (!cx->address) 1009 return; 1010 1011 /* 1012 * C2 latency must be less than or equal to 100 1013 * microseconds. 1014 */ 1015 else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { 1016 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1017 "latency too large [%d]\n", cx->latency)); 1018 return; 1019 } 1020 1021 /* 1022 * Otherwise we've met all of our C2 requirements. 1023 * Normalize the C2 latency to expidite policy 1024 */ 1025 cx->valid = 1; 1026 1027 #ifndef CONFIG_CPU_IDLE 1028 cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); 1029 #else 1030 cx->latency_ticks = cx->latency; 1031 #endif 1032 1033 return; 1034 } 1035 1036 static void acpi_processor_power_verify_c3(struct acpi_processor *pr, 1037 struct acpi_processor_cx *cx) 1038 { 1039 static int bm_check_flag; 1040 1041 1042 if (!cx->address) 1043 return; 1044 1045 /* 1046 * C3 latency must be less than or equal to 1000 1047 * microseconds. 1048 */ 1049 else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { 1050 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1051 "latency too large [%d]\n", cx->latency)); 1052 return; 1053 } 1054 1055 /* 1056 * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) 1057 * DMA transfers are used by any ISA device to avoid livelock. 1058 * Note that we could disable Type-F DMA (as recommended by 1059 * the erratum), but this is known to disrupt certain ISA 1060 * devices thus we take the conservative approach. 1061 */ 1062 else if (errata.piix4.fdma) { 1063 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1064 "C3 not supported on PIIX4 with Type-F DMA\n")); 1065 return; 1066 } 1067 1068 /* All the logic here assumes flags.bm_check is same across all CPUs */ 1069 if (!bm_check_flag) { 1070 /* Determine whether bm_check is needed based on CPU */ 1071 acpi_processor_power_init_bm_check(&(pr->flags), pr->id); 1072 bm_check_flag = pr->flags.bm_check; 1073 } else { 1074 pr->flags.bm_check = bm_check_flag; 1075 } 1076 1077 if (pr->flags.bm_check) { 1078 if (!pr->flags.bm_control) { 1079 if (pr->flags.has_cst != 1) { 1080 /* bus mastering control is necessary */ 1081 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1082 "C3 support requires BM control\n")); 1083 return; 1084 } else { 1085 /* Here we enter C3 without bus mastering */ 1086 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1087 "C3 support without BM control\n")); 1088 } 1089 } 1090 } else { 1091 /* 1092 * WBINVD should be set in fadt, for C3 state to be 1093 * supported on when bm_check is not required. 1094 */ 1095 if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { 1096 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1097 "Cache invalidation should work properly" 1098 " for C3 to be enabled on SMP systems\n")); 1099 return; 1100 } 1101 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); 1102 } 1103 1104 /* 1105 * Otherwise we've met all of our C3 requirements. 1106 * Normalize the C3 latency to expidite policy. Enable 1107 * checking of bus mastering status (bm_check) so we can 1108 * use this in our C3 policy 1109 */ 1110 cx->valid = 1; 1111 1112 #ifndef CONFIG_CPU_IDLE 1113 cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); 1114 #else 1115 cx->latency_ticks = cx->latency; 1116 #endif 1117 1118 return; 1119 } 1120 1121 static int acpi_processor_power_verify(struct acpi_processor *pr) 1122 { 1123 unsigned int i; 1124 unsigned int working = 0; 1125 1126 pr->power.timer_broadcast_on_state = INT_MAX; 1127 1128 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { 1129 struct acpi_processor_cx *cx = &pr->power.states[i]; 1130 1131 switch (cx->type) { 1132 case ACPI_STATE_C1: 1133 cx->valid = 1; 1134 break; 1135 1136 case ACPI_STATE_C2: 1137 acpi_processor_power_verify_c2(cx); 1138 if (cx->valid) 1139 acpi_timer_check_state(i, pr, cx); 1140 break; 1141 1142 case ACPI_STATE_C3: 1143 acpi_processor_power_verify_c3(pr, cx); 1144 if (cx->valid) 1145 acpi_timer_check_state(i, pr, cx); 1146 break; 1147 } 1148 1149 if (cx->valid) 1150 working++; 1151 } 1152 1153 acpi_propagate_timer_broadcast(pr); 1154 1155 return (working); 1156 } 1157 1158 static int acpi_processor_get_power_info(struct acpi_processor *pr) 1159 { 1160 unsigned int i; 1161 int result; 1162 1163 1164 /* NOTE: the idle thread may not be running while calling 1165 * this function */ 1166 1167 /* Zero initialize all the C-states info. */ 1168 memset(pr->power.states, 0, sizeof(pr->power.states)); 1169 1170 result = acpi_processor_get_power_info_cst(pr); 1171 if (result == -ENODEV) 1172 result = acpi_processor_get_power_info_fadt(pr); 1173 1174 if (result) 1175 return result; 1176 1177 acpi_processor_get_power_info_default(pr); 1178 1179 pr->power.count = acpi_processor_power_verify(pr); 1180 1181 #ifndef CONFIG_CPU_IDLE 1182 /* 1183 * Set Default Policy 1184 * ------------------ 1185 * Now that we know which states are supported, set the default 1186 * policy. Note that this policy can be changed dynamically 1187 * (e.g. encourage deeper sleeps to conserve battery life when 1188 * not on AC). 1189 */ 1190 result = acpi_processor_set_power_policy(pr); 1191 if (result) 1192 return result; 1193 #endif 1194 1195 /* 1196 * if one state of type C2 or C3 is available, mark this 1197 * CPU as being "idle manageable" 1198 */ 1199 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { 1200 if (pr->power.states[i].valid) { 1201 pr->power.count = i; 1202 if (pr->power.states[i].type >= ACPI_STATE_C2) 1203 pr->flags.power = 1; 1204 } 1205 } 1206 1207 return 0; 1208 } 1209 1210 static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) 1211 { 1212 struct acpi_processor *pr = seq->private; 1213 unsigned int i; 1214 1215 1216 if (!pr) 1217 goto end; 1218 1219 seq_printf(seq, "active state: C%zd\n" 1220 "max_cstate: C%d\n" 1221 "bus master activity: %08x\n" 1222 "maximum allowed latency: %d usec\n", 1223 pr->power.state ? pr->power.state - pr->power.states : 0, 1224 max_cstate, (unsigned)pr->power.bm_activity, 1225 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)); 1226 1227 seq_puts(seq, "states:\n"); 1228 1229 for (i = 1; i <= pr->power.count; i++) { 1230 seq_printf(seq, " %cC%d: ", 1231 (&pr->power.states[i] == 1232 pr->power.state ? '*' : ' '), i); 1233 1234 if (!pr->power.states[i].valid) { 1235 seq_puts(seq, "<not supported>\n"); 1236 continue; 1237 } 1238 1239 switch (pr->power.states[i].type) { 1240 case ACPI_STATE_C1: 1241 seq_printf(seq, "type[C1] "); 1242 break; 1243 case ACPI_STATE_C2: 1244 seq_printf(seq, "type[C2] "); 1245 break; 1246 case ACPI_STATE_C3: 1247 seq_printf(seq, "type[C3] "); 1248 break; 1249 default: 1250 seq_printf(seq, "type[--] "); 1251 break; 1252 } 1253 1254 if (pr->power.states[i].promotion.state) 1255 seq_printf(seq, "promotion[C%zd] ", 1256 (pr->power.states[i].promotion.state - 1257 pr->power.states)); 1258 else 1259 seq_puts(seq, "promotion[--] "); 1260 1261 if (pr->power.states[i].demotion.state) 1262 seq_printf(seq, "demotion[C%zd] ", 1263 (pr->power.states[i].demotion.state - 1264 pr->power.states)); 1265 else 1266 seq_puts(seq, "demotion[--] "); 1267 1268 seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", 1269 pr->power.states[i].latency, 1270 pr->power.states[i].usage, 1271 (unsigned long long)pr->power.states[i].time); 1272 } 1273 1274 end: 1275 return 0; 1276 } 1277 1278 static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) 1279 { 1280 return single_open(file, acpi_processor_power_seq_show, 1281 PDE(inode)->data); 1282 } 1283 1284 static const struct file_operations acpi_processor_power_fops = { 1285 .owner = THIS_MODULE, 1286 .open = acpi_processor_power_open_fs, 1287 .read = seq_read, 1288 .llseek = seq_lseek, 1289 .release = single_release, 1290 }; 1291 1292 #ifndef CONFIG_CPU_IDLE 1293 1294 int acpi_processor_cst_has_changed(struct acpi_processor *pr) 1295 { 1296 int result = 0; 1297 1298 1299 if (!pr) 1300 return -EINVAL; 1301 1302 if (nocst) { 1303 return -ENODEV; 1304 } 1305 1306 if (!pr->flags.power_setup_done) 1307 return -ENODEV; 1308 1309 /* Fall back to the default idle loop */ 1310 pm_idle = pm_idle_save; 1311 synchronize_sched(); /* Relies on interrupts forcing exit from idle. */ 1312 1313 pr->flags.power = 0; 1314 result = acpi_processor_get_power_info(pr); 1315 if ((pr->flags.power == 1) && (pr->flags.power_setup_done)) 1316 pm_idle = acpi_processor_idle; 1317 1318 return result; 1319 } 1320 1321 #ifdef CONFIG_SMP 1322 static void smp_callback(void *v) 1323 { 1324 /* we already woke the CPU up, nothing more to do */ 1325 } 1326 1327 /* 1328 * This function gets called when a part of the kernel has a new latency 1329 * requirement. This means we need to get all processors out of their C-state, 1330 * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that 1331 * wakes them all right up. 1332 */ 1333 static int acpi_processor_latency_notify(struct notifier_block *b, 1334 unsigned long l, void *v) 1335 { 1336 smp_call_function(smp_callback, NULL, 0, 1); 1337 return NOTIFY_OK; 1338 } 1339 1340 static struct notifier_block acpi_processor_latency_notifier = { 1341 .notifier_call = acpi_processor_latency_notify, 1342 }; 1343 1344 #endif 1345 1346 #else /* CONFIG_CPU_IDLE */ 1347 1348 /** 1349 * acpi_idle_bm_check - checks if bus master activity was detected 1350 */ 1351 static int acpi_idle_bm_check(void) 1352 { 1353 u32 bm_status = 0; 1354 1355 acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); 1356 if (bm_status) 1357 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); 1358 /* 1359 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect 1360 * the true state of bus mastering activity; forcing us to 1361 * manually check the BMIDEA bit of each IDE channel. 1362 */ 1363 else if (errata.piix4.bmisx) { 1364 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) 1365 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) 1366 bm_status = 1; 1367 } 1368 return bm_status; 1369 } 1370 1371 /** 1372 * acpi_idle_update_bm_rld - updates the BM_RLD bit depending on target state 1373 * @pr: the processor 1374 * @target: the new target state 1375 */ 1376 static inline void acpi_idle_update_bm_rld(struct acpi_processor *pr, 1377 struct acpi_processor_cx *target) 1378 { 1379 if (pr->flags.bm_rld_set && target->type != ACPI_STATE_C3) { 1380 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); 1381 pr->flags.bm_rld_set = 0; 1382 } 1383 1384 if (!pr->flags.bm_rld_set && target->type == ACPI_STATE_C3) { 1385 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); 1386 pr->flags.bm_rld_set = 1; 1387 } 1388 } 1389 1390 /** 1391 * acpi_idle_do_entry - a helper function that does C2 and C3 type entry 1392 * @cx: cstate data 1393 * 1394 * Caller disables interrupt before call and enables interrupt after return. 1395 */ 1396 static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) 1397 { 1398 if (cx->entry_method == ACPI_CSTATE_FFH) { 1399 /* Call into architectural FFH based C-state */ 1400 acpi_processor_ffh_cstate_enter(cx); 1401 } else if (cx->entry_method == ACPI_CSTATE_HALT) { 1402 acpi_safe_halt(); 1403 } else { 1404 int unused; 1405 /* IO port based C-state */ 1406 inb(cx->address); 1407 /* Dummy wait op - must do something useless after P_LVL2 read 1408 because chipsets cannot guarantee that STPCLK# signal 1409 gets asserted in time to freeze execution properly. */ 1410 unused = inl(acpi_gbl_FADT.xpm_timer_block.address); 1411 } 1412 } 1413 1414 /** 1415 * acpi_idle_enter_c1 - enters an ACPI C1 state-type 1416 * @dev: the target CPU 1417 * @state: the state data 1418 * 1419 * This is equivalent to the HALT instruction. 1420 */ 1421 static int acpi_idle_enter_c1(struct cpuidle_device *dev, 1422 struct cpuidle_state *state) 1423 { 1424 u32 t1, t2; 1425 struct acpi_processor *pr; 1426 struct acpi_processor_cx *cx = cpuidle_get_statedata(state); 1427 1428 pr = processors[smp_processor_id()]; 1429 1430 if (unlikely(!pr)) 1431 return 0; 1432 1433 local_irq_disable(); 1434 1435 /* Do not access any ACPI IO ports in suspend path */ 1436 if (acpi_idle_suspend) { 1437 acpi_safe_halt(); 1438 local_irq_enable(); 1439 return 0; 1440 } 1441 1442 if (pr->flags.bm_check) 1443 acpi_idle_update_bm_rld(pr, cx); 1444 1445 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); 1446 acpi_idle_do_entry(cx); 1447 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); 1448 1449 local_irq_enable(); 1450 cx->usage++; 1451 1452 return ticks_elapsed_in_us(t1, t2); 1453 } 1454 1455 /** 1456 * acpi_idle_enter_simple - enters an ACPI state without BM handling 1457 * @dev: the target CPU 1458 * @state: the state data 1459 */ 1460 static int acpi_idle_enter_simple(struct cpuidle_device *dev, 1461 struct cpuidle_state *state) 1462 { 1463 struct acpi_processor *pr; 1464 struct acpi_processor_cx *cx = cpuidle_get_statedata(state); 1465 u32 t1, t2; 1466 int sleep_ticks = 0; 1467 1468 pr = processors[smp_processor_id()]; 1469 1470 if (unlikely(!pr)) 1471 return 0; 1472 1473 if (acpi_idle_suspend) 1474 return(acpi_idle_enter_c1(dev, state)); 1475 1476 local_irq_disable(); 1477 current_thread_info()->status &= ~TS_POLLING; 1478 /* 1479 * TS_POLLING-cleared state must be visible before we test 1480 * NEED_RESCHED: 1481 */ 1482 smp_mb(); 1483 1484 if (unlikely(need_resched())) { 1485 current_thread_info()->status |= TS_POLLING; 1486 local_irq_enable(); 1487 return 0; 1488 } 1489 1490 /* 1491 * Must be done before busmaster disable as we might need to 1492 * access HPET ! 1493 */ 1494 acpi_state_timer_broadcast(pr, cx, 1); 1495 1496 if (pr->flags.bm_check) 1497 acpi_idle_update_bm_rld(pr, cx); 1498 1499 if (cx->type == ACPI_STATE_C3) 1500 ACPI_FLUSH_CPU_CACHE(); 1501 1502 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); 1503 /* Tell the scheduler that we are going deep-idle: */ 1504 sched_clock_idle_sleep_event(); 1505 acpi_idle_do_entry(cx); 1506 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); 1507 1508 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) 1509 /* TSC could halt in idle, so notify users */ 1510 if (tsc_halts_in_c(cx->type)) 1511 mark_tsc_unstable("TSC halts in idle");; 1512 #endif 1513 sleep_ticks = ticks_elapsed(t1, t2); 1514 1515 /* Tell the scheduler how much we idled: */ 1516 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); 1517 1518 local_irq_enable(); 1519 current_thread_info()->status |= TS_POLLING; 1520 1521 cx->usage++; 1522 1523 acpi_state_timer_broadcast(pr, cx, 0); 1524 cx->time += sleep_ticks; 1525 return ticks_elapsed_in_us(t1, t2); 1526 } 1527 1528 static int c3_cpu_count; 1529 static DEFINE_SPINLOCK(c3_lock); 1530 1531 /** 1532 * acpi_idle_enter_bm - enters C3 with proper BM handling 1533 * @dev: the target CPU 1534 * @state: the state data 1535 * 1536 * If BM is detected, the deepest non-C3 idle state is entered instead. 1537 */ 1538 static int acpi_idle_enter_bm(struct cpuidle_device *dev, 1539 struct cpuidle_state *state) 1540 { 1541 struct acpi_processor *pr; 1542 struct acpi_processor_cx *cx = cpuidle_get_statedata(state); 1543 u32 t1, t2; 1544 int sleep_ticks = 0; 1545 1546 pr = processors[smp_processor_id()]; 1547 1548 if (unlikely(!pr)) 1549 return 0; 1550 1551 if (acpi_idle_suspend) 1552 return(acpi_idle_enter_c1(dev, state)); 1553 1554 if (acpi_idle_bm_check()) { 1555 if (dev->safe_state) { 1556 return dev->safe_state->enter(dev, dev->safe_state); 1557 } else { 1558 local_irq_disable(); 1559 acpi_safe_halt(); 1560 local_irq_enable(); 1561 return 0; 1562 } 1563 } 1564 1565 local_irq_disable(); 1566 current_thread_info()->status &= ~TS_POLLING; 1567 /* 1568 * TS_POLLING-cleared state must be visible before we test 1569 * NEED_RESCHED: 1570 */ 1571 smp_mb(); 1572 1573 if (unlikely(need_resched())) { 1574 current_thread_info()->status |= TS_POLLING; 1575 local_irq_enable(); 1576 return 0; 1577 } 1578 1579 acpi_unlazy_tlb(smp_processor_id()); 1580 1581 /* Tell the scheduler that we are going deep-idle: */ 1582 sched_clock_idle_sleep_event(); 1583 /* 1584 * Must be done before busmaster disable as we might need to 1585 * access HPET ! 1586 */ 1587 acpi_state_timer_broadcast(pr, cx, 1); 1588 1589 acpi_idle_update_bm_rld(pr, cx); 1590 1591 /* 1592 * disable bus master 1593 * bm_check implies we need ARB_DIS 1594 * !bm_check implies we need cache flush 1595 * bm_control implies whether we can do ARB_DIS 1596 * 1597 * That leaves a case where bm_check is set and bm_control is 1598 * not set. In that case we cannot do much, we enter C3 1599 * without doing anything. 1600 */ 1601 if (pr->flags.bm_check && pr->flags.bm_control) { 1602 spin_lock(&c3_lock); 1603 c3_cpu_count++; 1604 /* Disable bus master arbitration when all CPUs are in C3 */ 1605 if (c3_cpu_count == num_online_cpus()) 1606 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); 1607 spin_unlock(&c3_lock); 1608 } else if (!pr->flags.bm_check) { 1609 ACPI_FLUSH_CPU_CACHE(); 1610 } 1611 1612 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); 1613 acpi_idle_do_entry(cx); 1614 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); 1615 1616 /* Re-enable bus master arbitration */ 1617 if (pr->flags.bm_check && pr->flags.bm_control) { 1618 spin_lock(&c3_lock); 1619 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); 1620 c3_cpu_count--; 1621 spin_unlock(&c3_lock); 1622 } 1623 1624 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) 1625 /* TSC could halt in idle, so notify users */ 1626 if (tsc_halts_in_c(ACPI_STATE_C3)) 1627 mark_tsc_unstable("TSC halts in idle"); 1628 #endif 1629 sleep_ticks = ticks_elapsed(t1, t2); 1630 /* Tell the scheduler how much we idled: */ 1631 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); 1632 1633 local_irq_enable(); 1634 current_thread_info()->status |= TS_POLLING; 1635 1636 cx->usage++; 1637 1638 acpi_state_timer_broadcast(pr, cx, 0); 1639 cx->time += sleep_ticks; 1640 return ticks_elapsed_in_us(t1, t2); 1641 } 1642 1643 struct cpuidle_driver acpi_idle_driver = { 1644 .name = "acpi_idle", 1645 .owner = THIS_MODULE, 1646 }; 1647 1648 /** 1649 * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE 1650 * @pr: the ACPI processor 1651 */ 1652 static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) 1653 { 1654 int i, count = CPUIDLE_DRIVER_STATE_START; 1655 struct acpi_processor_cx *cx; 1656 struct cpuidle_state *state; 1657 struct cpuidle_device *dev = &pr->power.dev; 1658 1659 if (!pr->flags.power_setup_done) 1660 return -EINVAL; 1661 1662 if (pr->flags.power == 0) { 1663 return -EINVAL; 1664 } 1665 1666 for (i = 0; i < CPUIDLE_STATE_MAX; i++) { 1667 dev->states[i].name[0] = '\0'; 1668 dev->states[i].desc[0] = '\0'; 1669 } 1670 1671 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { 1672 cx = &pr->power.states[i]; 1673 state = &dev->states[count]; 1674 1675 if (!cx->valid) 1676 continue; 1677 1678 #ifdef CONFIG_HOTPLUG_CPU 1679 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && 1680 !pr->flags.has_cst && 1681 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) 1682 continue; 1683 #endif 1684 cpuidle_set_statedata(state, cx); 1685 1686 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); 1687 strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); 1688 state->exit_latency = cx->latency; 1689 state->target_residency = cx->latency * latency_factor; 1690 state->power_usage = cx->power; 1691 1692 state->flags = 0; 1693 switch (cx->type) { 1694 case ACPI_STATE_C1: 1695 state->flags |= CPUIDLE_FLAG_SHALLOW; 1696 if (cx->entry_method == ACPI_CSTATE_FFH) 1697 state->flags |= CPUIDLE_FLAG_TIME_VALID; 1698 1699 state->enter = acpi_idle_enter_c1; 1700 dev->safe_state = state; 1701 break; 1702 1703 case ACPI_STATE_C2: 1704 state->flags |= CPUIDLE_FLAG_BALANCED; 1705 state->flags |= CPUIDLE_FLAG_TIME_VALID; 1706 state->enter = acpi_idle_enter_simple; 1707 dev->safe_state = state; 1708 break; 1709 1710 case ACPI_STATE_C3: 1711 state->flags |= CPUIDLE_FLAG_DEEP; 1712 state->flags |= CPUIDLE_FLAG_TIME_VALID; 1713 state->flags |= CPUIDLE_FLAG_CHECK_BM; 1714 state->enter = pr->flags.bm_check ? 1715 acpi_idle_enter_bm : 1716 acpi_idle_enter_simple; 1717 break; 1718 } 1719 1720 count++; 1721 if (count == CPUIDLE_STATE_MAX) 1722 break; 1723 } 1724 1725 dev->state_count = count; 1726 1727 if (!count) 1728 return -EINVAL; 1729 1730 return 0; 1731 } 1732 1733 int acpi_processor_cst_has_changed(struct acpi_processor *pr) 1734 { 1735 int ret; 1736 1737 if (!pr) 1738 return -EINVAL; 1739 1740 if (nocst) { 1741 return -ENODEV; 1742 } 1743 1744 if (!pr->flags.power_setup_done) 1745 return -ENODEV; 1746 1747 cpuidle_pause_and_lock(); 1748 cpuidle_disable_device(&pr->power.dev); 1749 acpi_processor_get_power_info(pr); 1750 acpi_processor_setup_cpuidle(pr); 1751 ret = cpuidle_enable_device(&pr->power.dev); 1752 cpuidle_resume_and_unlock(); 1753 1754 return ret; 1755 } 1756 1757 #endif /* CONFIG_CPU_IDLE */ 1758 1759 int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, 1760 struct acpi_device *device) 1761 { 1762 acpi_status status = 0; 1763 static int first_run; 1764 struct proc_dir_entry *entry = NULL; 1765 unsigned int i; 1766 1767 1768 if (!first_run) { 1769 dmi_check_system(processor_power_dmi_table); 1770 max_cstate = acpi_processor_cstate_check(max_cstate); 1771 if (max_cstate < ACPI_C_STATES_MAX) 1772 printk(KERN_NOTICE 1773 "ACPI: processor limited to max C-state %d\n", 1774 max_cstate); 1775 first_run++; 1776 #if !defined(CONFIG_CPU_IDLE) && defined(CONFIG_SMP) 1777 pm_qos_add_notifier(PM_QOS_CPU_DMA_LATENCY, 1778 &acpi_processor_latency_notifier); 1779 #endif 1780 } 1781 1782 if (!pr) 1783 return -EINVAL; 1784 1785 if (acpi_gbl_FADT.cst_control && !nocst) { 1786 status = 1787 acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); 1788 if (ACPI_FAILURE(status)) { 1789 ACPI_EXCEPTION((AE_INFO, status, 1790 "Notifying BIOS of _CST ability failed")); 1791 } 1792 } 1793 1794 acpi_processor_get_power_info(pr); 1795 pr->flags.power_setup_done = 1; 1796 1797 /* 1798 * Install the idle handler if processor power management is supported. 1799 * Note that we use previously set idle handler will be used on 1800 * platforms that only support C1. 1801 */ 1802 if ((pr->flags.power) && (!boot_option_idle_override)) { 1803 #ifdef CONFIG_CPU_IDLE 1804 acpi_processor_setup_cpuidle(pr); 1805 pr->power.dev.cpu = pr->id; 1806 if (cpuidle_register_device(&pr->power.dev)) 1807 return -EIO; 1808 #endif 1809 1810 printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id); 1811 for (i = 1; i <= pr->power.count; i++) 1812 if (pr->power.states[i].valid) 1813 printk(" C%d[C%d]", i, 1814 pr->power.states[i].type); 1815 printk(")\n"); 1816 1817 #ifndef CONFIG_CPU_IDLE 1818 if (pr->id == 0) { 1819 pm_idle_save = pm_idle; 1820 pm_idle = acpi_processor_idle; 1821 } 1822 #endif 1823 } 1824 1825 /* 'power' [R] */ 1826 entry = proc_create_data(ACPI_PROCESSOR_FILE_POWER, 1827 S_IRUGO, acpi_device_dir(device), 1828 &acpi_processor_power_fops, 1829 acpi_driver_data(device)); 1830 if (!entry) 1831 return -EIO; 1832 return 0; 1833 } 1834 1835 int acpi_processor_power_exit(struct acpi_processor *pr, 1836 struct acpi_device *device) 1837 { 1838 #ifdef CONFIG_CPU_IDLE 1839 if ((pr->flags.power) && (!boot_option_idle_override)) 1840 cpuidle_unregister_device(&pr->power.dev); 1841 #endif 1842 pr->flags.power_setup_done = 0; 1843 1844 if (acpi_device_dir(device)) 1845 remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, 1846 acpi_device_dir(device)); 1847 1848 #ifndef CONFIG_CPU_IDLE 1849 1850 /* Unregister the idle handler when processor #0 is removed. */ 1851 if (pr->id == 0) { 1852 pm_idle = pm_idle_save; 1853 1854 /* 1855 * We are about to unload the current idle thread pm callback 1856 * (pm_idle), Wait for all processors to update cached/local 1857 * copies of pm_idle before proceeding. 1858 */ 1859 cpu_idle_wait(); 1860 #ifdef CONFIG_SMP 1861 pm_qos_remove_notifier(PM_QOS_CPU_DMA_LATENCY, 1862 &acpi_processor_latency_notifier); 1863 #endif 1864 } 1865 #endif 1866 1867 return 0; 1868 } 1869