1 /* 2 * processor_idle - idle state submodule to the ACPI processor driver 3 * 4 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> 5 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 6 * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> 7 * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> 8 * - Added processor hotplug support 9 * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> 10 * - Added support for C3 on SMP 11 * 12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or (at 17 * your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, but 20 * WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 22 * General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License along 25 * with this program; if not, write to the Free Software Foundation, Inc., 26 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. 27 * 28 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 29 */ 30 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/init.h> 34 #include <linux/cpufreq.h> 35 #include <linux/proc_fs.h> 36 #include <linux/seq_file.h> 37 #include <linux/acpi.h> 38 #include <linux/dmi.h> 39 #include <linux/moduleparam.h> 40 #include <linux/sched.h> /* need_resched() */ 41 #include <linux/pm_qos_params.h> 42 #include <linux/clockchips.h> 43 #include <linux/cpuidle.h> 44 #include <linux/irqflags.h> 45 46 /* 47 * Include the apic definitions for x86 to have the APIC timer related defines 48 * available also for UP (on SMP it gets magically included via linux/smp.h). 49 * asm/acpi.h is not an option, as it would require more include magic. Also 50 * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. 51 */ 52 #ifdef CONFIG_X86 53 #include <asm/apic.h> 54 #endif 55 56 #include <asm/io.h> 57 #include <asm/uaccess.h> 58 59 #include <acpi/acpi_bus.h> 60 #include <acpi/processor.h> 61 #include <asm/processor.h> 62 63 #define PREFIX "ACPI: " 64 65 #define ACPI_PROCESSOR_CLASS "processor" 66 #define _COMPONENT ACPI_PROCESSOR_COMPONENT 67 ACPI_MODULE_NAME("processor_idle"); 68 #define ACPI_PROCESSOR_FILE_POWER "power" 69 #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) 70 #define C2_OVERHEAD 1 /* 1us */ 71 #define C3_OVERHEAD 1 /* 1us */ 72 #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) 73 74 static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; 75 module_param(max_cstate, uint, 0000); 76 static unsigned int nocst __read_mostly; 77 module_param(nocst, uint, 0000); 78 79 static unsigned int latency_factor __read_mostly = 2; 80 module_param(latency_factor, uint, 0644); 81 82 static s64 us_to_pm_timer_ticks(s64 t) 83 { 84 return div64_u64(t * PM_TIMER_FREQUENCY, 1000000); 85 } 86 /* 87 * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. 88 * For now disable this. Probably a bug somewhere else. 89 * 90 * To skip this limit, boot/load with a large max_cstate limit. 91 */ 92 static int set_max_cstate(const struct dmi_system_id *id) 93 { 94 if (max_cstate > ACPI_PROCESSOR_MAX_POWER) 95 return 0; 96 97 printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." 98 " Override with \"processor.max_cstate=%d\"\n", id->ident, 99 (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); 100 101 max_cstate = (long)id->driver_data; 102 103 return 0; 104 } 105 106 /* Actually this shouldn't be __cpuinitdata, would be better to fix the 107 callers to only run once -AK */ 108 static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { 109 { set_max_cstate, "Clevo 5600D", { 110 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), 111 DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, 112 (void *)2}, 113 {}, 114 }; 115 116 117 /* 118 * Callers should disable interrupts before the call and enable 119 * interrupts after return. 120 */ 121 static void acpi_safe_halt(void) 122 { 123 current_thread_info()->status &= ~TS_POLLING; 124 /* 125 * TS_POLLING-cleared state must be visible before we 126 * test NEED_RESCHED: 127 */ 128 smp_mb(); 129 if (!need_resched()) { 130 safe_halt(); 131 local_irq_disable(); 132 } 133 current_thread_info()->status |= TS_POLLING; 134 } 135 136 #ifdef ARCH_APICTIMER_STOPS_ON_C3 137 138 /* 139 * Some BIOS implementations switch to C3 in the published C2 state. 140 * This seems to be a common problem on AMD boxen, but other vendors 141 * are affected too. We pick the most conservative approach: we assume 142 * that the local APIC stops in both C2 and C3. 143 */ 144 static void lapic_timer_check_state(int state, struct acpi_processor *pr, 145 struct acpi_processor_cx *cx) 146 { 147 struct acpi_processor_power *pwr = &pr->power; 148 u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; 149 150 if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT)) 151 return; 152 153 if (boot_cpu_has(X86_FEATURE_AMDC1E)) 154 type = ACPI_STATE_C1; 155 156 /* 157 * Check, if one of the previous states already marked the lapic 158 * unstable 159 */ 160 if (pwr->timer_broadcast_on_state < state) 161 return; 162 163 if (cx->type >= type) 164 pr->power.timer_broadcast_on_state = state; 165 } 166 167 static void __lapic_timer_propagate_broadcast(void *arg) 168 { 169 struct acpi_processor *pr = (struct acpi_processor *) arg; 170 unsigned long reason; 171 172 reason = pr->power.timer_broadcast_on_state < INT_MAX ? 173 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; 174 175 clockevents_notify(reason, &pr->id); 176 } 177 178 static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) 179 { 180 smp_call_function_single(pr->id, __lapic_timer_propagate_broadcast, 181 (void *)pr, 1); 182 } 183 184 /* Power(C) State timer broadcast control */ 185 static void lapic_timer_state_broadcast(struct acpi_processor *pr, 186 struct acpi_processor_cx *cx, 187 int broadcast) 188 { 189 int state = cx - pr->power.states; 190 191 if (state >= pr->power.timer_broadcast_on_state) { 192 unsigned long reason; 193 194 reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : 195 CLOCK_EVT_NOTIFY_BROADCAST_EXIT; 196 clockevents_notify(reason, &pr->id); 197 } 198 } 199 200 #else 201 202 static void lapic_timer_check_state(int state, struct acpi_processor *pr, 203 struct acpi_processor_cx *cstate) { } 204 static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { } 205 static void lapic_timer_state_broadcast(struct acpi_processor *pr, 206 struct acpi_processor_cx *cx, 207 int broadcast) 208 { 209 } 210 211 #endif 212 213 /* 214 * Suspend / resume control 215 */ 216 static int acpi_idle_suspend; 217 static u32 saved_bm_rld; 218 219 static void acpi_idle_bm_rld_save(void) 220 { 221 acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld); 222 } 223 static void acpi_idle_bm_rld_restore(void) 224 { 225 u32 resumed_bm_rld; 226 227 acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &resumed_bm_rld); 228 229 if (resumed_bm_rld != saved_bm_rld) 230 acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld); 231 } 232 233 int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) 234 { 235 if (acpi_idle_suspend == 1) 236 return 0; 237 238 acpi_idle_bm_rld_save(); 239 acpi_idle_suspend = 1; 240 return 0; 241 } 242 243 int acpi_processor_resume(struct acpi_device * device) 244 { 245 if (acpi_idle_suspend == 0) 246 return 0; 247 248 acpi_idle_bm_rld_restore(); 249 acpi_idle_suspend = 0; 250 return 0; 251 } 252 253 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) 254 static void tsc_check_state(int state) 255 { 256 switch (boot_cpu_data.x86_vendor) { 257 case X86_VENDOR_AMD: 258 case X86_VENDOR_INTEL: 259 /* 260 * AMD Fam10h TSC will tick in all 261 * C/P/S0/S1 states when this bit is set. 262 */ 263 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) 264 return; 265 266 /*FALL THROUGH*/ 267 default: 268 /* TSC could halt in idle, so notify users */ 269 if (state > ACPI_STATE_C1) 270 mark_tsc_unstable("TSC halts in idle"); 271 } 272 } 273 #else 274 static void tsc_check_state(int state) { return; } 275 #endif 276 277 static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) 278 { 279 280 if (!pr) 281 return -EINVAL; 282 283 if (!pr->pblk) 284 return -ENODEV; 285 286 /* if info is obtained from pblk/fadt, type equals state */ 287 pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; 288 pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; 289 290 #ifndef CONFIG_HOTPLUG_CPU 291 /* 292 * Check for P_LVL2_UP flag before entering C2 and above on 293 * an SMP system. 294 */ 295 if ((num_online_cpus() > 1) && 296 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) 297 return -ENODEV; 298 #endif 299 300 /* determine C2 and C3 address from pblk */ 301 pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; 302 pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; 303 304 /* determine latencies from FADT */ 305 pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; 306 pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; 307 308 /* 309 * FADT specified C2 latency must be less than or equal to 310 * 100 microseconds. 311 */ 312 if (acpi_gbl_FADT.C2latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { 313 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 314 "C2 latency too large [%d]\n", acpi_gbl_FADT.C2latency)); 315 /* invalidate C2 */ 316 pr->power.states[ACPI_STATE_C2].address = 0; 317 } 318 319 /* 320 * FADT supplied C3 latency must be less than or equal to 321 * 1000 microseconds. 322 */ 323 if (acpi_gbl_FADT.C3latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { 324 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 325 "C3 latency too large [%d]\n", acpi_gbl_FADT.C3latency)); 326 /* invalidate C3 */ 327 pr->power.states[ACPI_STATE_C3].address = 0; 328 } 329 330 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 331 "lvl2[0x%08x] lvl3[0x%08x]\n", 332 pr->power.states[ACPI_STATE_C2].address, 333 pr->power.states[ACPI_STATE_C3].address)); 334 335 return 0; 336 } 337 338 static int acpi_processor_get_power_info_default(struct acpi_processor *pr) 339 { 340 if (!pr->power.states[ACPI_STATE_C1].valid) { 341 /* set the first C-State to C1 */ 342 /* all processors need to support C1 */ 343 pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; 344 pr->power.states[ACPI_STATE_C1].valid = 1; 345 pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; 346 } 347 /* the C0 state only exists as a filler in our array */ 348 pr->power.states[ACPI_STATE_C0].valid = 1; 349 return 0; 350 } 351 352 static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) 353 { 354 acpi_status status = 0; 355 acpi_integer count; 356 int current_count; 357 int i; 358 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 359 union acpi_object *cst; 360 361 362 if (nocst) 363 return -ENODEV; 364 365 current_count = 0; 366 367 status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); 368 if (ACPI_FAILURE(status)) { 369 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); 370 return -ENODEV; 371 } 372 373 cst = buffer.pointer; 374 375 /* There must be at least 2 elements */ 376 if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { 377 printk(KERN_ERR PREFIX "not enough elements in _CST\n"); 378 status = -EFAULT; 379 goto end; 380 } 381 382 count = cst->package.elements[0].integer.value; 383 384 /* Validate number of power states. */ 385 if (count < 1 || count != cst->package.count - 1) { 386 printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); 387 status = -EFAULT; 388 goto end; 389 } 390 391 /* Tell driver that at least _CST is supported. */ 392 pr->flags.has_cst = 1; 393 394 for (i = 1; i <= count; i++) { 395 union acpi_object *element; 396 union acpi_object *obj; 397 struct acpi_power_register *reg; 398 struct acpi_processor_cx cx; 399 400 memset(&cx, 0, sizeof(cx)); 401 402 element = &(cst->package.elements[i]); 403 if (element->type != ACPI_TYPE_PACKAGE) 404 continue; 405 406 if (element->package.count != 4) 407 continue; 408 409 obj = &(element->package.elements[0]); 410 411 if (obj->type != ACPI_TYPE_BUFFER) 412 continue; 413 414 reg = (struct acpi_power_register *)obj->buffer.pointer; 415 416 if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && 417 (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) 418 continue; 419 420 /* There should be an easy way to extract an integer... */ 421 obj = &(element->package.elements[1]); 422 if (obj->type != ACPI_TYPE_INTEGER) 423 continue; 424 425 cx.type = obj->integer.value; 426 /* 427 * Some buggy BIOSes won't list C1 in _CST - 428 * Let acpi_processor_get_power_info_default() handle them later 429 */ 430 if (i == 1 && cx.type != ACPI_STATE_C1) 431 current_count++; 432 433 cx.address = reg->address; 434 cx.index = current_count + 1; 435 436 cx.entry_method = ACPI_CSTATE_SYSTEMIO; 437 if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { 438 if (acpi_processor_ffh_cstate_probe 439 (pr->id, &cx, reg) == 0) { 440 cx.entry_method = ACPI_CSTATE_FFH; 441 } else if (cx.type == ACPI_STATE_C1) { 442 /* 443 * C1 is a special case where FIXED_HARDWARE 444 * can be handled in non-MWAIT way as well. 445 * In that case, save this _CST entry info. 446 * Otherwise, ignore this info and continue. 447 */ 448 cx.entry_method = ACPI_CSTATE_HALT; 449 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); 450 } else { 451 continue; 452 } 453 if (cx.type == ACPI_STATE_C1 && 454 (idle_halt || idle_nomwait)) { 455 /* 456 * In most cases the C1 space_id obtained from 457 * _CST object is FIXED_HARDWARE access mode. 458 * But when the option of idle=halt is added, 459 * the entry_method type should be changed from 460 * CSTATE_FFH to CSTATE_HALT. 461 * When the option of idle=nomwait is added, 462 * the C1 entry_method type should be 463 * CSTATE_HALT. 464 */ 465 cx.entry_method = ACPI_CSTATE_HALT; 466 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); 467 } 468 } else { 469 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", 470 cx.address); 471 } 472 473 if (cx.type == ACPI_STATE_C1) { 474 cx.valid = 1; 475 } 476 477 obj = &(element->package.elements[2]); 478 if (obj->type != ACPI_TYPE_INTEGER) 479 continue; 480 481 cx.latency = obj->integer.value; 482 483 obj = &(element->package.elements[3]); 484 if (obj->type != ACPI_TYPE_INTEGER) 485 continue; 486 487 cx.power = obj->integer.value; 488 489 current_count++; 490 memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); 491 492 /* 493 * We support total ACPI_PROCESSOR_MAX_POWER - 1 494 * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) 495 */ 496 if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { 497 printk(KERN_WARNING 498 "Limiting number of power states to max (%d)\n", 499 ACPI_PROCESSOR_MAX_POWER); 500 printk(KERN_WARNING 501 "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); 502 break; 503 } 504 } 505 506 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", 507 current_count)); 508 509 /* Validate number of power states discovered */ 510 if (current_count < 2) 511 status = -EFAULT; 512 513 end: 514 kfree(buffer.pointer); 515 516 return status; 517 } 518 519 static void acpi_processor_power_verify_c3(struct acpi_processor *pr, 520 struct acpi_processor_cx *cx) 521 { 522 static int bm_check_flag = -1; 523 static int bm_control_flag = -1; 524 525 526 if (!cx->address) 527 return; 528 529 /* 530 * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) 531 * DMA transfers are used by any ISA device to avoid livelock. 532 * Note that we could disable Type-F DMA (as recommended by 533 * the erratum), but this is known to disrupt certain ISA 534 * devices thus we take the conservative approach. 535 */ 536 else if (errata.piix4.fdma) { 537 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 538 "C3 not supported on PIIX4 with Type-F DMA\n")); 539 return; 540 } 541 542 /* All the logic here assumes flags.bm_check is same across all CPUs */ 543 if (bm_check_flag == -1) { 544 /* Determine whether bm_check is needed based on CPU */ 545 acpi_processor_power_init_bm_check(&(pr->flags), pr->id); 546 bm_check_flag = pr->flags.bm_check; 547 bm_control_flag = pr->flags.bm_control; 548 } else { 549 pr->flags.bm_check = bm_check_flag; 550 pr->flags.bm_control = bm_control_flag; 551 } 552 553 if (pr->flags.bm_check) { 554 if (!pr->flags.bm_control) { 555 if (pr->flags.has_cst != 1) { 556 /* bus mastering control is necessary */ 557 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 558 "C3 support requires BM control\n")); 559 return; 560 } else { 561 /* Here we enter C3 without bus mastering */ 562 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 563 "C3 support without BM control\n")); 564 } 565 } 566 } else { 567 /* 568 * WBINVD should be set in fadt, for C3 state to be 569 * supported on when bm_check is not required. 570 */ 571 if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { 572 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 573 "Cache invalidation should work properly" 574 " for C3 to be enabled on SMP systems\n")); 575 return; 576 } 577 } 578 579 /* 580 * Otherwise we've met all of our C3 requirements. 581 * Normalize the C3 latency to expidite policy. Enable 582 * checking of bus mastering status (bm_check) so we can 583 * use this in our C3 policy 584 */ 585 cx->valid = 1; 586 587 cx->latency_ticks = cx->latency; 588 /* 589 * On older chipsets, BM_RLD needs to be set 590 * in order for Bus Master activity to wake the 591 * system from C3. Newer chipsets handle DMA 592 * during C3 automatically and BM_RLD is a NOP. 593 * In either case, the proper way to 594 * handle BM_RLD is to set it and leave it set. 595 */ 596 acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1); 597 598 return; 599 } 600 601 static int acpi_processor_power_verify(struct acpi_processor *pr) 602 { 603 unsigned int i; 604 unsigned int working = 0; 605 606 pr->power.timer_broadcast_on_state = INT_MAX; 607 608 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { 609 struct acpi_processor_cx *cx = &pr->power.states[i]; 610 611 switch (cx->type) { 612 case ACPI_STATE_C1: 613 cx->valid = 1; 614 break; 615 616 case ACPI_STATE_C2: 617 if (!cx->address) 618 break; 619 cx->valid = 1; 620 cx->latency_ticks = cx->latency; /* Normalize latency */ 621 break; 622 623 case ACPI_STATE_C3: 624 acpi_processor_power_verify_c3(pr, cx); 625 break; 626 } 627 if (!cx->valid) 628 continue; 629 630 lapic_timer_check_state(i, pr, cx); 631 tsc_check_state(cx->type); 632 working++; 633 } 634 635 lapic_timer_propagate_broadcast(pr); 636 637 return (working); 638 } 639 640 static int acpi_processor_get_power_info(struct acpi_processor *pr) 641 { 642 unsigned int i; 643 int result; 644 645 646 /* NOTE: the idle thread may not be running while calling 647 * this function */ 648 649 /* Zero initialize all the C-states info. */ 650 memset(pr->power.states, 0, sizeof(pr->power.states)); 651 652 result = acpi_processor_get_power_info_cst(pr); 653 if (result == -ENODEV) 654 result = acpi_processor_get_power_info_fadt(pr); 655 656 if (result) 657 return result; 658 659 acpi_processor_get_power_info_default(pr); 660 661 pr->power.count = acpi_processor_power_verify(pr); 662 663 /* 664 * if one state of type C2 or C3 is available, mark this 665 * CPU as being "idle manageable" 666 */ 667 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { 668 if (pr->power.states[i].valid) { 669 pr->power.count = i; 670 if (pr->power.states[i].type >= ACPI_STATE_C2) 671 pr->flags.power = 1; 672 } 673 } 674 675 return 0; 676 } 677 678 #ifdef CONFIG_ACPI_PROCFS 679 static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) 680 { 681 struct acpi_processor *pr = seq->private; 682 unsigned int i; 683 684 685 if (!pr) 686 goto end; 687 688 seq_printf(seq, "active state: C%zd\n" 689 "max_cstate: C%d\n" 690 "maximum allowed latency: %d usec\n", 691 pr->power.state ? pr->power.state - pr->power.states : 0, 692 max_cstate, pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)); 693 694 seq_puts(seq, "states:\n"); 695 696 for (i = 1; i <= pr->power.count; i++) { 697 seq_printf(seq, " %cC%d: ", 698 (&pr->power.states[i] == 699 pr->power.state ? '*' : ' '), i); 700 701 if (!pr->power.states[i].valid) { 702 seq_puts(seq, "<not supported>\n"); 703 continue; 704 } 705 706 switch (pr->power.states[i].type) { 707 case ACPI_STATE_C1: 708 seq_printf(seq, "type[C1] "); 709 break; 710 case ACPI_STATE_C2: 711 seq_printf(seq, "type[C2] "); 712 break; 713 case ACPI_STATE_C3: 714 seq_printf(seq, "type[C3] "); 715 break; 716 default: 717 seq_printf(seq, "type[--] "); 718 break; 719 } 720 721 if (pr->power.states[i].promotion.state) 722 seq_printf(seq, "promotion[C%zd] ", 723 (pr->power.states[i].promotion.state - 724 pr->power.states)); 725 else 726 seq_puts(seq, "promotion[--] "); 727 728 if (pr->power.states[i].demotion.state) 729 seq_printf(seq, "demotion[C%zd] ", 730 (pr->power.states[i].demotion.state - 731 pr->power.states)); 732 else 733 seq_puts(seq, "demotion[--] "); 734 735 seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", 736 pr->power.states[i].latency, 737 pr->power.states[i].usage, 738 (unsigned long long)pr->power.states[i].time); 739 } 740 741 end: 742 return 0; 743 } 744 745 static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) 746 { 747 return single_open(file, acpi_processor_power_seq_show, 748 PDE(inode)->data); 749 } 750 751 static const struct file_operations acpi_processor_power_fops = { 752 .owner = THIS_MODULE, 753 .open = acpi_processor_power_open_fs, 754 .read = seq_read, 755 .llseek = seq_lseek, 756 .release = single_release, 757 }; 758 #endif 759 760 /** 761 * acpi_idle_bm_check - checks if bus master activity was detected 762 */ 763 static int acpi_idle_bm_check(void) 764 { 765 u32 bm_status = 0; 766 767 acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); 768 if (bm_status) 769 acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); 770 /* 771 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect 772 * the true state of bus mastering activity; forcing us to 773 * manually check the BMIDEA bit of each IDE channel. 774 */ 775 else if (errata.piix4.bmisx) { 776 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) 777 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) 778 bm_status = 1; 779 } 780 return bm_status; 781 } 782 783 /** 784 * acpi_idle_do_entry - a helper function that does C2 and C3 type entry 785 * @cx: cstate data 786 * 787 * Caller disables interrupt before call and enables interrupt after return. 788 */ 789 static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) 790 { 791 /* Don't trace irqs off for idle */ 792 stop_critical_timings(); 793 if (cx->entry_method == ACPI_CSTATE_FFH) { 794 /* Call into architectural FFH based C-state */ 795 acpi_processor_ffh_cstate_enter(cx); 796 } else if (cx->entry_method == ACPI_CSTATE_HALT) { 797 acpi_safe_halt(); 798 } else { 799 int unused; 800 /* IO port based C-state */ 801 inb(cx->address); 802 /* Dummy wait op - must do something useless after P_LVL2 read 803 because chipsets cannot guarantee that STPCLK# signal 804 gets asserted in time to freeze execution properly. */ 805 unused = inl(acpi_gbl_FADT.xpm_timer_block.address); 806 } 807 start_critical_timings(); 808 } 809 810 /** 811 * acpi_idle_enter_c1 - enters an ACPI C1 state-type 812 * @dev: the target CPU 813 * @state: the state data 814 * 815 * This is equivalent to the HALT instruction. 816 */ 817 static int acpi_idle_enter_c1(struct cpuidle_device *dev, 818 struct cpuidle_state *state) 819 { 820 ktime_t kt1, kt2; 821 s64 idle_time; 822 struct acpi_processor *pr; 823 struct acpi_processor_cx *cx = cpuidle_get_statedata(state); 824 825 pr = __get_cpu_var(processors); 826 827 if (unlikely(!pr)) 828 return 0; 829 830 local_irq_disable(); 831 832 /* Do not access any ACPI IO ports in suspend path */ 833 if (acpi_idle_suspend) { 834 local_irq_enable(); 835 cpu_relax(); 836 return 0; 837 } 838 839 lapic_timer_state_broadcast(pr, cx, 1); 840 kt1 = ktime_get_real(); 841 acpi_idle_do_entry(cx); 842 kt2 = ktime_get_real(); 843 idle_time = ktime_to_us(ktime_sub(kt2, kt1)); 844 845 local_irq_enable(); 846 cx->usage++; 847 lapic_timer_state_broadcast(pr, cx, 0); 848 849 return idle_time; 850 } 851 852 /** 853 * acpi_idle_enter_simple - enters an ACPI state without BM handling 854 * @dev: the target CPU 855 * @state: the state data 856 */ 857 static int acpi_idle_enter_simple(struct cpuidle_device *dev, 858 struct cpuidle_state *state) 859 { 860 struct acpi_processor *pr; 861 struct acpi_processor_cx *cx = cpuidle_get_statedata(state); 862 ktime_t kt1, kt2; 863 s64 idle_time; 864 s64 sleep_ticks = 0; 865 866 pr = __get_cpu_var(processors); 867 868 if (unlikely(!pr)) 869 return 0; 870 871 if (acpi_idle_suspend) 872 return(acpi_idle_enter_c1(dev, state)); 873 874 local_irq_disable(); 875 current_thread_info()->status &= ~TS_POLLING; 876 /* 877 * TS_POLLING-cleared state must be visible before we test 878 * NEED_RESCHED: 879 */ 880 smp_mb(); 881 882 if (unlikely(need_resched())) { 883 current_thread_info()->status |= TS_POLLING; 884 local_irq_enable(); 885 return 0; 886 } 887 888 /* 889 * Must be done before busmaster disable as we might need to 890 * access HPET ! 891 */ 892 lapic_timer_state_broadcast(pr, cx, 1); 893 894 if (cx->type == ACPI_STATE_C3) 895 ACPI_FLUSH_CPU_CACHE(); 896 897 kt1 = ktime_get_real(); 898 /* Tell the scheduler that we are going deep-idle: */ 899 sched_clock_idle_sleep_event(); 900 acpi_idle_do_entry(cx); 901 kt2 = ktime_get_real(); 902 idle_time = ktime_to_us(ktime_sub(kt2, kt1)); 903 904 sleep_ticks = us_to_pm_timer_ticks(idle_time); 905 906 /* Tell the scheduler how much we idled: */ 907 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); 908 909 local_irq_enable(); 910 current_thread_info()->status |= TS_POLLING; 911 912 cx->usage++; 913 914 lapic_timer_state_broadcast(pr, cx, 0); 915 cx->time += sleep_ticks; 916 return idle_time; 917 } 918 919 static int c3_cpu_count; 920 static DEFINE_SPINLOCK(c3_lock); 921 922 /** 923 * acpi_idle_enter_bm - enters C3 with proper BM handling 924 * @dev: the target CPU 925 * @state: the state data 926 * 927 * If BM is detected, the deepest non-C3 idle state is entered instead. 928 */ 929 static int acpi_idle_enter_bm(struct cpuidle_device *dev, 930 struct cpuidle_state *state) 931 { 932 struct acpi_processor *pr; 933 struct acpi_processor_cx *cx = cpuidle_get_statedata(state); 934 ktime_t kt1, kt2; 935 s64 idle_time; 936 s64 sleep_ticks = 0; 937 938 939 pr = __get_cpu_var(processors); 940 941 if (unlikely(!pr)) 942 return 0; 943 944 if (acpi_idle_suspend) 945 return(acpi_idle_enter_c1(dev, state)); 946 947 if (acpi_idle_bm_check()) { 948 if (dev->safe_state) { 949 dev->last_state = dev->safe_state; 950 return dev->safe_state->enter(dev, dev->safe_state); 951 } else { 952 local_irq_disable(); 953 acpi_safe_halt(); 954 local_irq_enable(); 955 return 0; 956 } 957 } 958 959 local_irq_disable(); 960 current_thread_info()->status &= ~TS_POLLING; 961 /* 962 * TS_POLLING-cleared state must be visible before we test 963 * NEED_RESCHED: 964 */ 965 smp_mb(); 966 967 if (unlikely(need_resched())) { 968 current_thread_info()->status |= TS_POLLING; 969 local_irq_enable(); 970 return 0; 971 } 972 973 acpi_unlazy_tlb(smp_processor_id()); 974 975 /* Tell the scheduler that we are going deep-idle: */ 976 sched_clock_idle_sleep_event(); 977 /* 978 * Must be done before busmaster disable as we might need to 979 * access HPET ! 980 */ 981 lapic_timer_state_broadcast(pr, cx, 1); 982 983 kt1 = ktime_get_real(); 984 /* 985 * disable bus master 986 * bm_check implies we need ARB_DIS 987 * !bm_check implies we need cache flush 988 * bm_control implies whether we can do ARB_DIS 989 * 990 * That leaves a case where bm_check is set and bm_control is 991 * not set. In that case we cannot do much, we enter C3 992 * without doing anything. 993 */ 994 if (pr->flags.bm_check && pr->flags.bm_control) { 995 spin_lock(&c3_lock); 996 c3_cpu_count++; 997 /* Disable bus master arbitration when all CPUs are in C3 */ 998 if (c3_cpu_count == num_online_cpus()) 999 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1); 1000 spin_unlock(&c3_lock); 1001 } else if (!pr->flags.bm_check) { 1002 ACPI_FLUSH_CPU_CACHE(); 1003 } 1004 1005 acpi_idle_do_entry(cx); 1006 1007 /* Re-enable bus master arbitration */ 1008 if (pr->flags.bm_check && pr->flags.bm_control) { 1009 spin_lock(&c3_lock); 1010 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0); 1011 c3_cpu_count--; 1012 spin_unlock(&c3_lock); 1013 } 1014 kt2 = ktime_get_real(); 1015 idle_time = ktime_to_us(ktime_sub(kt2, kt1)); 1016 1017 sleep_ticks = us_to_pm_timer_ticks(idle_time); 1018 /* Tell the scheduler how much we idled: */ 1019 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); 1020 1021 local_irq_enable(); 1022 current_thread_info()->status |= TS_POLLING; 1023 1024 cx->usage++; 1025 1026 lapic_timer_state_broadcast(pr, cx, 0); 1027 cx->time += sleep_ticks; 1028 return idle_time; 1029 } 1030 1031 struct cpuidle_driver acpi_idle_driver = { 1032 .name = "acpi_idle", 1033 .owner = THIS_MODULE, 1034 }; 1035 1036 /** 1037 * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE 1038 * @pr: the ACPI processor 1039 */ 1040 static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) 1041 { 1042 int i, count = CPUIDLE_DRIVER_STATE_START; 1043 struct acpi_processor_cx *cx; 1044 struct cpuidle_state *state; 1045 struct cpuidle_device *dev = &pr->power.dev; 1046 1047 if (!pr->flags.power_setup_done) 1048 return -EINVAL; 1049 1050 if (pr->flags.power == 0) { 1051 return -EINVAL; 1052 } 1053 1054 dev->cpu = pr->id; 1055 for (i = 0; i < CPUIDLE_STATE_MAX; i++) { 1056 dev->states[i].name[0] = '\0'; 1057 dev->states[i].desc[0] = '\0'; 1058 } 1059 1060 if (max_cstate == 0) 1061 max_cstate = 1; 1062 1063 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { 1064 cx = &pr->power.states[i]; 1065 state = &dev->states[count]; 1066 1067 if (!cx->valid) 1068 continue; 1069 1070 #ifdef CONFIG_HOTPLUG_CPU 1071 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && 1072 !pr->flags.has_cst && 1073 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) 1074 continue; 1075 #endif 1076 cpuidle_set_statedata(state, cx); 1077 1078 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); 1079 strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); 1080 state->exit_latency = cx->latency; 1081 state->target_residency = cx->latency * latency_factor; 1082 state->power_usage = cx->power; 1083 1084 state->flags = 0; 1085 switch (cx->type) { 1086 case ACPI_STATE_C1: 1087 state->flags |= CPUIDLE_FLAG_SHALLOW; 1088 if (cx->entry_method == ACPI_CSTATE_FFH) 1089 state->flags |= CPUIDLE_FLAG_TIME_VALID; 1090 1091 state->enter = acpi_idle_enter_c1; 1092 dev->safe_state = state; 1093 break; 1094 1095 case ACPI_STATE_C2: 1096 state->flags |= CPUIDLE_FLAG_BALANCED; 1097 state->flags |= CPUIDLE_FLAG_TIME_VALID; 1098 state->enter = acpi_idle_enter_simple; 1099 dev->safe_state = state; 1100 break; 1101 1102 case ACPI_STATE_C3: 1103 state->flags |= CPUIDLE_FLAG_DEEP; 1104 state->flags |= CPUIDLE_FLAG_TIME_VALID; 1105 state->flags |= CPUIDLE_FLAG_CHECK_BM; 1106 state->enter = pr->flags.bm_check ? 1107 acpi_idle_enter_bm : 1108 acpi_idle_enter_simple; 1109 break; 1110 } 1111 1112 count++; 1113 if (count == CPUIDLE_STATE_MAX) 1114 break; 1115 } 1116 1117 dev->state_count = count; 1118 1119 if (!count) 1120 return -EINVAL; 1121 1122 return 0; 1123 } 1124 1125 int acpi_processor_cst_has_changed(struct acpi_processor *pr) 1126 { 1127 int ret = 0; 1128 1129 if (boot_option_idle_override) 1130 return 0; 1131 1132 if (!pr) 1133 return -EINVAL; 1134 1135 if (nocst) { 1136 return -ENODEV; 1137 } 1138 1139 if (!pr->flags.power_setup_done) 1140 return -ENODEV; 1141 1142 cpuidle_pause_and_lock(); 1143 cpuidle_disable_device(&pr->power.dev); 1144 acpi_processor_get_power_info(pr); 1145 if (pr->flags.power) { 1146 acpi_processor_setup_cpuidle(pr); 1147 ret = cpuidle_enable_device(&pr->power.dev); 1148 } 1149 cpuidle_resume_and_unlock(); 1150 1151 return ret; 1152 } 1153 1154 int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, 1155 struct acpi_device *device) 1156 { 1157 acpi_status status = 0; 1158 static int first_run; 1159 #ifdef CONFIG_ACPI_PROCFS 1160 struct proc_dir_entry *entry = NULL; 1161 #endif 1162 1163 if (boot_option_idle_override) 1164 return 0; 1165 1166 if (!first_run) { 1167 if (idle_halt) { 1168 /* 1169 * When the boot option of "idle=halt" is added, halt 1170 * is used for CPU IDLE. 1171 * In such case C2/C3 is meaningless. So the max_cstate 1172 * is set to one. 1173 */ 1174 max_cstate = 1; 1175 } 1176 dmi_check_system(processor_power_dmi_table); 1177 max_cstate = acpi_processor_cstate_check(max_cstate); 1178 if (max_cstate < ACPI_C_STATES_MAX) 1179 printk(KERN_NOTICE 1180 "ACPI: processor limited to max C-state %d\n", 1181 max_cstate); 1182 first_run++; 1183 } 1184 1185 if (!pr) 1186 return -EINVAL; 1187 1188 if (acpi_gbl_FADT.cst_control && !nocst) { 1189 status = 1190 acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); 1191 if (ACPI_FAILURE(status)) { 1192 ACPI_EXCEPTION((AE_INFO, status, 1193 "Notifying BIOS of _CST ability failed")); 1194 } 1195 } 1196 1197 acpi_processor_get_power_info(pr); 1198 pr->flags.power_setup_done = 1; 1199 1200 /* 1201 * Install the idle handler if processor power management is supported. 1202 * Note that we use previously set idle handler will be used on 1203 * platforms that only support C1. 1204 */ 1205 if (pr->flags.power) { 1206 acpi_processor_setup_cpuidle(pr); 1207 if (cpuidle_register_device(&pr->power.dev)) 1208 return -EIO; 1209 } 1210 #ifdef CONFIG_ACPI_PROCFS 1211 /* 'power' [R] */ 1212 entry = proc_create_data(ACPI_PROCESSOR_FILE_POWER, 1213 S_IRUGO, acpi_device_dir(device), 1214 &acpi_processor_power_fops, 1215 acpi_driver_data(device)); 1216 if (!entry) 1217 return -EIO; 1218 #endif 1219 return 0; 1220 } 1221 1222 int acpi_processor_power_exit(struct acpi_processor *pr, 1223 struct acpi_device *device) 1224 { 1225 if (boot_option_idle_override) 1226 return 0; 1227 1228 cpuidle_unregister_device(&pr->power.dev); 1229 pr->flags.power_setup_done = 0; 1230 1231 #ifdef CONFIG_ACPI_PROCFS 1232 if (acpi_device_dir(device)) 1233 remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, 1234 acpi_device_dir(device)); 1235 #endif 1236 1237 return 0; 1238 } 1239