1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 40 $) 4 * 5 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> 6 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 7 */ 8 9 #define pr_fmt(fmt) "ACPI: " fmt 10 11 #include <linux/cleanup.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/init.h> 15 #include <linux/types.h> 16 #include <linux/mutex.h> 17 #include <linux/pm.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/pci.h> 20 #include <linux/pci-acpi.h> 21 #include <linux/dmar.h> 22 #include <linux/acpi.h> 23 #include <linux/slab.h> 24 #include <linux/dmi.h> 25 #include <linux/platform_data/x86/apple.h> 26 #include "internal.h" 27 28 static int acpi_pci_root_add(struct acpi_device *device, 29 const struct acpi_device_id *not_used); 30 static void acpi_pci_root_remove(struct acpi_device *device); 31 32 static int acpi_pci_root_scan_dependent(struct acpi_device *adev) 33 { 34 acpiphp_check_host_bridge(adev); 35 return 0; 36 } 37 38 #define ACPI_PCIE_REQ_SUPPORT (OSC_PCI_EXT_CONFIG_SUPPORT \ 39 | OSC_PCI_ASPM_SUPPORT \ 40 | OSC_PCI_CLOCK_PM_SUPPORT \ 41 | OSC_PCI_MSI_SUPPORT) 42 43 static const struct acpi_device_id root_device_ids[] = { 44 {"PNP0A03", 0}, 45 {"", 0}, 46 }; 47 48 static struct acpi_scan_handler pci_root_handler = { 49 .ids = root_device_ids, 50 .attach = acpi_pci_root_add, 51 .detach = acpi_pci_root_remove, 52 .hotplug = { 53 .enabled = true, 54 .scan_dependent = acpi_pci_root_scan_dependent, 55 }, 56 }; 57 58 /** 59 * acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge 60 * @handle: the ACPI CA node in question. 61 * 62 * Note: we could make this API take a struct acpi_device * instead, but 63 * for now, it's more convenient to operate on an acpi_handle. 64 */ 65 int acpi_is_root_bridge(acpi_handle handle) 66 { 67 struct acpi_device *device = acpi_fetch_acpi_dev(handle); 68 int ret; 69 70 if (!device) 71 return 0; 72 73 ret = acpi_match_device_ids(device, root_device_ids); 74 if (ret) 75 return 0; 76 else 77 return 1; 78 } 79 EXPORT_SYMBOL_GPL(acpi_is_root_bridge); 80 81 static acpi_status 82 get_root_bridge_busnr_callback(struct acpi_resource *resource, void *data) 83 { 84 struct resource *res = data; 85 struct acpi_resource_address64 address; 86 acpi_status status; 87 88 status = acpi_resource_to_address64(resource, &address); 89 if (ACPI_FAILURE(status)) 90 return AE_OK; 91 92 if ((address.address.address_length > 0) && 93 (address.resource_type == ACPI_BUS_NUMBER_RANGE)) { 94 res->start = address.address.minimum; 95 res->end = address.address.minimum + address.address.address_length - 1; 96 } 97 98 return AE_OK; 99 } 100 101 static acpi_status try_get_root_bridge_busnr(acpi_handle handle, 102 struct resource *res) 103 { 104 acpi_status status; 105 106 res->start = -1; 107 status = 108 acpi_walk_resources(handle, METHOD_NAME__CRS, 109 get_root_bridge_busnr_callback, res); 110 if (ACPI_FAILURE(status)) 111 return status; 112 if (res->start == -1) 113 return AE_ERROR; 114 return AE_OK; 115 } 116 117 struct pci_osc_bit_struct { 118 u32 bit; 119 char *desc; 120 }; 121 122 static struct pci_osc_bit_struct pci_osc_support_bit[] = { 123 { OSC_PCI_EXT_CONFIG_SUPPORT, "ExtendedConfig" }, 124 { OSC_PCI_ASPM_SUPPORT, "ASPM" }, 125 { OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" }, 126 { OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" }, 127 { OSC_PCI_MSI_SUPPORT, "MSI" }, 128 { OSC_PCI_EDR_SUPPORT, "EDR" }, 129 { OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" }, 130 }; 131 132 static struct pci_osc_bit_struct pci_osc_control_bit[] = { 133 { OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, "PCIeHotplug" }, 134 { OSC_PCI_SHPC_NATIVE_HP_CONTROL, "SHPCHotplug" }, 135 { OSC_PCI_EXPRESS_PME_CONTROL, "PME" }, 136 { OSC_PCI_EXPRESS_AER_CONTROL, "AER" }, 137 { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" }, 138 { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" }, 139 { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" }, 140 }; 141 142 static struct pci_osc_bit_struct cxl_osc_support_bit[] = { 143 { OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT, "CXL11PortRegAccess" }, 144 { OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT, "CXL20PortDevRegAccess" }, 145 { OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT, "CXLProtocolErrorReporting" }, 146 { OSC_CXL_NATIVE_HP_SUPPORT, "CXLNativeHotPlug" }, 147 }; 148 149 static struct pci_osc_bit_struct cxl_osc_control_bit[] = { 150 { OSC_CXL_ERROR_REPORTING_CONTROL, "CXLMemErrorReporting" }, 151 }; 152 153 static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word, 154 struct pci_osc_bit_struct *table, int size) 155 { 156 char buf[80]; 157 int i, len = 0; 158 struct pci_osc_bit_struct *entry; 159 160 buf[0] = '\0'; 161 for (i = 0, entry = table; i < size; i++, entry++) 162 if (word & entry->bit) 163 len += scnprintf(buf + len, sizeof(buf) - len, "%s%s", 164 len ? " " : "", entry->desc); 165 166 dev_info(&root->device->dev, "_OSC: %s [%s]\n", msg, buf); 167 } 168 169 static void decode_osc_support(struct acpi_pci_root *root, char *msg, u32 word) 170 { 171 decode_osc_bits(root, msg, word, pci_osc_support_bit, 172 ARRAY_SIZE(pci_osc_support_bit)); 173 } 174 175 static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word) 176 { 177 decode_osc_bits(root, msg, word, pci_osc_control_bit, 178 ARRAY_SIZE(pci_osc_control_bit)); 179 } 180 181 static void decode_cxl_osc_support(struct acpi_pci_root *root, char *msg, u32 word) 182 { 183 decode_osc_bits(root, msg, word, cxl_osc_support_bit, 184 ARRAY_SIZE(cxl_osc_support_bit)); 185 } 186 187 static void decode_cxl_osc_control(struct acpi_pci_root *root, char *msg, u32 word) 188 { 189 decode_osc_bits(root, msg, word, cxl_osc_control_bit, 190 ARRAY_SIZE(cxl_osc_control_bit)); 191 } 192 193 static inline bool is_pcie(struct acpi_pci_root *root) 194 { 195 return root->bridge_type == ACPI_BRIDGE_TYPE_PCIE; 196 } 197 198 static inline bool is_cxl(struct acpi_pci_root *root) 199 { 200 return root->bridge_type == ACPI_BRIDGE_TYPE_CXL; 201 } 202 203 static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766"; 204 static u8 cxl_osc_uuid_str[] = "68F2D50B-C469-4d8A-BD3D-941A103FD3FC"; 205 206 static char *to_uuid(struct acpi_pci_root *root) 207 { 208 if (is_cxl(root)) 209 return cxl_osc_uuid_str; 210 return pci_osc_uuid_str; 211 } 212 213 static int cap_length(struct acpi_pci_root *root) 214 { 215 if (is_cxl(root)) 216 return sizeof(u32) * OSC_CXL_CAPABILITY_DWORDS; 217 return sizeof(u32) * OSC_PCI_CAPABILITY_DWORDS; 218 } 219 220 static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root, 221 const u32 *capbuf, u32 *pci_control, 222 u32 *cxl_control) 223 { 224 struct acpi_osc_context context = { 225 .uuid_str = to_uuid(root), 226 .rev = 1, 227 .cap.length = cap_length(root), 228 .cap.pointer = (void *)capbuf, 229 }; 230 acpi_status status; 231 232 status = acpi_run_osc(root->device->handle, &context); 233 if (ACPI_SUCCESS(status)) { 234 *pci_control = acpi_osc_ctx_get_pci_control(&context); 235 if (is_cxl(root)) 236 *cxl_control = acpi_osc_ctx_get_cxl_control(&context); 237 kfree(context.ret.pointer); 238 } 239 return status; 240 } 241 242 static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, u32 support, 243 u32 *control, u32 cxl_support, 244 u32 *cxl_control) 245 { 246 acpi_status status; 247 u32 pci_result, cxl_result, capbuf[OSC_CXL_CAPABILITY_DWORDS]; 248 249 support |= root->osc_support_set; 250 251 capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE; 252 capbuf[OSC_SUPPORT_DWORD] = support; 253 capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set; 254 255 if (is_cxl(root)) { 256 cxl_support |= root->osc_ext_support_set; 257 capbuf[OSC_EXT_SUPPORT_DWORD] = cxl_support; 258 capbuf[OSC_EXT_CONTROL_DWORD] = *cxl_control | root->osc_ext_control_set; 259 } 260 261 retry: 262 status = acpi_pci_run_osc(root, capbuf, &pci_result, &cxl_result); 263 if (ACPI_SUCCESS(status)) { 264 root->osc_support_set = support; 265 *control = pci_result; 266 if (is_cxl(root)) { 267 root->osc_ext_support_set = cxl_support; 268 *cxl_control = cxl_result; 269 } 270 } else if (is_cxl(root)) { 271 /* 272 * CXL _OSC is optional on CXL 1.1 hosts. Fall back to PCIe _OSC 273 * upon any failure using CXL _OSC. 274 */ 275 root->bridge_type = ACPI_BRIDGE_TYPE_PCIE; 276 goto retry; 277 } 278 return status; 279 } 280 281 struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle) 282 { 283 struct acpi_device *device = acpi_fetch_acpi_dev(handle); 284 struct acpi_pci_root *root; 285 286 if (!device || acpi_match_device_ids(device, root_device_ids)) 287 return NULL; 288 289 root = acpi_driver_data(device); 290 291 return root; 292 } 293 EXPORT_SYMBOL_GPL(acpi_pci_find_root); 294 295 /** 296 * acpi_dev_get_pci_dev - Get a struct pci_dev for a given ACPI device 297 * @adev: Target ACPI device. 298 * 299 * Find the PCI device associated with @adev, if any, and bump up its reference 300 * counter. 301 * 302 * Callers are responsible for dropping the PCI device reference obtained by 303 * this function. 304 * 305 * Return: The struct pci_dev pointer of a reference-counted PCI device on 306 * success or NULL on failure. 307 */ 308 struct pci_dev *acpi_dev_get_pci_dev(struct acpi_device *adev) 309 { 310 struct acpi_device_physical_node *pn; 311 312 if (!adev) 313 return NULL; 314 315 guard(mutex)(&adev->physical_node_lock); 316 317 list_for_each_entry(pn, &adev->physical_node_list, node) { 318 if (dev_is_pci(pn->dev)) { 319 get_device(pn->dev); 320 return to_pci_dev(pn->dev); 321 } 322 } 323 324 return NULL; 325 } 326 EXPORT_SYMBOL_GPL(acpi_dev_get_pci_dev); 327 328 /** 329 * acpi_pci_osc_control_set - Request control of PCI root _OSC features. 330 * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex). 331 * @mask: Mask of _OSC bits to request control of, place to store control mask. 332 * @support: _OSC supported capability. 333 * @cxl_mask: Mask of CXL _OSC control bits, place to store control mask. 334 * @cxl_support: CXL _OSC supported capability. 335 * 336 * Run _OSC query for @mask and if that is successful, compare the returned 337 * mask of control bits with @req. If all of the @req bits are set in the 338 * returned mask, run _OSC request for it. 339 * 340 * The variable at the @mask address may be modified regardless of whether or 341 * not the function returns success. On success it will contain the mask of 342 * _OSC bits the BIOS has granted control of, but its contents are meaningless 343 * on failure. 344 **/ 345 static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, 346 u32 support, u32 *cxl_mask, 347 u32 cxl_support) 348 { 349 u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL; 350 struct acpi_pci_root *root; 351 acpi_status status; 352 u32 ctrl, cxl_ctrl = 0, capbuf[OSC_CXL_CAPABILITY_DWORDS]; 353 354 if (!mask) 355 return AE_BAD_PARAMETER; 356 357 root = acpi_pci_find_root(handle); 358 if (!root) 359 return AE_NOT_EXIST; 360 361 ctrl = *mask; 362 *mask |= root->osc_control_set; 363 364 if (is_cxl(root)) { 365 cxl_ctrl = *cxl_mask; 366 *cxl_mask |= root->osc_ext_control_set; 367 } 368 369 /* Need to check the available controls bits before requesting them. */ 370 do { 371 u32 pci_missing = 0, cxl_missing = 0; 372 373 status = acpi_pci_query_osc(root, support, mask, cxl_support, 374 cxl_mask); 375 if (ACPI_FAILURE(status)) 376 return status; 377 if (is_cxl(root)) { 378 if (ctrl == *mask && cxl_ctrl == *cxl_mask) 379 break; 380 pci_missing = ctrl & ~(*mask); 381 cxl_missing = cxl_ctrl & ~(*cxl_mask); 382 } else { 383 if (ctrl == *mask) 384 break; 385 pci_missing = ctrl & ~(*mask); 386 } 387 if (pci_missing) 388 decode_osc_control(root, "platform does not support", 389 pci_missing); 390 if (cxl_missing) 391 decode_cxl_osc_control(root, "CXL platform does not support", 392 cxl_missing); 393 ctrl = *mask; 394 cxl_ctrl = *cxl_mask; 395 } while (*mask || *cxl_mask); 396 397 /* No need to request _OSC if the control was already granted. */ 398 if ((root->osc_control_set & ctrl) == ctrl && 399 (root->osc_ext_control_set & cxl_ctrl) == cxl_ctrl) 400 return AE_OK; 401 402 if ((ctrl & req) != req) { 403 decode_osc_control(root, "not requesting control; platform does not support", 404 req & ~(ctrl)); 405 return AE_SUPPORT; 406 } 407 408 capbuf[OSC_QUERY_DWORD] = 0; 409 capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set; 410 capbuf[OSC_CONTROL_DWORD] = ctrl; 411 if (is_cxl(root)) { 412 capbuf[OSC_EXT_SUPPORT_DWORD] = root->osc_ext_support_set; 413 capbuf[OSC_EXT_CONTROL_DWORD] = cxl_ctrl; 414 } 415 416 status = acpi_pci_run_osc(root, capbuf, mask, cxl_mask); 417 if (ACPI_FAILURE(status)) 418 return status; 419 420 root->osc_control_set = *mask; 421 root->osc_ext_control_set = *cxl_mask; 422 return AE_OK; 423 } 424 425 static u32 calculate_support(void) 426 { 427 u32 support; 428 429 /* 430 * All supported architectures that use ACPI have support for 431 * PCI domains, so we indicate this in _OSC support capabilities. 432 */ 433 support = OSC_PCI_SEGMENT_GROUPS_SUPPORT; 434 support |= OSC_PCI_HPX_TYPE_3_SUPPORT; 435 if (pci_ext_cfg_avail()) 436 support |= OSC_PCI_EXT_CONFIG_SUPPORT; 437 if (pcie_aspm_support_enabled()) 438 support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT; 439 if (pci_msi_enabled()) 440 support |= OSC_PCI_MSI_SUPPORT; 441 if (IS_ENABLED(CONFIG_PCIE_EDR)) 442 support |= OSC_PCI_EDR_SUPPORT; 443 444 return support; 445 } 446 447 /* 448 * Background on hotplug support, and making it depend on only 449 * CONFIG_HOTPLUG_PCI_PCIE vs. also considering CONFIG_MEMORY_HOTPLUG: 450 * 451 * CONFIG_ACPI_HOTPLUG_MEMORY does depend on CONFIG_MEMORY_HOTPLUG, but 452 * there is no existing _OSC for memory hotplug support. The reason is that 453 * ACPI memory hotplug requires the OS to acknowledge / coordinate with 454 * memory plug events via a scan handler. On the CXL side the equivalent 455 * would be if Linux supported the Mechanical Retention Lock [1], or 456 * otherwise had some coordination for the driver of a PCI device 457 * undergoing hotplug to be consulted on whether the hotplug should 458 * proceed or not. 459 * 460 * The concern is that if Linux says no to supporting CXL hotplug then 461 * the BIOS may say no to giving the OS hotplug control of any other PCIe 462 * device. So the question here is not whether hotplug is enabled, it's 463 * whether it is handled natively by the at all OS, and if 464 * CONFIG_HOTPLUG_PCI_PCIE is enabled then the answer is "yes". 465 * 466 * Otherwise, the plan for CXL coordinated remove, since the kernel does 467 * not support blocking hotplug, is to require the memory device to be 468 * disabled before hotplug is attempted. When CONFIG_MEMORY_HOTPLUG is 469 * disabled that step will fail and the remove attempt cancelled by the 470 * user. If that is not honored and the card is removed anyway then it 471 * does not matter if CONFIG_MEMORY_HOTPLUG is enabled or not, it will 472 * cause a crash and other badness. 473 * 474 * Therefore, just say yes to CXL hotplug and require removal to 475 * be coordinated by userspace unless and until the kernel grows better 476 * mechanisms for doing "managed" removal of devices in consultation with 477 * the driver. 478 * 479 * [1]: https://lore.kernel.org/all/20201122014203.4706-1-ashok.raj@intel.com/ 480 */ 481 static u32 calculate_cxl_support(void) 482 { 483 u32 support; 484 485 support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT; 486 support |= OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT; 487 if (pci_aer_available()) 488 support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT; 489 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) 490 support |= OSC_CXL_NATIVE_HP_SUPPORT; 491 492 return support; 493 } 494 495 static u32 calculate_control(void) 496 { 497 u32 control; 498 499 control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL 500 | OSC_PCI_EXPRESS_PME_CONTROL; 501 502 if (IS_ENABLED(CONFIG_PCIEASPM)) 503 control |= OSC_PCI_EXPRESS_LTR_CONTROL; 504 505 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) 506 control |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL; 507 508 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC)) 509 control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL; 510 511 if (pci_aer_available()) 512 control |= OSC_PCI_EXPRESS_AER_CONTROL; 513 514 /* 515 * Per the Downstream Port Containment Related Enhancements ECN to 516 * the PCI Firmware Spec, r3.2, sec 4.5.1, table 4-5, 517 * OSC_PCI_EXPRESS_DPC_CONTROL indicates the OS supports both DPC 518 * and EDR. 519 */ 520 if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR)) 521 control |= OSC_PCI_EXPRESS_DPC_CONTROL; 522 523 return control; 524 } 525 526 static u32 calculate_cxl_control(void) 527 { 528 u32 control = 0; 529 530 if (IS_ENABLED(CONFIG_MEMORY_FAILURE)) 531 control |= OSC_CXL_ERROR_REPORTING_CONTROL; 532 533 return control; 534 } 535 536 static bool os_control_query_checks(struct acpi_pci_root *root, u32 support) 537 { 538 struct acpi_device *device = root->device; 539 540 if (pcie_ports_disabled) { 541 dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n"); 542 return false; 543 } 544 545 if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) { 546 decode_osc_support(root, "not requesting OS control; OS requires", 547 ACPI_PCIE_REQ_SUPPORT); 548 return false; 549 } 550 551 return true; 552 } 553 554 static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm) 555 { 556 u32 support, control = 0, requested = 0; 557 u32 cxl_support = 0, cxl_control = 0, cxl_requested = 0; 558 acpi_status status; 559 struct acpi_device *device = root->device; 560 acpi_handle handle = device->handle; 561 562 /* 563 * Apple always return failure on _OSC calls when _OSI("Darwin") has 564 * been called successfully. We know the feature set supported by the 565 * platform, so avoid calling _OSC at all 566 */ 567 if (x86_apple_machine) { 568 root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL; 569 decode_osc_control(root, "OS assumes control of", 570 root->osc_control_set); 571 return; 572 } 573 574 if (!is_pcie(root) && !is_cxl(root) && !acpi_has_method(handle, "_OSC")) { 575 dev_dbg(&device->dev, "Non-PCIe host bridge without _OSC, skipping\n"); 576 577 *no_aspm = 1; 578 return; 579 } 580 581 support = calculate_support(); 582 583 decode_osc_support(root, "OS supports", support); 584 585 if (os_control_query_checks(root, support)) 586 requested = control = calculate_control(); 587 588 if (is_cxl(root)) { 589 cxl_support = calculate_cxl_support(); 590 decode_cxl_osc_support(root, "OS supports", cxl_support); 591 cxl_requested = cxl_control = calculate_cxl_control(); 592 } 593 594 status = acpi_pci_osc_control_set(handle, &control, support, 595 &cxl_control, cxl_support); 596 if (ACPI_SUCCESS(status)) { 597 if (control) 598 decode_osc_control(root, "OS now controls", control); 599 if (cxl_control) 600 decode_cxl_osc_control(root, "OS now controls", 601 cxl_control); 602 603 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) { 604 /* 605 * We have ASPM control, but the FADT indicates that 606 * it's unsupported. Leave existing configuration 607 * intact and prevent the OS from touching it. 608 */ 609 dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n"); 610 *no_aspm = 1; 611 } 612 } else { 613 /* 614 * We want to disable ASPM here, but aspm_disabled 615 * needs to remain in its state from boot so that we 616 * properly handle PCIe 1.1 devices. So we set this 617 * flag here, to defer the action until after the ACPI 618 * root scan. 619 */ 620 *no_aspm = 1; 621 622 if (control) { 623 decode_osc_control(root, "OS requested", requested); 624 decode_osc_control(root, "platform willing to grant", control); 625 } 626 if (cxl_control) { 627 decode_cxl_osc_control(root, "OS requested", cxl_requested); 628 decode_cxl_osc_control(root, "platform willing to grant", 629 cxl_control); 630 } 631 632 dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n", 633 acpi_format_exception(status)); 634 } 635 } 636 637 static int acpi_pci_root_add(struct acpi_device *device, 638 const struct acpi_device_id *not_used) 639 { 640 unsigned long long segment, bus; 641 acpi_status status; 642 int result; 643 struct acpi_pci_root *root; 644 acpi_handle handle = device->handle; 645 int no_aspm = 0; 646 bool hotadd = system_state == SYSTEM_RUNNING; 647 const char *acpi_hid; 648 649 root = kzalloc_obj(struct acpi_pci_root); 650 if (!root) 651 return -ENOMEM; 652 653 segment = 0; 654 status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL, 655 &segment); 656 if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { 657 dev_err(&device->dev, "can't evaluate _SEG\n"); 658 result = -ENODEV; 659 goto end; 660 } 661 662 /* Check _CRS first, then _BBN. If no _BBN, default to zero. */ 663 root->secondary.flags = IORESOURCE_BUS; 664 status = try_get_root_bridge_busnr(handle, &root->secondary); 665 if (ACPI_FAILURE(status)) { 666 /* 667 * We need both the start and end of the downstream bus range 668 * to interpret _CBA (MMCONFIG base address), so it really is 669 * supposed to be in _CRS. If we don't find it there, all we 670 * can do is assume [_BBN-0xFF] or [0-0xFF]. 671 */ 672 root->secondary.end = 0xFF; 673 dev_warn(&device->dev, 674 FW_BUG "no secondary bus range in _CRS\n"); 675 status = acpi_evaluate_integer(handle, METHOD_NAME__BBN, 676 NULL, &bus); 677 if (ACPI_SUCCESS(status)) 678 root->secondary.start = bus; 679 else if (status == AE_NOT_FOUND) 680 root->secondary.start = 0; 681 else { 682 dev_err(&device->dev, "can't evaluate _BBN\n"); 683 result = -ENODEV; 684 goto end; 685 } 686 } 687 688 root->device = device; 689 root->segment = segment & 0xFFFF; 690 device->driver_data = root; 691 692 if (hotadd && dmar_device_add(handle)) { 693 result = -ENXIO; 694 goto end; 695 } 696 697 pr_info("PCI Root Bridge [%s] (domain %04x %pR)\n", 698 acpi_device_bid(device), root->segment, &root->secondary); 699 700 root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle); 701 702 acpi_hid = acpi_device_hid(root->device); 703 if (strcmp(acpi_hid, "PNP0A08") == 0) 704 root->bridge_type = ACPI_BRIDGE_TYPE_PCIE; 705 else if (strcmp(acpi_hid, "ACPI0016") == 0) 706 root->bridge_type = ACPI_BRIDGE_TYPE_CXL; 707 else 708 dev_dbg(&device->dev, "Assuming non-PCIe host bridge\n"); 709 710 negotiate_os_control(root, &no_aspm); 711 712 /* 713 * TBD: Need PCI interface for enumeration/configuration of roots. 714 */ 715 716 /* 717 * Scan the Root Bridge 718 * -------------------- 719 * Must do this prior to any attempt to bind the root device, as the 720 * PCI namespace does not get created until this call is made (and 721 * thus the root bridge's pci_dev does not exist). 722 */ 723 root->bus = pci_acpi_scan_root(root); 724 if (!root->bus) { 725 dev_err(&device->dev, 726 "Bus %04x:%02x not present in PCI namespace\n", 727 root->segment, (unsigned int)root->secondary.start); 728 result = -ENODEV; 729 goto remove_dmar; 730 } 731 732 if (no_aspm) 733 pcie_no_aspm(); 734 735 pci_acpi_add_root_pm_notifier(device, root); 736 device_set_wakeup_capable(root->bus->bridge, device->wakeup.flags.valid); 737 738 if (hotadd) { 739 pcibios_resource_survey_bus(root->bus); 740 pci_assign_unassigned_root_bus_resources(root->bus); 741 /* 742 * This is only called for the hotadd case. For the boot-time 743 * case, we need to wait until after PCI initialization in 744 * order to deal with IOAPICs mapped in on a PCI BAR. 745 * 746 * This is currently x86-specific, because acpi_ioapic_add() 747 * is an empty function without CONFIG_ACPI_HOTPLUG_IOAPIC. 748 * And CONFIG_ACPI_HOTPLUG_IOAPIC depends on CONFIG_X86_IO_APIC 749 * (see drivers/acpi/Kconfig). 750 */ 751 acpi_ioapic_add(root->device->handle); 752 } 753 754 pci_lock_rescan_remove(); 755 pci_bus_add_devices(root->bus); 756 pci_unlock_rescan_remove(); 757 758 /* Clear _DEP dependencies to allow consumers to enumerate */ 759 acpi_dev_clear_dependencies(device); 760 761 return 1; 762 763 remove_dmar: 764 if (hotadd) 765 dmar_device_remove(handle); 766 end: 767 device->driver_data = NULL; 768 kfree(root); 769 return result; 770 } 771 772 static void acpi_pci_root_remove(struct acpi_device *device) 773 { 774 struct acpi_pci_root *root = acpi_driver_data(device); 775 776 pci_lock_rescan_remove(); 777 778 pci_stop_root_bus(root->bus); 779 780 pci_ioapic_remove(root); 781 device_set_wakeup_capable(root->bus->bridge, false); 782 pci_acpi_remove_bus_pm_notifier(device); 783 784 pci_remove_root_bus(root->bus); 785 WARN_ON(acpi_ioapic_remove(root)); 786 787 dmar_device_remove(device->handle); 788 789 pci_unlock_rescan_remove(); 790 791 device->driver_data = NULL; 792 kfree(root); 793 } 794 795 /* 796 * Following code to support acpi_pci_root_create() is copied from 797 * arch/x86/pci/acpi.c and modified so it could be reused by x86, IA64 798 * and ARM64. 799 */ 800 static void acpi_pci_root_validate_resources(struct device *dev, 801 struct list_head *resources, 802 unsigned long type) 803 { 804 LIST_HEAD(list); 805 struct resource *res1, *res2, *root = NULL; 806 struct resource_entry *tmp, *entry, *entry2; 807 808 BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0); 809 root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource; 810 811 list_splice_init(resources, &list); 812 resource_list_for_each_entry_safe(entry, tmp, &list) { 813 bool free = false; 814 resource_size_t end; 815 816 res1 = entry->res; 817 if (!(res1->flags & type)) 818 goto next; 819 820 /* Exclude non-addressable range or non-addressable portion */ 821 end = min(res1->end, root->end); 822 if (end <= res1->start) { 823 dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n", 824 res1); 825 free = true; 826 goto next; 827 } else if (res1->end != end) { 828 dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n", 829 res1, (unsigned long long)end + 1, 830 (unsigned long long)res1->end); 831 res1->end = end; 832 } 833 834 resource_list_for_each_entry(entry2, resources) { 835 res2 = entry2->res; 836 if (!(res2->flags & type)) 837 continue; 838 839 /* 840 * I don't like throwing away windows because then 841 * our resources no longer match the ACPI _CRS, but 842 * the kernel resource tree doesn't allow overlaps. 843 */ 844 if (resource_union(res1, res2, res2)) { 845 dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n", 846 res2, res1); 847 free = true; 848 goto next; 849 } 850 } 851 852 next: 853 resource_list_del(entry); 854 if (free) 855 resource_list_free_entry(entry); 856 else 857 resource_list_add_tail(entry, resources); 858 } 859 } 860 861 static void acpi_pci_root_remap_iospace(const struct fwnode_handle *fwnode, 862 struct resource_entry *entry) 863 { 864 #ifdef PCI_IOBASE 865 struct resource *res = entry->res; 866 resource_size_t cpu_addr = res->start; 867 resource_size_t pci_addr = cpu_addr - entry->offset; 868 resource_size_t length = resource_size(res); 869 unsigned long port; 870 871 if (pci_register_io_range(fwnode, cpu_addr, length)) 872 goto err; 873 874 port = pci_address_to_pio(cpu_addr); 875 if (port == (unsigned long)-1) 876 goto err; 877 878 res->start = port; 879 res->end = port + length - 1; 880 entry->offset = port - pci_addr; 881 882 if (pci_remap_iospace(res, cpu_addr) < 0) 883 goto err; 884 885 pr_info("Remapped I/O %pa to %pR\n", &cpu_addr, res); 886 return; 887 err: 888 res->flags |= IORESOURCE_DISABLED; 889 #endif 890 } 891 892 int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info) 893 { 894 int ret; 895 struct list_head *list = &info->resources; 896 struct acpi_device *device = info->bridge; 897 struct resource_entry *entry, *tmp; 898 unsigned long flags; 899 900 flags = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT; 901 ret = acpi_dev_get_resources(device, list, 902 acpi_dev_filter_resource_type_cb, 903 (void *)flags); 904 if (ret < 0) 905 dev_warn(&device->dev, 906 "failed to parse _CRS method, error code %d\n", ret); 907 else if (ret == 0) 908 dev_dbg(&device->dev, 909 "no IO and memory resources present in _CRS\n"); 910 else { 911 resource_list_for_each_entry_safe(entry, tmp, list) { 912 if (entry->res->flags & IORESOURCE_IO) 913 acpi_pci_root_remap_iospace(&device->fwnode, 914 entry); 915 916 if (entry->res->flags & IORESOURCE_DISABLED) 917 resource_list_destroy_entry(entry); 918 else 919 entry->res->name = info->name; 920 } 921 acpi_pci_root_validate_resources(&device->dev, list, 922 IORESOURCE_MEM); 923 acpi_pci_root_validate_resources(&device->dev, list, 924 IORESOURCE_IO); 925 } 926 927 return ret; 928 } 929 930 static void pci_acpi_root_add_resources(struct acpi_pci_root_info *info) 931 { 932 struct resource_entry *entry, *tmp; 933 struct resource *res, *conflict, *root = NULL; 934 935 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 936 res = entry->res; 937 if (res->flags & IORESOURCE_MEM) 938 root = &iomem_resource; 939 else if (res->flags & IORESOURCE_IO) 940 root = &ioport_resource; 941 else 942 continue; 943 944 /* 945 * Some legacy x86 host bridge drivers use iomem_resource and 946 * ioport_resource as default resource pool, skip it. 947 */ 948 if (res == root) 949 continue; 950 951 conflict = insert_resource_conflict(root, res); 952 if (conflict) { 953 dev_info(&info->bridge->dev, 954 "ignoring host bridge window %pR (conflicts with %s %pR)\n", 955 res, conflict->name, conflict); 956 resource_list_destroy_entry(entry); 957 } 958 } 959 } 960 961 static void __acpi_pci_root_release_info(struct acpi_pci_root_info *info) 962 { 963 struct resource *res; 964 struct resource_entry *entry, *tmp; 965 966 if (!info) 967 return; 968 969 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 970 res = entry->res; 971 if (res->parent && 972 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 973 release_resource(res); 974 resource_list_destroy_entry(entry); 975 } 976 977 info->ops->release_info(info); 978 } 979 980 static void acpi_pci_root_release_info(struct pci_host_bridge *bridge) 981 { 982 struct resource *res; 983 struct resource_entry *entry; 984 985 resource_list_for_each_entry(entry, &bridge->windows) { 986 res = entry->res; 987 if (res->flags & IORESOURCE_IO) 988 pci_unmap_iospace(res); 989 if (res->parent && 990 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 991 release_resource(res); 992 } 993 __acpi_pci_root_release_info(bridge->release_data); 994 } 995 996 struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, 997 struct acpi_pci_root_ops *ops, 998 struct acpi_pci_root_info *info, 999 void *sysdata) 1000 { 1001 int ret, busnum = root->secondary.start; 1002 struct acpi_device *device = root->device; 1003 int node = acpi_get_node(device->handle); 1004 struct pci_bus *bus; 1005 struct pci_host_bridge *host_bridge; 1006 1007 info->root = root; 1008 info->bridge = device; 1009 info->ops = ops; 1010 INIT_LIST_HEAD(&info->resources); 1011 snprintf(info->name, sizeof(info->name), "PCI Bus %04x:%02x", 1012 root->segment, busnum); 1013 1014 if (ops->init_info && ops->init_info(info)) 1015 goto out_release_info; 1016 if (ops->prepare_resources) 1017 ret = ops->prepare_resources(info); 1018 else 1019 ret = acpi_pci_probe_root_resources(info); 1020 if (ret < 0) 1021 goto out_release_info; 1022 1023 pci_acpi_root_add_resources(info); 1024 pci_add_resource(&info->resources, &root->secondary); 1025 bus = pci_create_root_bus(NULL, busnum, ops->pci_ops, 1026 sysdata, &info->resources); 1027 if (!bus) 1028 goto out_release_info; 1029 1030 host_bridge = to_pci_host_bridge(bus->bridge); 1031 if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) 1032 host_bridge->native_pcie_hotplug = 0; 1033 if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL)) 1034 host_bridge->native_shpc_hotplug = 0; 1035 if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL)) 1036 host_bridge->native_aer = 0; 1037 if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL)) 1038 host_bridge->native_pme = 0; 1039 if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL)) 1040 host_bridge->native_ltr = 0; 1041 if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL)) 1042 host_bridge->native_dpc = 0; 1043 1044 if (!(root->osc_ext_control_set & OSC_CXL_ERROR_REPORTING_CONTROL)) 1045 host_bridge->native_cxl_error = 0; 1046 1047 acpi_dev_power_up_children_with_adr(device); 1048 1049 pci_scan_child_bus(bus); 1050 pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info, 1051 info); 1052 if (node != NUMA_NO_NODE) 1053 dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node); 1054 return bus; 1055 1056 out_release_info: 1057 __acpi_pci_root_release_info(info); 1058 return NULL; 1059 } 1060 1061 void __init acpi_pci_root_init(void) 1062 { 1063 if (acpi_pci_disabled) 1064 return; 1065 1066 pci_acpi_crs_quirks(); 1067 acpi_scan_add_handler_with_hotplug(&pci_root_handler, "pci_root"); 1068 } 1069