1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 40 $) 4 * 5 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> 6 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 7 */ 8 9 #define pr_fmt(fmt) "ACPI: " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/types.h> 15 #include <linux/mutex.h> 16 #include <linux/pm.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pci.h> 19 #include <linux/pci-acpi.h> 20 #include <linux/dmar.h> 21 #include <linux/acpi.h> 22 #include <linux/slab.h> 23 #include <linux/dmi.h> 24 #include <linux/platform_data/x86/apple.h> 25 #include <acpi/apei.h> /* for acpi_hest_init() */ 26 27 #include "internal.h" 28 29 #define ACPI_PCI_ROOT_CLASS "pci_bridge" 30 #define ACPI_PCI_ROOT_DEVICE_NAME "PCI Root Bridge" 31 static int acpi_pci_root_add(struct acpi_device *device, 32 const struct acpi_device_id *not_used); 33 static void acpi_pci_root_remove(struct acpi_device *device); 34 35 static int acpi_pci_root_scan_dependent(struct acpi_device *adev) 36 { 37 acpiphp_check_host_bridge(adev); 38 return 0; 39 } 40 41 #define ACPI_PCIE_REQ_SUPPORT (OSC_PCI_EXT_CONFIG_SUPPORT \ 42 | OSC_PCI_ASPM_SUPPORT \ 43 | OSC_PCI_CLOCK_PM_SUPPORT \ 44 | OSC_PCI_MSI_SUPPORT) 45 46 static const struct acpi_device_id root_device_ids[] = { 47 {"PNP0A03", 0}, 48 {"", 0}, 49 }; 50 51 static struct acpi_scan_handler pci_root_handler = { 52 .ids = root_device_ids, 53 .attach = acpi_pci_root_add, 54 .detach = acpi_pci_root_remove, 55 .hotplug = { 56 .enabled = true, 57 .scan_dependent = acpi_pci_root_scan_dependent, 58 }, 59 }; 60 61 /** 62 * acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge 63 * @handle: the ACPI CA node in question. 64 * 65 * Note: we could make this API take a struct acpi_device * instead, but 66 * for now, it's more convenient to operate on an acpi_handle. 67 */ 68 int acpi_is_root_bridge(acpi_handle handle) 69 { 70 int ret; 71 struct acpi_device *device; 72 73 ret = acpi_bus_get_device(handle, &device); 74 if (ret) 75 return 0; 76 77 ret = acpi_match_device_ids(device, root_device_ids); 78 if (ret) 79 return 0; 80 else 81 return 1; 82 } 83 EXPORT_SYMBOL_GPL(acpi_is_root_bridge); 84 85 static acpi_status 86 get_root_bridge_busnr_callback(struct acpi_resource *resource, void *data) 87 { 88 struct resource *res = data; 89 struct acpi_resource_address64 address; 90 acpi_status status; 91 92 status = acpi_resource_to_address64(resource, &address); 93 if (ACPI_FAILURE(status)) 94 return AE_OK; 95 96 if ((address.address.address_length > 0) && 97 (address.resource_type == ACPI_BUS_NUMBER_RANGE)) { 98 res->start = address.address.minimum; 99 res->end = address.address.minimum + address.address.address_length - 1; 100 } 101 102 return AE_OK; 103 } 104 105 static acpi_status try_get_root_bridge_busnr(acpi_handle handle, 106 struct resource *res) 107 { 108 acpi_status status; 109 110 res->start = -1; 111 status = 112 acpi_walk_resources(handle, METHOD_NAME__CRS, 113 get_root_bridge_busnr_callback, res); 114 if (ACPI_FAILURE(status)) 115 return status; 116 if (res->start == -1) 117 return AE_ERROR; 118 return AE_OK; 119 } 120 121 struct pci_osc_bit_struct { 122 u32 bit; 123 char *desc; 124 }; 125 126 static struct pci_osc_bit_struct pci_osc_support_bit[] = { 127 { OSC_PCI_EXT_CONFIG_SUPPORT, "ExtendedConfig" }, 128 { OSC_PCI_ASPM_SUPPORT, "ASPM" }, 129 { OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" }, 130 { OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" }, 131 { OSC_PCI_MSI_SUPPORT, "MSI" }, 132 { OSC_PCI_EDR_SUPPORT, "EDR" }, 133 { OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" }, 134 }; 135 136 static struct pci_osc_bit_struct pci_osc_control_bit[] = { 137 { OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, "PCIeHotplug" }, 138 { OSC_PCI_SHPC_NATIVE_HP_CONTROL, "SHPCHotplug" }, 139 { OSC_PCI_EXPRESS_PME_CONTROL, "PME" }, 140 { OSC_PCI_EXPRESS_AER_CONTROL, "AER" }, 141 { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" }, 142 { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" }, 143 { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" }, 144 }; 145 146 static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word, 147 struct pci_osc_bit_struct *table, int size) 148 { 149 char buf[80]; 150 int i, len = 0; 151 struct pci_osc_bit_struct *entry; 152 153 buf[0] = '\0'; 154 for (i = 0, entry = table; i < size; i++, entry++) 155 if (word & entry->bit) 156 len += scnprintf(buf + len, sizeof(buf) - len, "%s%s", 157 len ? " " : "", entry->desc); 158 159 dev_info(&root->device->dev, "_OSC: %s [%s]\n", msg, buf); 160 } 161 162 static void decode_osc_support(struct acpi_pci_root *root, char *msg, u32 word) 163 { 164 decode_osc_bits(root, msg, word, pci_osc_support_bit, 165 ARRAY_SIZE(pci_osc_support_bit)); 166 } 167 168 static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word) 169 { 170 decode_osc_bits(root, msg, word, pci_osc_control_bit, 171 ARRAY_SIZE(pci_osc_control_bit)); 172 } 173 174 static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766"; 175 176 static acpi_status acpi_pci_run_osc(acpi_handle handle, 177 const u32 *capbuf, u32 *retval) 178 { 179 struct acpi_osc_context context = { 180 .uuid_str = pci_osc_uuid_str, 181 .rev = 1, 182 .cap.length = 12, 183 .cap.pointer = (void *)capbuf, 184 }; 185 acpi_status status; 186 187 status = acpi_run_osc(handle, &context); 188 if (ACPI_SUCCESS(status)) { 189 *retval = *((u32 *)(context.ret.pointer + 8)); 190 kfree(context.ret.pointer); 191 } 192 return status; 193 } 194 195 static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, 196 u32 support, 197 u32 *control) 198 { 199 acpi_status status; 200 u32 result, capbuf[3]; 201 202 support |= root->osc_support_set; 203 204 capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE; 205 capbuf[OSC_SUPPORT_DWORD] = support; 206 capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set; 207 208 status = acpi_pci_run_osc(root->device->handle, capbuf, &result); 209 if (ACPI_SUCCESS(status)) { 210 root->osc_support_set = support; 211 *control = result; 212 } 213 return status; 214 } 215 216 struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle) 217 { 218 struct acpi_pci_root *root; 219 struct acpi_device *device; 220 221 if (acpi_bus_get_device(handle, &device) || 222 acpi_match_device_ids(device, root_device_ids)) 223 return NULL; 224 225 root = acpi_driver_data(device); 226 227 return root; 228 } 229 EXPORT_SYMBOL_GPL(acpi_pci_find_root); 230 231 struct acpi_handle_node { 232 struct list_head node; 233 acpi_handle handle; 234 }; 235 236 /** 237 * acpi_get_pci_dev - convert ACPI CA handle to struct pci_dev 238 * @handle: the handle in question 239 * 240 * Given an ACPI CA handle, the desired PCI device is located in the 241 * list of PCI devices. 242 * 243 * If the device is found, its reference count is increased and this 244 * function returns a pointer to its data structure. The caller must 245 * decrement the reference count by calling pci_dev_put(). 246 * If no device is found, %NULL is returned. 247 */ 248 struct pci_dev *acpi_get_pci_dev(acpi_handle handle) 249 { 250 int dev, fn; 251 unsigned long long adr; 252 acpi_status status; 253 acpi_handle phandle; 254 struct pci_bus *pbus; 255 struct pci_dev *pdev = NULL; 256 struct acpi_handle_node *node, *tmp; 257 struct acpi_pci_root *root; 258 LIST_HEAD(device_list); 259 260 /* 261 * Walk up the ACPI CA namespace until we reach a PCI root bridge. 262 */ 263 phandle = handle; 264 while (!acpi_is_root_bridge(phandle)) { 265 node = kzalloc(sizeof(struct acpi_handle_node), GFP_KERNEL); 266 if (!node) 267 goto out; 268 269 INIT_LIST_HEAD(&node->node); 270 node->handle = phandle; 271 list_add(&node->node, &device_list); 272 273 status = acpi_get_parent(phandle, &phandle); 274 if (ACPI_FAILURE(status)) 275 goto out; 276 } 277 278 root = acpi_pci_find_root(phandle); 279 if (!root) 280 goto out; 281 282 pbus = root->bus; 283 284 /* 285 * Now, walk back down the PCI device tree until we return to our 286 * original handle. Assumes that everything between the PCI root 287 * bridge and the device we're looking for must be a P2P bridge. 288 */ 289 list_for_each_entry(node, &device_list, node) { 290 acpi_handle hnd = node->handle; 291 status = acpi_evaluate_integer(hnd, "_ADR", NULL, &adr); 292 if (ACPI_FAILURE(status)) 293 goto out; 294 dev = (adr >> 16) & 0xffff; 295 fn = adr & 0xffff; 296 297 pdev = pci_get_slot(pbus, PCI_DEVFN(dev, fn)); 298 if (!pdev || hnd == handle) 299 break; 300 301 pbus = pdev->subordinate; 302 pci_dev_put(pdev); 303 304 /* 305 * This function may be called for a non-PCI device that has a 306 * PCI parent (eg. a disk under a PCI SATA controller). In that 307 * case pdev->subordinate will be NULL for the parent. 308 */ 309 if (!pbus) { 310 dev_dbg(&pdev->dev, "Not a PCI-to-PCI bridge\n"); 311 pdev = NULL; 312 break; 313 } 314 } 315 out: 316 list_for_each_entry_safe(node, tmp, &device_list, node) 317 kfree(node); 318 319 return pdev; 320 } 321 EXPORT_SYMBOL_GPL(acpi_get_pci_dev); 322 323 /** 324 * acpi_pci_osc_control_set - Request control of PCI root _OSC features. 325 * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex). 326 * @mask: Mask of _OSC bits to request control of, place to store control mask. 327 * @req: Mask of _OSC bits the control of is essential to the caller. 328 * 329 * Run _OSC query for @mask and if that is successful, compare the returned 330 * mask of control bits with @req. If all of the @req bits are set in the 331 * returned mask, run _OSC request for it. 332 * 333 * The variable at the @mask address may be modified regardless of whether or 334 * not the function returns success. On success it will contain the mask of 335 * _OSC bits the BIOS has granted control of, but its contents are meaningless 336 * on failure. 337 **/ 338 static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 support) 339 { 340 u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL; 341 struct acpi_pci_root *root; 342 acpi_status status; 343 u32 ctrl, capbuf[3]; 344 345 if (!mask) 346 return AE_BAD_PARAMETER; 347 348 root = acpi_pci_find_root(handle); 349 if (!root) 350 return AE_NOT_EXIST; 351 352 ctrl = *mask; 353 *mask |= root->osc_control_set; 354 355 /* Need to check the available controls bits before requesting them. */ 356 do { 357 status = acpi_pci_query_osc(root, support, mask); 358 if (ACPI_FAILURE(status)) 359 return status; 360 if (ctrl == *mask) 361 break; 362 decode_osc_control(root, "platform does not support", 363 ctrl & ~(*mask)); 364 ctrl = *mask; 365 } while (*mask); 366 367 /* No need to request _OSC if the control was already granted. */ 368 if ((root->osc_control_set & ctrl) == ctrl) 369 return AE_OK; 370 371 if ((ctrl & req) != req) { 372 decode_osc_control(root, "not requesting control; platform does not support", 373 req & ~(ctrl)); 374 return AE_SUPPORT; 375 } 376 377 capbuf[OSC_QUERY_DWORD] = 0; 378 capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set; 379 capbuf[OSC_CONTROL_DWORD] = ctrl; 380 status = acpi_pci_run_osc(handle, capbuf, mask); 381 if (ACPI_FAILURE(status)) 382 return status; 383 384 root->osc_control_set = *mask; 385 return AE_OK; 386 } 387 388 static u32 calculate_support(void) 389 { 390 u32 support; 391 392 /* 393 * All supported architectures that use ACPI have support for 394 * PCI domains, so we indicate this in _OSC support capabilities. 395 */ 396 support = OSC_PCI_SEGMENT_GROUPS_SUPPORT; 397 support |= OSC_PCI_HPX_TYPE_3_SUPPORT; 398 if (pci_ext_cfg_avail()) 399 support |= OSC_PCI_EXT_CONFIG_SUPPORT; 400 if (pcie_aspm_support_enabled()) 401 support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT; 402 if (pci_msi_enabled()) 403 support |= OSC_PCI_MSI_SUPPORT; 404 if (IS_ENABLED(CONFIG_PCIE_EDR)) 405 support |= OSC_PCI_EDR_SUPPORT; 406 407 return support; 408 } 409 410 static u32 calculate_control(void) 411 { 412 u32 control; 413 414 control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL 415 | OSC_PCI_EXPRESS_PME_CONTROL; 416 417 if (IS_ENABLED(CONFIG_PCIEASPM)) 418 control |= OSC_PCI_EXPRESS_LTR_CONTROL; 419 420 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) 421 control |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL; 422 423 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC)) 424 control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL; 425 426 if (pci_aer_available()) 427 control |= OSC_PCI_EXPRESS_AER_CONTROL; 428 429 /* 430 * Per the Downstream Port Containment Related Enhancements ECN to 431 * the PCI Firmware Spec, r3.2, sec 4.5.1, table 4-5, 432 * OSC_PCI_EXPRESS_DPC_CONTROL indicates the OS supports both DPC 433 * and EDR. 434 */ 435 if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR)) 436 control |= OSC_PCI_EXPRESS_DPC_CONTROL; 437 438 return control; 439 } 440 441 static bool os_control_query_checks(struct acpi_pci_root *root, u32 support) 442 { 443 struct acpi_device *device = root->device; 444 445 if (pcie_ports_disabled) { 446 dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n"); 447 return false; 448 } 449 450 if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) { 451 decode_osc_support(root, "not requesting OS control; OS requires", 452 ACPI_PCIE_REQ_SUPPORT); 453 return false; 454 } 455 456 return true; 457 } 458 459 static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm, 460 bool is_pcie) 461 { 462 u32 support, control = 0, requested = 0; 463 acpi_status status; 464 struct acpi_device *device = root->device; 465 acpi_handle handle = device->handle; 466 467 /* 468 * Apple always return failure on _OSC calls when _OSI("Darwin") has 469 * been called successfully. We know the feature set supported by the 470 * platform, so avoid calling _OSC at all 471 */ 472 if (x86_apple_machine) { 473 root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL; 474 decode_osc_control(root, "OS assumes control of", 475 root->osc_control_set); 476 return; 477 } 478 479 support = calculate_support(); 480 481 decode_osc_support(root, "OS supports", support); 482 483 if (os_control_query_checks(root, support)) 484 requested = control = calculate_control(); 485 486 status = acpi_pci_osc_control_set(handle, &control, support); 487 if (ACPI_SUCCESS(status)) { 488 if (control) 489 decode_osc_control(root, "OS now controls", control); 490 491 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) { 492 /* 493 * We have ASPM control, but the FADT indicates that 494 * it's unsupported. Leave existing configuration 495 * intact and prevent the OS from touching it. 496 */ 497 dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n"); 498 *no_aspm = 1; 499 } 500 } else { 501 /* 502 * We want to disable ASPM here, but aspm_disabled 503 * needs to remain in its state from boot so that we 504 * properly handle PCIe 1.1 devices. So we set this 505 * flag here, to defer the action until after the ACPI 506 * root scan. 507 */ 508 *no_aspm = 1; 509 510 /* _OSC is optional for PCI host bridges */ 511 if ((status == AE_NOT_FOUND) && !is_pcie) 512 return; 513 514 if (control) { 515 decode_osc_control(root, "OS requested", requested); 516 decode_osc_control(root, "platform willing to grant", control); 517 } 518 519 dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n", 520 acpi_format_exception(status)); 521 } 522 } 523 524 static int acpi_pci_root_add(struct acpi_device *device, 525 const struct acpi_device_id *not_used) 526 { 527 unsigned long long segment, bus; 528 acpi_status status; 529 int result; 530 struct acpi_pci_root *root; 531 acpi_handle handle = device->handle; 532 int no_aspm = 0; 533 bool hotadd = system_state == SYSTEM_RUNNING; 534 bool is_pcie; 535 536 root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL); 537 if (!root) 538 return -ENOMEM; 539 540 segment = 0; 541 status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL, 542 &segment); 543 if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { 544 dev_err(&device->dev, "can't evaluate _SEG\n"); 545 result = -ENODEV; 546 goto end; 547 } 548 549 /* Check _CRS first, then _BBN. If no _BBN, default to zero. */ 550 root->secondary.flags = IORESOURCE_BUS; 551 status = try_get_root_bridge_busnr(handle, &root->secondary); 552 if (ACPI_FAILURE(status)) { 553 /* 554 * We need both the start and end of the downstream bus range 555 * to interpret _CBA (MMCONFIG base address), so it really is 556 * supposed to be in _CRS. If we don't find it there, all we 557 * can do is assume [_BBN-0xFF] or [0-0xFF]. 558 */ 559 root->secondary.end = 0xFF; 560 dev_warn(&device->dev, 561 FW_BUG "no secondary bus range in _CRS\n"); 562 status = acpi_evaluate_integer(handle, METHOD_NAME__BBN, 563 NULL, &bus); 564 if (ACPI_SUCCESS(status)) 565 root->secondary.start = bus; 566 else if (status == AE_NOT_FOUND) 567 root->secondary.start = 0; 568 else { 569 dev_err(&device->dev, "can't evaluate _BBN\n"); 570 result = -ENODEV; 571 goto end; 572 } 573 } 574 575 root->device = device; 576 root->segment = segment & 0xFFFF; 577 strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME); 578 strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS); 579 device->driver_data = root; 580 581 if (hotadd && dmar_device_add(handle)) { 582 result = -ENXIO; 583 goto end; 584 } 585 586 pr_info("%s [%s] (domain %04x %pR)\n", 587 acpi_device_name(device), acpi_device_bid(device), 588 root->segment, &root->secondary); 589 590 root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle); 591 592 is_pcie = strcmp(acpi_device_hid(device), "PNP0A08") == 0; 593 negotiate_os_control(root, &no_aspm, is_pcie); 594 595 /* 596 * TBD: Need PCI interface for enumeration/configuration of roots. 597 */ 598 599 /* 600 * Scan the Root Bridge 601 * -------------------- 602 * Must do this prior to any attempt to bind the root device, as the 603 * PCI namespace does not get created until this call is made (and 604 * thus the root bridge's pci_dev does not exist). 605 */ 606 root->bus = pci_acpi_scan_root(root); 607 if (!root->bus) { 608 dev_err(&device->dev, 609 "Bus %04x:%02x not present in PCI namespace\n", 610 root->segment, (unsigned int)root->secondary.start); 611 device->driver_data = NULL; 612 result = -ENODEV; 613 goto remove_dmar; 614 } 615 616 if (no_aspm) 617 pcie_no_aspm(); 618 619 pci_acpi_add_bus_pm_notifier(device); 620 device_set_wakeup_capable(root->bus->bridge, device->wakeup.flags.valid); 621 622 if (hotadd) { 623 pcibios_resource_survey_bus(root->bus); 624 pci_assign_unassigned_root_bus_resources(root->bus); 625 /* 626 * This is only called for the hotadd case. For the boot-time 627 * case, we need to wait until after PCI initialization in 628 * order to deal with IOAPICs mapped in on a PCI BAR. 629 * 630 * This is currently x86-specific, because acpi_ioapic_add() 631 * is an empty function without CONFIG_ACPI_HOTPLUG_IOAPIC. 632 * And CONFIG_ACPI_HOTPLUG_IOAPIC depends on CONFIG_X86_IO_APIC 633 * (see drivers/acpi/Kconfig). 634 */ 635 acpi_ioapic_add(root->device->handle); 636 } 637 638 pci_lock_rescan_remove(); 639 pci_bus_add_devices(root->bus); 640 pci_unlock_rescan_remove(); 641 return 1; 642 643 remove_dmar: 644 if (hotadd) 645 dmar_device_remove(handle); 646 end: 647 kfree(root); 648 return result; 649 } 650 651 static void acpi_pci_root_remove(struct acpi_device *device) 652 { 653 struct acpi_pci_root *root = acpi_driver_data(device); 654 655 pci_lock_rescan_remove(); 656 657 pci_stop_root_bus(root->bus); 658 659 pci_ioapic_remove(root); 660 device_set_wakeup_capable(root->bus->bridge, false); 661 pci_acpi_remove_bus_pm_notifier(device); 662 663 pci_remove_root_bus(root->bus); 664 WARN_ON(acpi_ioapic_remove(root)); 665 666 dmar_device_remove(device->handle); 667 668 pci_unlock_rescan_remove(); 669 670 kfree(root); 671 } 672 673 /* 674 * Following code to support acpi_pci_root_create() is copied from 675 * arch/x86/pci/acpi.c and modified so it could be reused by x86, IA64 676 * and ARM64. 677 */ 678 static void acpi_pci_root_validate_resources(struct device *dev, 679 struct list_head *resources, 680 unsigned long type) 681 { 682 LIST_HEAD(list); 683 struct resource *res1, *res2, *root = NULL; 684 struct resource_entry *tmp, *entry, *entry2; 685 686 BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0); 687 root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource; 688 689 list_splice_init(resources, &list); 690 resource_list_for_each_entry_safe(entry, tmp, &list) { 691 bool free = false; 692 resource_size_t end; 693 694 res1 = entry->res; 695 if (!(res1->flags & type)) 696 goto next; 697 698 /* Exclude non-addressable range or non-addressable portion */ 699 end = min(res1->end, root->end); 700 if (end <= res1->start) { 701 dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n", 702 res1); 703 free = true; 704 goto next; 705 } else if (res1->end != end) { 706 dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n", 707 res1, (unsigned long long)end + 1, 708 (unsigned long long)res1->end); 709 res1->end = end; 710 } 711 712 resource_list_for_each_entry(entry2, resources) { 713 res2 = entry2->res; 714 if (!(res2->flags & type)) 715 continue; 716 717 /* 718 * I don't like throwing away windows because then 719 * our resources no longer match the ACPI _CRS, but 720 * the kernel resource tree doesn't allow overlaps. 721 */ 722 if (resource_union(res1, res2, res2)) { 723 dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n", 724 res2, res1); 725 free = true; 726 goto next; 727 } 728 } 729 730 next: 731 resource_list_del(entry); 732 if (free) 733 resource_list_free_entry(entry); 734 else 735 resource_list_add_tail(entry, resources); 736 } 737 } 738 739 static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode, 740 struct resource_entry *entry) 741 { 742 #ifdef PCI_IOBASE 743 struct resource *res = entry->res; 744 resource_size_t cpu_addr = res->start; 745 resource_size_t pci_addr = cpu_addr - entry->offset; 746 resource_size_t length = resource_size(res); 747 unsigned long port; 748 749 if (pci_register_io_range(fwnode, cpu_addr, length)) 750 goto err; 751 752 port = pci_address_to_pio(cpu_addr); 753 if (port == (unsigned long)-1) 754 goto err; 755 756 res->start = port; 757 res->end = port + length - 1; 758 entry->offset = port - pci_addr; 759 760 if (pci_remap_iospace(res, cpu_addr) < 0) 761 goto err; 762 763 pr_info("Remapped I/O %pa to %pR\n", &cpu_addr, res); 764 return; 765 err: 766 res->flags |= IORESOURCE_DISABLED; 767 #endif 768 } 769 770 int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info) 771 { 772 int ret; 773 struct list_head *list = &info->resources; 774 struct acpi_device *device = info->bridge; 775 struct resource_entry *entry, *tmp; 776 unsigned long flags; 777 778 flags = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT; 779 ret = acpi_dev_get_resources(device, list, 780 acpi_dev_filter_resource_type_cb, 781 (void *)flags); 782 if (ret < 0) 783 dev_warn(&device->dev, 784 "failed to parse _CRS method, error code %d\n", ret); 785 else if (ret == 0) 786 dev_dbg(&device->dev, 787 "no IO and memory resources present in _CRS\n"); 788 else { 789 resource_list_for_each_entry_safe(entry, tmp, list) { 790 if (entry->res->flags & IORESOURCE_IO) 791 acpi_pci_root_remap_iospace(&device->fwnode, 792 entry); 793 794 if (entry->res->flags & IORESOURCE_DISABLED) 795 resource_list_destroy_entry(entry); 796 else 797 entry->res->name = info->name; 798 } 799 acpi_pci_root_validate_resources(&device->dev, list, 800 IORESOURCE_MEM); 801 acpi_pci_root_validate_resources(&device->dev, list, 802 IORESOURCE_IO); 803 } 804 805 return ret; 806 } 807 808 static void pci_acpi_root_add_resources(struct acpi_pci_root_info *info) 809 { 810 struct resource_entry *entry, *tmp; 811 struct resource *res, *conflict, *root = NULL; 812 813 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 814 res = entry->res; 815 if (res->flags & IORESOURCE_MEM) 816 root = &iomem_resource; 817 else if (res->flags & IORESOURCE_IO) 818 root = &ioport_resource; 819 else 820 continue; 821 822 /* 823 * Some legacy x86 host bridge drivers use iomem_resource and 824 * ioport_resource as default resource pool, skip it. 825 */ 826 if (res == root) 827 continue; 828 829 conflict = insert_resource_conflict(root, res); 830 if (conflict) { 831 dev_info(&info->bridge->dev, 832 "ignoring host bridge window %pR (conflicts with %s %pR)\n", 833 res, conflict->name, conflict); 834 resource_list_destroy_entry(entry); 835 } 836 } 837 } 838 839 static void __acpi_pci_root_release_info(struct acpi_pci_root_info *info) 840 { 841 struct resource *res; 842 struct resource_entry *entry, *tmp; 843 844 if (!info) 845 return; 846 847 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 848 res = entry->res; 849 if (res->parent && 850 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 851 release_resource(res); 852 resource_list_destroy_entry(entry); 853 } 854 855 info->ops->release_info(info); 856 } 857 858 static void acpi_pci_root_release_info(struct pci_host_bridge *bridge) 859 { 860 struct resource *res; 861 struct resource_entry *entry; 862 863 resource_list_for_each_entry(entry, &bridge->windows) { 864 res = entry->res; 865 if (res->flags & IORESOURCE_IO) 866 pci_unmap_iospace(res); 867 if (res->parent && 868 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 869 release_resource(res); 870 } 871 __acpi_pci_root_release_info(bridge->release_data); 872 } 873 874 struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, 875 struct acpi_pci_root_ops *ops, 876 struct acpi_pci_root_info *info, 877 void *sysdata) 878 { 879 int ret, busnum = root->secondary.start; 880 struct acpi_device *device = root->device; 881 int node = acpi_get_node(device->handle); 882 struct pci_bus *bus; 883 struct pci_host_bridge *host_bridge; 884 union acpi_object *obj; 885 886 info->root = root; 887 info->bridge = device; 888 info->ops = ops; 889 INIT_LIST_HEAD(&info->resources); 890 snprintf(info->name, sizeof(info->name), "PCI Bus %04x:%02x", 891 root->segment, busnum); 892 893 if (ops->init_info && ops->init_info(info)) 894 goto out_release_info; 895 if (ops->prepare_resources) 896 ret = ops->prepare_resources(info); 897 else 898 ret = acpi_pci_probe_root_resources(info); 899 if (ret < 0) 900 goto out_release_info; 901 902 pci_acpi_root_add_resources(info); 903 pci_add_resource(&info->resources, &root->secondary); 904 bus = pci_create_root_bus(NULL, busnum, ops->pci_ops, 905 sysdata, &info->resources); 906 if (!bus) 907 goto out_release_info; 908 909 host_bridge = to_pci_host_bridge(bus->bridge); 910 if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) 911 host_bridge->native_pcie_hotplug = 0; 912 if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL)) 913 host_bridge->native_shpc_hotplug = 0; 914 if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL)) 915 host_bridge->native_aer = 0; 916 if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL)) 917 host_bridge->native_pme = 0; 918 if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL)) 919 host_bridge->native_ltr = 0; 920 if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL)) 921 host_bridge->native_dpc = 0; 922 923 /* 924 * Evaluate the "PCI Boot Configuration" _DSM Function. If it 925 * exists and returns 0, we must preserve any PCI resource 926 * assignments made by firmware for this host bridge. 927 */ 928 obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 1, 929 DSM_PCI_PRESERVE_BOOT_CONFIG, NULL); 930 if (obj && obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 0) 931 host_bridge->preserve_config = 1; 932 ACPI_FREE(obj); 933 934 pci_scan_child_bus(bus); 935 pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info, 936 info); 937 if (node != NUMA_NO_NODE) 938 dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node); 939 return bus; 940 941 out_release_info: 942 __acpi_pci_root_release_info(info); 943 return NULL; 944 } 945 946 void __init acpi_pci_root_init(void) 947 { 948 acpi_hest_init(); 949 if (acpi_pci_disabled) 950 return; 951 952 pci_acpi_crs_quirks(); 953 acpi_scan_add_handler_with_hotplug(&pci_root_handler, "pci_root"); 954 } 955