1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 40 $) 4 * 5 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> 6 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/mutex.h> 14 #include <linux/pm.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/pci.h> 17 #include <linux/pci-acpi.h> 18 #include <linux/pci-aspm.h> 19 #include <linux/dmar.h> 20 #include <linux/acpi.h> 21 #include <linux/slab.h> 22 #include <linux/dmi.h> 23 #include <linux/platform_data/x86/apple.h> 24 #include <acpi/apei.h> /* for acpi_hest_init() */ 25 26 #include "internal.h" 27 28 #define _COMPONENT ACPI_PCI_COMPONENT 29 ACPI_MODULE_NAME("pci_root"); 30 #define ACPI_PCI_ROOT_CLASS "pci_bridge" 31 #define ACPI_PCI_ROOT_DEVICE_NAME "PCI Root Bridge" 32 static int acpi_pci_root_add(struct acpi_device *device, 33 const struct acpi_device_id *not_used); 34 static void acpi_pci_root_remove(struct acpi_device *device); 35 36 static int acpi_pci_root_scan_dependent(struct acpi_device *adev) 37 { 38 acpiphp_check_host_bridge(adev); 39 return 0; 40 } 41 42 #define ACPI_PCIE_REQ_SUPPORT (OSC_PCI_EXT_CONFIG_SUPPORT \ 43 | OSC_PCI_ASPM_SUPPORT \ 44 | OSC_PCI_CLOCK_PM_SUPPORT \ 45 | OSC_PCI_MSI_SUPPORT) 46 47 static const struct acpi_device_id root_device_ids[] = { 48 {"PNP0A03", 0}, 49 {"", 0}, 50 }; 51 52 static struct acpi_scan_handler pci_root_handler = { 53 .ids = root_device_ids, 54 .attach = acpi_pci_root_add, 55 .detach = acpi_pci_root_remove, 56 .hotplug = { 57 .enabled = true, 58 .scan_dependent = acpi_pci_root_scan_dependent, 59 }, 60 }; 61 62 static DEFINE_MUTEX(osc_lock); 63 64 /** 65 * acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge 66 * @handle - the ACPI CA node in question. 67 * 68 * Note: we could make this API take a struct acpi_device * instead, but 69 * for now, it's more convenient to operate on an acpi_handle. 70 */ 71 int acpi_is_root_bridge(acpi_handle handle) 72 { 73 int ret; 74 struct acpi_device *device; 75 76 ret = acpi_bus_get_device(handle, &device); 77 if (ret) 78 return 0; 79 80 ret = acpi_match_device_ids(device, root_device_ids); 81 if (ret) 82 return 0; 83 else 84 return 1; 85 } 86 EXPORT_SYMBOL_GPL(acpi_is_root_bridge); 87 88 static acpi_status 89 get_root_bridge_busnr_callback(struct acpi_resource *resource, void *data) 90 { 91 struct resource *res = data; 92 struct acpi_resource_address64 address; 93 acpi_status status; 94 95 status = acpi_resource_to_address64(resource, &address); 96 if (ACPI_FAILURE(status)) 97 return AE_OK; 98 99 if ((address.address.address_length > 0) && 100 (address.resource_type == ACPI_BUS_NUMBER_RANGE)) { 101 res->start = address.address.minimum; 102 res->end = address.address.minimum + address.address.address_length - 1; 103 } 104 105 return AE_OK; 106 } 107 108 static acpi_status try_get_root_bridge_busnr(acpi_handle handle, 109 struct resource *res) 110 { 111 acpi_status status; 112 113 res->start = -1; 114 status = 115 acpi_walk_resources(handle, METHOD_NAME__CRS, 116 get_root_bridge_busnr_callback, res); 117 if (ACPI_FAILURE(status)) 118 return status; 119 if (res->start == -1) 120 return AE_ERROR; 121 return AE_OK; 122 } 123 124 struct pci_osc_bit_struct { 125 u32 bit; 126 char *desc; 127 }; 128 129 static struct pci_osc_bit_struct pci_osc_support_bit[] = { 130 { OSC_PCI_EXT_CONFIG_SUPPORT, "ExtendedConfig" }, 131 { OSC_PCI_ASPM_SUPPORT, "ASPM" }, 132 { OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" }, 133 { OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" }, 134 { OSC_PCI_MSI_SUPPORT, "MSI" }, 135 { OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" }, 136 }; 137 138 static struct pci_osc_bit_struct pci_osc_control_bit[] = { 139 { OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, "PCIeHotplug" }, 140 { OSC_PCI_SHPC_NATIVE_HP_CONTROL, "SHPCHotplug" }, 141 { OSC_PCI_EXPRESS_PME_CONTROL, "PME" }, 142 { OSC_PCI_EXPRESS_AER_CONTROL, "AER" }, 143 { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" }, 144 { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" }, 145 }; 146 147 static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word, 148 struct pci_osc_bit_struct *table, int size) 149 { 150 char buf[80]; 151 int i, len = 0; 152 struct pci_osc_bit_struct *entry; 153 154 buf[0] = '\0'; 155 for (i = 0, entry = table; i < size; i++, entry++) 156 if (word & entry->bit) 157 len += snprintf(buf + len, sizeof(buf) - len, "%s%s", 158 len ? " " : "", entry->desc); 159 160 dev_info(&root->device->dev, "_OSC: %s [%s]\n", msg, buf); 161 } 162 163 static void decode_osc_support(struct acpi_pci_root *root, char *msg, u32 word) 164 { 165 decode_osc_bits(root, msg, word, pci_osc_support_bit, 166 ARRAY_SIZE(pci_osc_support_bit)); 167 } 168 169 static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word) 170 { 171 decode_osc_bits(root, msg, word, pci_osc_control_bit, 172 ARRAY_SIZE(pci_osc_control_bit)); 173 } 174 175 static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766"; 176 177 static acpi_status acpi_pci_run_osc(acpi_handle handle, 178 const u32 *capbuf, u32 *retval) 179 { 180 struct acpi_osc_context context = { 181 .uuid_str = pci_osc_uuid_str, 182 .rev = 1, 183 .cap.length = 12, 184 .cap.pointer = (void *)capbuf, 185 }; 186 acpi_status status; 187 188 status = acpi_run_osc(handle, &context); 189 if (ACPI_SUCCESS(status)) { 190 *retval = *((u32 *)(context.ret.pointer + 8)); 191 kfree(context.ret.pointer); 192 } 193 return status; 194 } 195 196 static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, 197 u32 support, 198 u32 *control) 199 { 200 acpi_status status; 201 u32 result, capbuf[3]; 202 203 support &= OSC_PCI_SUPPORT_MASKS; 204 support |= root->osc_support_set; 205 206 capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE; 207 capbuf[OSC_SUPPORT_DWORD] = support; 208 if (control) { 209 *control &= OSC_PCI_CONTROL_MASKS; 210 capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set; 211 } else { 212 /* Run _OSC query only with existing controls. */ 213 capbuf[OSC_CONTROL_DWORD] = root->osc_control_set; 214 } 215 216 status = acpi_pci_run_osc(root->device->handle, capbuf, &result); 217 if (ACPI_SUCCESS(status)) { 218 root->osc_support_set = support; 219 if (control) 220 *control = result; 221 } 222 return status; 223 } 224 225 static acpi_status acpi_pci_osc_support(struct acpi_pci_root *root, u32 flags) 226 { 227 acpi_status status; 228 229 mutex_lock(&osc_lock); 230 status = acpi_pci_query_osc(root, flags, NULL); 231 mutex_unlock(&osc_lock); 232 return status; 233 } 234 235 struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle) 236 { 237 struct acpi_pci_root *root; 238 struct acpi_device *device; 239 240 if (acpi_bus_get_device(handle, &device) || 241 acpi_match_device_ids(device, root_device_ids)) 242 return NULL; 243 244 root = acpi_driver_data(device); 245 246 return root; 247 } 248 EXPORT_SYMBOL_GPL(acpi_pci_find_root); 249 250 struct acpi_handle_node { 251 struct list_head node; 252 acpi_handle handle; 253 }; 254 255 /** 256 * acpi_get_pci_dev - convert ACPI CA handle to struct pci_dev 257 * @handle: the handle in question 258 * 259 * Given an ACPI CA handle, the desired PCI device is located in the 260 * list of PCI devices. 261 * 262 * If the device is found, its reference count is increased and this 263 * function returns a pointer to its data structure. The caller must 264 * decrement the reference count by calling pci_dev_put(). 265 * If no device is found, %NULL is returned. 266 */ 267 struct pci_dev *acpi_get_pci_dev(acpi_handle handle) 268 { 269 int dev, fn; 270 unsigned long long adr; 271 acpi_status status; 272 acpi_handle phandle; 273 struct pci_bus *pbus; 274 struct pci_dev *pdev = NULL; 275 struct acpi_handle_node *node, *tmp; 276 struct acpi_pci_root *root; 277 LIST_HEAD(device_list); 278 279 /* 280 * Walk up the ACPI CA namespace until we reach a PCI root bridge. 281 */ 282 phandle = handle; 283 while (!acpi_is_root_bridge(phandle)) { 284 node = kzalloc(sizeof(struct acpi_handle_node), GFP_KERNEL); 285 if (!node) 286 goto out; 287 288 INIT_LIST_HEAD(&node->node); 289 node->handle = phandle; 290 list_add(&node->node, &device_list); 291 292 status = acpi_get_parent(phandle, &phandle); 293 if (ACPI_FAILURE(status)) 294 goto out; 295 } 296 297 root = acpi_pci_find_root(phandle); 298 if (!root) 299 goto out; 300 301 pbus = root->bus; 302 303 /* 304 * Now, walk back down the PCI device tree until we return to our 305 * original handle. Assumes that everything between the PCI root 306 * bridge and the device we're looking for must be a P2P bridge. 307 */ 308 list_for_each_entry(node, &device_list, node) { 309 acpi_handle hnd = node->handle; 310 status = acpi_evaluate_integer(hnd, "_ADR", NULL, &adr); 311 if (ACPI_FAILURE(status)) 312 goto out; 313 dev = (adr >> 16) & 0xffff; 314 fn = adr & 0xffff; 315 316 pdev = pci_get_slot(pbus, PCI_DEVFN(dev, fn)); 317 if (!pdev || hnd == handle) 318 break; 319 320 pbus = pdev->subordinate; 321 pci_dev_put(pdev); 322 323 /* 324 * This function may be called for a non-PCI device that has a 325 * PCI parent (eg. a disk under a PCI SATA controller). In that 326 * case pdev->subordinate will be NULL for the parent. 327 */ 328 if (!pbus) { 329 dev_dbg(&pdev->dev, "Not a PCI-to-PCI bridge\n"); 330 pdev = NULL; 331 break; 332 } 333 } 334 out: 335 list_for_each_entry_safe(node, tmp, &device_list, node) 336 kfree(node); 337 338 return pdev; 339 } 340 EXPORT_SYMBOL_GPL(acpi_get_pci_dev); 341 342 /** 343 * acpi_pci_osc_control_set - Request control of PCI root _OSC features. 344 * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex). 345 * @mask: Mask of _OSC bits to request control of, place to store control mask. 346 * @req: Mask of _OSC bits the control of is essential to the caller. 347 * 348 * Run _OSC query for @mask and if that is successful, compare the returned 349 * mask of control bits with @req. If all of the @req bits are set in the 350 * returned mask, run _OSC request for it. 351 * 352 * The variable at the @mask address may be modified regardless of whether or 353 * not the function returns success. On success it will contain the mask of 354 * _OSC bits the BIOS has granted control of, but its contents are meaningless 355 * on failure. 356 **/ 357 acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 req) 358 { 359 struct acpi_pci_root *root; 360 acpi_status status = AE_OK; 361 u32 ctrl, capbuf[3]; 362 363 if (!mask) 364 return AE_BAD_PARAMETER; 365 366 ctrl = *mask & OSC_PCI_CONTROL_MASKS; 367 if ((ctrl & req) != req) 368 return AE_TYPE; 369 370 root = acpi_pci_find_root(handle); 371 if (!root) 372 return AE_NOT_EXIST; 373 374 mutex_lock(&osc_lock); 375 376 *mask = ctrl | root->osc_control_set; 377 /* No need to evaluate _OSC if the control was already granted. */ 378 if ((root->osc_control_set & ctrl) == ctrl) 379 goto out; 380 381 /* Need to check the available controls bits before requesting them. */ 382 while (*mask) { 383 status = acpi_pci_query_osc(root, root->osc_support_set, mask); 384 if (ACPI_FAILURE(status)) 385 goto out; 386 if (ctrl == *mask) 387 break; 388 decode_osc_control(root, "platform does not support", 389 ctrl & ~(*mask)); 390 ctrl = *mask; 391 } 392 393 if ((ctrl & req) != req) { 394 decode_osc_control(root, "not requesting control; platform does not support", 395 req & ~(ctrl)); 396 status = AE_SUPPORT; 397 goto out; 398 } 399 400 capbuf[OSC_QUERY_DWORD] = 0; 401 capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set; 402 capbuf[OSC_CONTROL_DWORD] = ctrl; 403 status = acpi_pci_run_osc(handle, capbuf, mask); 404 if (ACPI_SUCCESS(status)) 405 root->osc_control_set = *mask; 406 out: 407 mutex_unlock(&osc_lock); 408 return status; 409 } 410 EXPORT_SYMBOL(acpi_pci_osc_control_set); 411 412 static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm, 413 bool is_pcie) 414 { 415 u32 support, control, requested; 416 acpi_status status; 417 struct acpi_device *device = root->device; 418 acpi_handle handle = device->handle; 419 420 /* 421 * Apple always return failure on _OSC calls when _OSI("Darwin") has 422 * been called successfully. We know the feature set supported by the 423 * platform, so avoid calling _OSC at all 424 */ 425 if (x86_apple_machine) { 426 root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL; 427 decode_osc_control(root, "OS assumes control of", 428 root->osc_control_set); 429 return; 430 } 431 432 /* 433 * All supported architectures that use ACPI have support for 434 * PCI domains, so we indicate this in _OSC support capabilities. 435 */ 436 support = OSC_PCI_SEGMENT_GROUPS_SUPPORT; 437 support |= OSC_PCI_HPX_TYPE_3_SUPPORT; 438 if (pci_ext_cfg_avail()) 439 support |= OSC_PCI_EXT_CONFIG_SUPPORT; 440 if (pcie_aspm_support_enabled()) 441 support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT; 442 if (pci_msi_enabled()) 443 support |= OSC_PCI_MSI_SUPPORT; 444 445 decode_osc_support(root, "OS supports", support); 446 status = acpi_pci_osc_support(root, support); 447 if (ACPI_FAILURE(status)) { 448 *no_aspm = 1; 449 450 /* _OSC is optional for PCI host bridges */ 451 if ((status == AE_NOT_FOUND) && !is_pcie) 452 return; 453 454 dev_info(&device->dev, "_OSC failed (%s)%s\n", 455 acpi_format_exception(status), 456 pcie_aspm_support_enabled() ? "; disabling ASPM" : ""); 457 return; 458 } 459 460 if (pcie_ports_disabled) { 461 dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n"); 462 return; 463 } 464 465 if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) { 466 decode_osc_support(root, "not requesting OS control; OS requires", 467 ACPI_PCIE_REQ_SUPPORT); 468 return; 469 } 470 471 control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL 472 | OSC_PCI_EXPRESS_PME_CONTROL; 473 474 if (IS_ENABLED(CONFIG_PCIEASPM)) 475 control |= OSC_PCI_EXPRESS_LTR_CONTROL; 476 477 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) 478 control |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL; 479 480 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC)) 481 control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL; 482 483 if (pci_aer_available()) { 484 if (aer_acpi_firmware_first()) 485 dev_info(&device->dev, 486 "PCIe AER handled by firmware\n"); 487 else 488 control |= OSC_PCI_EXPRESS_AER_CONTROL; 489 } 490 491 requested = control; 492 status = acpi_pci_osc_control_set(handle, &control, 493 OSC_PCI_EXPRESS_CAPABILITY_CONTROL); 494 if (ACPI_SUCCESS(status)) { 495 decode_osc_control(root, "OS now controls", control); 496 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) { 497 /* 498 * We have ASPM control, but the FADT indicates that 499 * it's unsupported. Leave existing configuration 500 * intact and prevent the OS from touching it. 501 */ 502 dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n"); 503 *no_aspm = 1; 504 } 505 } else { 506 decode_osc_control(root, "OS requested", requested); 507 decode_osc_control(root, "platform willing to grant", control); 508 dev_info(&device->dev, "_OSC failed (%s); disabling ASPM\n", 509 acpi_format_exception(status)); 510 511 /* 512 * We want to disable ASPM here, but aspm_disabled 513 * needs to remain in its state from boot so that we 514 * properly handle PCIe 1.1 devices. So we set this 515 * flag here, to defer the action until after the ACPI 516 * root scan. 517 */ 518 *no_aspm = 1; 519 } 520 } 521 522 static int acpi_pci_root_add(struct acpi_device *device, 523 const struct acpi_device_id *not_used) 524 { 525 unsigned long long segment, bus; 526 acpi_status status; 527 int result; 528 struct acpi_pci_root *root; 529 acpi_handle handle = device->handle; 530 int no_aspm = 0; 531 bool hotadd = system_state == SYSTEM_RUNNING; 532 bool is_pcie; 533 534 root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL); 535 if (!root) 536 return -ENOMEM; 537 538 segment = 0; 539 status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL, 540 &segment); 541 if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { 542 dev_err(&device->dev, "can't evaluate _SEG\n"); 543 result = -ENODEV; 544 goto end; 545 } 546 547 /* Check _CRS first, then _BBN. If no _BBN, default to zero. */ 548 root->secondary.flags = IORESOURCE_BUS; 549 status = try_get_root_bridge_busnr(handle, &root->secondary); 550 if (ACPI_FAILURE(status)) { 551 /* 552 * We need both the start and end of the downstream bus range 553 * to interpret _CBA (MMCONFIG base address), so it really is 554 * supposed to be in _CRS. If we don't find it there, all we 555 * can do is assume [_BBN-0xFF] or [0-0xFF]. 556 */ 557 root->secondary.end = 0xFF; 558 dev_warn(&device->dev, 559 FW_BUG "no secondary bus range in _CRS\n"); 560 status = acpi_evaluate_integer(handle, METHOD_NAME__BBN, 561 NULL, &bus); 562 if (ACPI_SUCCESS(status)) 563 root->secondary.start = bus; 564 else if (status == AE_NOT_FOUND) 565 root->secondary.start = 0; 566 else { 567 dev_err(&device->dev, "can't evaluate _BBN\n"); 568 result = -ENODEV; 569 goto end; 570 } 571 } 572 573 root->device = device; 574 root->segment = segment & 0xFFFF; 575 strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME); 576 strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS); 577 device->driver_data = root; 578 579 if (hotadd && dmar_device_add(handle)) { 580 result = -ENXIO; 581 goto end; 582 } 583 584 pr_info(PREFIX "%s [%s] (domain %04x %pR)\n", 585 acpi_device_name(device), acpi_device_bid(device), 586 root->segment, &root->secondary); 587 588 root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle); 589 590 is_pcie = strcmp(acpi_device_hid(device), "PNP0A08") == 0; 591 negotiate_os_control(root, &no_aspm, is_pcie); 592 593 /* 594 * TBD: Need PCI interface for enumeration/configuration of roots. 595 */ 596 597 /* 598 * Scan the Root Bridge 599 * -------------------- 600 * Must do this prior to any attempt to bind the root device, as the 601 * PCI namespace does not get created until this call is made (and 602 * thus the root bridge's pci_dev does not exist). 603 */ 604 root->bus = pci_acpi_scan_root(root); 605 if (!root->bus) { 606 dev_err(&device->dev, 607 "Bus %04x:%02x not present in PCI namespace\n", 608 root->segment, (unsigned int)root->secondary.start); 609 device->driver_data = NULL; 610 result = -ENODEV; 611 goto remove_dmar; 612 } 613 614 if (no_aspm) 615 pcie_no_aspm(); 616 617 pci_acpi_add_bus_pm_notifier(device); 618 device_set_wakeup_capable(root->bus->bridge, device->wakeup.flags.valid); 619 620 if (hotadd) { 621 pcibios_resource_survey_bus(root->bus); 622 pci_assign_unassigned_root_bus_resources(root->bus); 623 /* 624 * This is only called for the hotadd case. For the boot-time 625 * case, we need to wait until after PCI initialization in 626 * order to deal with IOAPICs mapped in on a PCI BAR. 627 * 628 * This is currently x86-specific, because acpi_ioapic_add() 629 * is an empty function without CONFIG_ACPI_HOTPLUG_IOAPIC. 630 * And CONFIG_ACPI_HOTPLUG_IOAPIC depends on CONFIG_X86_IO_APIC 631 * (see drivers/acpi/Kconfig). 632 */ 633 acpi_ioapic_add(root->device->handle); 634 } 635 636 pci_lock_rescan_remove(); 637 pci_bus_add_devices(root->bus); 638 pci_unlock_rescan_remove(); 639 return 1; 640 641 remove_dmar: 642 if (hotadd) 643 dmar_device_remove(handle); 644 end: 645 kfree(root); 646 return result; 647 } 648 649 static void acpi_pci_root_remove(struct acpi_device *device) 650 { 651 struct acpi_pci_root *root = acpi_driver_data(device); 652 653 pci_lock_rescan_remove(); 654 655 pci_stop_root_bus(root->bus); 656 657 pci_ioapic_remove(root); 658 device_set_wakeup_capable(root->bus->bridge, false); 659 pci_acpi_remove_bus_pm_notifier(device); 660 661 pci_remove_root_bus(root->bus); 662 WARN_ON(acpi_ioapic_remove(root)); 663 664 dmar_device_remove(device->handle); 665 666 pci_unlock_rescan_remove(); 667 668 kfree(root); 669 } 670 671 /* 672 * Following code to support acpi_pci_root_create() is copied from 673 * arch/x86/pci/acpi.c and modified so it could be reused by x86, IA64 674 * and ARM64. 675 */ 676 static void acpi_pci_root_validate_resources(struct device *dev, 677 struct list_head *resources, 678 unsigned long type) 679 { 680 LIST_HEAD(list); 681 struct resource *res1, *res2, *root = NULL; 682 struct resource_entry *tmp, *entry, *entry2; 683 684 BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0); 685 root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource; 686 687 list_splice_init(resources, &list); 688 resource_list_for_each_entry_safe(entry, tmp, &list) { 689 bool free = false; 690 resource_size_t end; 691 692 res1 = entry->res; 693 if (!(res1->flags & type)) 694 goto next; 695 696 /* Exclude non-addressable range or non-addressable portion */ 697 end = min(res1->end, root->end); 698 if (end <= res1->start) { 699 dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n", 700 res1); 701 free = true; 702 goto next; 703 } else if (res1->end != end) { 704 dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n", 705 res1, (unsigned long long)end + 1, 706 (unsigned long long)res1->end); 707 res1->end = end; 708 } 709 710 resource_list_for_each_entry(entry2, resources) { 711 res2 = entry2->res; 712 if (!(res2->flags & type)) 713 continue; 714 715 /* 716 * I don't like throwing away windows because then 717 * our resources no longer match the ACPI _CRS, but 718 * the kernel resource tree doesn't allow overlaps. 719 */ 720 if (resource_overlaps(res1, res2)) { 721 res2->start = min(res1->start, res2->start); 722 res2->end = max(res1->end, res2->end); 723 dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n", 724 res2, res1); 725 free = true; 726 goto next; 727 } 728 } 729 730 next: 731 resource_list_del(entry); 732 if (free) 733 resource_list_free_entry(entry); 734 else 735 resource_list_add_tail(entry, resources); 736 } 737 } 738 739 static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode, 740 struct resource_entry *entry) 741 { 742 #ifdef PCI_IOBASE 743 struct resource *res = entry->res; 744 resource_size_t cpu_addr = res->start; 745 resource_size_t pci_addr = cpu_addr - entry->offset; 746 resource_size_t length = resource_size(res); 747 unsigned long port; 748 749 if (pci_register_io_range(fwnode, cpu_addr, length)) 750 goto err; 751 752 port = pci_address_to_pio(cpu_addr); 753 if (port == (unsigned long)-1) 754 goto err; 755 756 res->start = port; 757 res->end = port + length - 1; 758 entry->offset = port - pci_addr; 759 760 if (pci_remap_iospace(res, cpu_addr) < 0) 761 goto err; 762 763 pr_info("Remapped I/O %pa to %pR\n", &cpu_addr, res); 764 return; 765 err: 766 res->flags |= IORESOURCE_DISABLED; 767 #endif 768 } 769 770 int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info) 771 { 772 int ret; 773 struct list_head *list = &info->resources; 774 struct acpi_device *device = info->bridge; 775 struct resource_entry *entry, *tmp; 776 unsigned long flags; 777 778 flags = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT; 779 ret = acpi_dev_get_resources(device, list, 780 acpi_dev_filter_resource_type_cb, 781 (void *)flags); 782 if (ret < 0) 783 dev_warn(&device->dev, 784 "failed to parse _CRS method, error code %d\n", ret); 785 else if (ret == 0) 786 dev_dbg(&device->dev, 787 "no IO and memory resources present in _CRS\n"); 788 else { 789 resource_list_for_each_entry_safe(entry, tmp, list) { 790 if (entry->res->flags & IORESOURCE_IO) 791 acpi_pci_root_remap_iospace(&device->fwnode, 792 entry); 793 794 if (entry->res->flags & IORESOURCE_DISABLED) 795 resource_list_destroy_entry(entry); 796 else 797 entry->res->name = info->name; 798 } 799 acpi_pci_root_validate_resources(&device->dev, list, 800 IORESOURCE_MEM); 801 acpi_pci_root_validate_resources(&device->dev, list, 802 IORESOURCE_IO); 803 } 804 805 return ret; 806 } 807 808 static void pci_acpi_root_add_resources(struct acpi_pci_root_info *info) 809 { 810 struct resource_entry *entry, *tmp; 811 struct resource *res, *conflict, *root = NULL; 812 813 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 814 res = entry->res; 815 if (res->flags & IORESOURCE_MEM) 816 root = &iomem_resource; 817 else if (res->flags & IORESOURCE_IO) 818 root = &ioport_resource; 819 else 820 continue; 821 822 /* 823 * Some legacy x86 host bridge drivers use iomem_resource and 824 * ioport_resource as default resource pool, skip it. 825 */ 826 if (res == root) 827 continue; 828 829 conflict = insert_resource_conflict(root, res); 830 if (conflict) { 831 dev_info(&info->bridge->dev, 832 "ignoring host bridge window %pR (conflicts with %s %pR)\n", 833 res, conflict->name, conflict); 834 resource_list_destroy_entry(entry); 835 } 836 } 837 } 838 839 static void __acpi_pci_root_release_info(struct acpi_pci_root_info *info) 840 { 841 struct resource *res; 842 struct resource_entry *entry, *tmp; 843 844 if (!info) 845 return; 846 847 resource_list_for_each_entry_safe(entry, tmp, &info->resources) { 848 res = entry->res; 849 if (res->parent && 850 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 851 release_resource(res); 852 resource_list_destroy_entry(entry); 853 } 854 855 info->ops->release_info(info); 856 } 857 858 static void acpi_pci_root_release_info(struct pci_host_bridge *bridge) 859 { 860 struct resource *res; 861 struct resource_entry *entry; 862 863 resource_list_for_each_entry(entry, &bridge->windows) { 864 res = entry->res; 865 if (res->flags & IORESOURCE_IO) 866 pci_unmap_iospace(res); 867 if (res->parent && 868 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) 869 release_resource(res); 870 } 871 __acpi_pci_root_release_info(bridge->release_data); 872 } 873 874 struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, 875 struct acpi_pci_root_ops *ops, 876 struct acpi_pci_root_info *info, 877 void *sysdata) 878 { 879 int ret, busnum = root->secondary.start; 880 struct acpi_device *device = root->device; 881 int node = acpi_get_node(device->handle); 882 struct pci_bus *bus; 883 struct pci_host_bridge *host_bridge; 884 union acpi_object *obj; 885 886 info->root = root; 887 info->bridge = device; 888 info->ops = ops; 889 INIT_LIST_HEAD(&info->resources); 890 snprintf(info->name, sizeof(info->name), "PCI Bus %04x:%02x", 891 root->segment, busnum); 892 893 if (ops->init_info && ops->init_info(info)) 894 goto out_release_info; 895 if (ops->prepare_resources) 896 ret = ops->prepare_resources(info); 897 else 898 ret = acpi_pci_probe_root_resources(info); 899 if (ret < 0) 900 goto out_release_info; 901 902 pci_acpi_root_add_resources(info); 903 pci_add_resource(&info->resources, &root->secondary); 904 bus = pci_create_root_bus(NULL, busnum, ops->pci_ops, 905 sysdata, &info->resources); 906 if (!bus) 907 goto out_release_info; 908 909 host_bridge = to_pci_host_bridge(bus->bridge); 910 if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) 911 host_bridge->native_pcie_hotplug = 0; 912 if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL)) 913 host_bridge->native_shpc_hotplug = 0; 914 if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL)) 915 host_bridge->native_aer = 0; 916 if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL)) 917 host_bridge->native_pme = 0; 918 if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL)) 919 host_bridge->native_ltr = 0; 920 921 /* 922 * Evaluate the "PCI Boot Configuration" _DSM Function. If it 923 * exists and returns 0, we must preserve any PCI resource 924 * assignments made by firmware for this host bridge. 925 */ 926 obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 1, 927 IGNORE_PCI_BOOT_CONFIG_DSM, NULL); 928 if (obj && obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 0) 929 host_bridge->preserve_config = 1; 930 ACPI_FREE(obj); 931 932 pci_scan_child_bus(bus); 933 pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info, 934 info); 935 if (node != NUMA_NO_NODE) 936 dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node); 937 return bus; 938 939 out_release_info: 940 __acpi_pci_root_release_info(info); 941 return NULL; 942 } 943 944 void __init acpi_pci_root_init(void) 945 { 946 acpi_hest_init(); 947 if (acpi_pci_disabled) 948 return; 949 950 pci_acpi_crs_quirks(); 951 acpi_scan_add_handler_with_hotplug(&pci_root_handler, "pci_root"); 952 } 953