1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */ 3 4 #include <linux/clk.h> 5 #include <linux/delay.h> 6 #include <linux/dev_printk.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/err.h> 9 #include <linux/iommu.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/reset.h> 13 14 #include "rocket_core.h" 15 16 int rocket_core_init(struct rocket_core *core) 17 { 18 struct device *dev = core->dev; 19 struct platform_device *pdev = to_platform_device(dev); 20 u32 version; 21 int err = 0; 22 23 core->resets[0].id = "srst_a"; 24 core->resets[1].id = "srst_h"; 25 err = devm_reset_control_bulk_get_exclusive(&pdev->dev, ARRAY_SIZE(core->resets), 26 core->resets); 27 if (err) 28 return dev_err_probe(dev, err, "failed to get resets for core %d\n", core->index); 29 30 err = devm_clk_bulk_get(dev, ARRAY_SIZE(core->clks), core->clks); 31 if (err) 32 return dev_err_probe(dev, err, "failed to get clocks for core %d\n", core->index); 33 34 core->pc_iomem = devm_platform_ioremap_resource_byname(pdev, "pc"); 35 if (IS_ERR(core->pc_iomem)) { 36 dev_err(dev, "couldn't find PC registers %ld\n", PTR_ERR(core->pc_iomem)); 37 return PTR_ERR(core->pc_iomem); 38 } 39 40 core->cna_iomem = devm_platform_ioremap_resource_byname(pdev, "cna"); 41 if (IS_ERR(core->cna_iomem)) { 42 dev_err(dev, "couldn't find CNA registers %ld\n", PTR_ERR(core->cna_iomem)); 43 return PTR_ERR(core->cna_iomem); 44 } 45 46 core->core_iomem = devm_platform_ioremap_resource_byname(pdev, "core"); 47 if (IS_ERR(core->core_iomem)) { 48 dev_err(dev, "couldn't find CORE registers %ld\n", PTR_ERR(core->core_iomem)); 49 return PTR_ERR(core->core_iomem); 50 } 51 52 dma_set_max_seg_size(dev, UINT_MAX); 53 54 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 55 if (err) 56 return err; 57 58 core->iommu_group = iommu_group_get(dev); 59 60 pm_runtime_use_autosuspend(dev); 61 62 /* 63 * As this NPU will be most often used as part of a media pipeline that 64 * ends presenting in a display, choose 50 ms (~3 frames at 60Hz) as an 65 * autosuspend delay as that will keep the device powered up while the 66 * pipeline is running. 67 */ 68 pm_runtime_set_autosuspend_delay(dev, 50); 69 70 pm_runtime_enable(dev); 71 72 err = pm_runtime_get_sync(dev); 73 74 version = rocket_pc_readl(core, VERSION); 75 version += rocket_pc_readl(core, VERSION_NUM) & 0xffff; 76 77 pm_runtime_mark_last_busy(dev); 78 pm_runtime_put_autosuspend(dev); 79 80 dev_info(dev, "Rockchip NPU core %d version: %d\n", core->index, version); 81 82 return 0; 83 } 84 85 void rocket_core_fini(struct rocket_core *core) 86 { 87 pm_runtime_dont_use_autosuspend(core->dev); 88 pm_runtime_disable(core->dev); 89 iommu_group_put(core->iommu_group); 90 core->iommu_group = NULL; 91 } 92 93 void rocket_core_reset(struct rocket_core *core) 94 { 95 reset_control_bulk_assert(ARRAY_SIZE(core->resets), core->resets); 96 97 udelay(10); 98 99 reset_control_bulk_deassert(ARRAY_SIZE(core->resets), core->resets); 100 } 101