1 /* SPDX-License-Identifier: GPL-2.0-only 2 * 3 * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef _QAIC_H_ 8 #define _QAIC_H_ 9 10 #include <linux/interrupt.h> 11 #include <linux/kref.h> 12 #include <linux/mhi.h> 13 #include <linux/mutex.h> 14 #include <linux/pci.h> 15 #include <linux/spinlock.h> 16 #include <linux/srcu.h> 17 #include <linux/wait.h> 18 #include <linux/workqueue.h> 19 #include <drm/drm_device.h> 20 #include <drm/drm_gem.h> 21 22 #define QAIC_DBC_BASE SZ_128K 23 #define QAIC_DBC_SIZE SZ_4K 24 25 #define QAIC_NO_PARTITION -1 26 27 #define QAIC_DBC_OFF(i) ((i) * QAIC_DBC_SIZE + QAIC_DBC_BASE) 28 29 #define to_qaic_bo(obj) container_of(obj, struct qaic_bo, base) 30 #define to_qaic_drm_device(dev) container_of(dev, struct qaic_drm_device, drm) 31 #define to_drm(qddev) (&(qddev)->drm) 32 #define to_accel_kdev(qddev) (to_drm(qddev)->accel->kdev) /* Return Linux device of accel node */ 33 34 extern bool datapath_polling; 35 36 struct qaic_user { 37 /* Uniquely identifies this user for the device */ 38 int handle; 39 struct kref ref_count; 40 /* Char device opened by this user */ 41 struct qaic_drm_device *qddev; 42 /* Node in list of users that opened this drm device */ 43 struct list_head node; 44 /* SRCU used to synchronize this user during cleanup */ 45 struct srcu_struct qddev_lock; 46 atomic_t chunk_id; 47 }; 48 49 struct dma_bridge_chan { 50 /* Pointer to device strcut maintained by driver */ 51 struct qaic_device *qdev; 52 /* ID of this DMA bridge channel(DBC) */ 53 unsigned int id; 54 /* Synchronizes access to xfer_list */ 55 spinlock_t xfer_lock; 56 /* Base address of request queue */ 57 void *req_q_base; 58 /* Base address of response queue */ 59 void *rsp_q_base; 60 /* 61 * Base bus address of request queue. Response queue bus address can be 62 * calculated by adding request queue size to this variable 63 */ 64 dma_addr_t dma_addr; 65 /* Total size of request and response queue in byte */ 66 u32 total_size; 67 /* Capacity of request/response queue */ 68 u32 nelem; 69 /* The user that opened this DBC */ 70 struct qaic_user *usr; 71 /* 72 * Request ID of next memory handle that goes in request queue. One 73 * memory handle can enqueue more than one request elements, all 74 * this requests that belong to same memory handle have same request ID 75 */ 76 u16 next_req_id; 77 /* true: DBC is in use; false: DBC not in use */ 78 bool in_use; 79 /* 80 * Base address of device registers. Used to read/write request and 81 * response queue's head and tail pointer of this DBC. 82 */ 83 void __iomem *dbc_base; 84 /* Head of list where each node is a memory handle queued in request queue */ 85 struct list_head xfer_list; 86 /* Synchronizes DBC readers during cleanup */ 87 struct srcu_struct ch_lock; 88 /* 89 * When this DBC is released, any thread waiting on this wait queue is 90 * woken up 91 */ 92 wait_queue_head_t dbc_release; 93 /* Head of list where each node is a bo associated with this DBC */ 94 struct list_head bo_lists; 95 /* The irq line for this DBC. Used for polling */ 96 unsigned int irq; 97 /* Polling work item to simulate interrupts */ 98 struct work_struct poll_work; 99 }; 100 101 struct qaic_device { 102 /* Pointer to base PCI device struct of our physical device */ 103 struct pci_dev *pdev; 104 /* Req. ID of request that will be queued next in MHI control device */ 105 u32 next_seq_num; 106 /* Base address of bar 0 */ 107 void __iomem *bar_0; 108 /* Base address of bar 2 */ 109 void __iomem *bar_2; 110 /* Controller structure for MHI devices */ 111 struct mhi_controller *mhi_cntrl; 112 /* MHI control channel device */ 113 struct mhi_device *cntl_ch; 114 /* List of requests queued in MHI control device */ 115 struct list_head cntl_xfer_list; 116 /* Synchronizes MHI control device transactions and its xfer list */ 117 struct mutex cntl_mutex; 118 /* Array of DBC struct of this device */ 119 struct dma_bridge_chan *dbc; 120 /* Work queue for tasks related to MHI control device */ 121 struct workqueue_struct *cntl_wq; 122 /* Synchronizes all the users of device during cleanup */ 123 struct srcu_struct dev_lock; 124 /* true: Device under reset; false: Device not under reset */ 125 bool in_reset; 126 /* 127 * true: A tx MHI transaction has failed and a rx buffer is still queued 128 * in control device. Such a buffer is considered lost rx buffer 129 * false: No rx buffer is lost in control device 130 */ 131 bool cntl_lost_buf; 132 /* Maximum number of DBC supported by this device */ 133 u32 num_dbc; 134 /* Reference to the drm_device for this device when it is created */ 135 struct qaic_drm_device *qddev; 136 /* Generate the CRC of a control message */ 137 u32 (*gen_crc)(void *msg); 138 /* Validate the CRC of a control message */ 139 bool (*valid_crc)(void *msg); 140 }; 141 142 struct qaic_drm_device { 143 /* The drm device struct of this drm device */ 144 struct drm_device drm; 145 /* Pointer to the root device struct driven by this driver */ 146 struct qaic_device *qdev; 147 /* 148 * The physical device can be partition in number of logical devices. 149 * And each logical device is given a partition id. This member stores 150 * that id. QAIC_NO_PARTITION is a sentinel used to mark that this drm 151 * device is the actual physical device 152 */ 153 s32 partition_id; 154 /* Head in list of users who have opened this drm device */ 155 struct list_head users; 156 /* Synchronizes access to users list */ 157 struct mutex users_mutex; 158 }; 159 160 struct qaic_bo { 161 struct drm_gem_object base; 162 /* Scatter/gather table for allocate/imported BO */ 163 struct sg_table *sgt; 164 /* Head in list of slices of this BO */ 165 struct list_head slices; 166 /* Total nents, for all slices of this BO */ 167 int total_slice_nents; 168 /* 169 * Direction of transfer. It can assume only two value DMA_TO_DEVICE and 170 * DMA_FROM_DEVICE. 171 */ 172 int dir; 173 /* The pointer of the DBC which operates on this BO */ 174 struct dma_bridge_chan *dbc; 175 /* Number of slice that belongs to this buffer */ 176 u32 nr_slice; 177 /* Number of slice that have been transferred by DMA engine */ 178 u32 nr_slice_xfer_done; 179 /* true = BO is queued for execution, true = BO is not queued */ 180 bool queued; 181 /* 182 * If true then user has attached slicing information to this BO by 183 * calling DRM_IOCTL_QAIC_ATTACH_SLICE_BO ioctl. 184 */ 185 bool sliced; 186 /* Request ID of this BO if it is queued for execution */ 187 u16 req_id; 188 /* Handle assigned to this BO */ 189 u32 handle; 190 /* Wait on this for completion of DMA transfer of this BO */ 191 struct completion xfer_done; 192 /* 193 * Node in linked list where head is dbc->xfer_list. 194 * This link list contain BO's that are queued for DMA transfer. 195 */ 196 struct list_head xfer_list; 197 /* 198 * Node in linked list where head is dbc->bo_lists. 199 * This link list contain BO's that are associated with the DBC it is 200 * linked to. 201 */ 202 struct list_head bo_list; 203 struct { 204 /* 205 * Latest timestamp(ns) at which kernel received a request to 206 * execute this BO 207 */ 208 u64 req_received_ts; 209 /* 210 * Latest timestamp(ns) at which kernel enqueued requests of 211 * this BO for execution in DMA queue 212 */ 213 u64 req_submit_ts; 214 /* 215 * Latest timestamp(ns) at which kernel received a completion 216 * interrupt for requests of this BO 217 */ 218 u64 req_processed_ts; 219 /* 220 * Number of elements already enqueued in DMA queue before 221 * enqueuing requests of this BO 222 */ 223 u32 queue_level_before; 224 } perf_stats; 225 /* Synchronizes BO operations */ 226 struct mutex lock; 227 }; 228 229 struct bo_slice { 230 /* Mapped pages */ 231 struct sg_table *sgt; 232 /* Number of requests required to queue in DMA queue */ 233 int nents; 234 /* See enum dma_data_direction */ 235 int dir; 236 /* Actual requests that will be copied in DMA queue */ 237 struct dbc_req *reqs; 238 struct kref ref_count; 239 /* true: No DMA transfer required */ 240 bool no_xfer; 241 /* Pointer to the parent BO handle */ 242 struct qaic_bo *bo; 243 /* Node in list of slices maintained by parent BO */ 244 struct list_head slice; 245 /* Size of this slice in bytes */ 246 u64 size; 247 /* Offset of this slice in buffer */ 248 u64 offset; 249 }; 250 251 int get_dbc_req_elem_size(void); 252 int get_dbc_rsp_elem_size(void); 253 int get_cntl_version(struct qaic_device *qdev, struct qaic_user *usr, u16 *major, u16 *minor); 254 int qaic_manage_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); 255 void qaic_mhi_ul_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result); 256 257 void qaic_mhi_dl_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result); 258 259 int qaic_control_open(struct qaic_device *qdev); 260 void qaic_control_close(struct qaic_device *qdev); 261 void qaic_release_usr(struct qaic_device *qdev, struct qaic_user *usr); 262 263 irqreturn_t dbc_irq_threaded_fn(int irq, void *data); 264 irqreturn_t dbc_irq_handler(int irq, void *data); 265 int disable_dbc(struct qaic_device *qdev, u32 dbc_id, struct qaic_user *usr); 266 void enable_dbc(struct qaic_device *qdev, u32 dbc_id, struct qaic_user *usr); 267 void wakeup_dbc(struct qaic_device *qdev, u32 dbc_id); 268 void release_dbc(struct qaic_device *qdev, u32 dbc_id); 269 270 void wake_all_cntl(struct qaic_device *qdev); 271 void qaic_dev_reset_clean_local_state(struct qaic_device *qdev, bool exit_reset); 272 273 struct drm_gem_object *qaic_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf); 274 275 int qaic_create_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); 276 int qaic_mmap_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); 277 int qaic_attach_slice_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); 278 int qaic_execute_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); 279 int qaic_partial_execute_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); 280 int qaic_wait_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); 281 int qaic_perf_stats_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); 282 int qaic_detach_slice_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); 283 void irq_polling_work(struct work_struct *work); 284 285 #endif /* _QAIC_H_ */ 286