1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020-2023 Intel Corporation 4 */ 5 6 #include <linux/genalloc.h> 7 #include <linux/highmem.h> 8 #include <linux/kthread.h> 9 #include <linux/wait.h> 10 11 #include "ivpu_drv.h" 12 #include "ivpu_gem.h" 13 #include "ivpu_hw.h" 14 #include "ivpu_hw_reg_io.h" 15 #include "ivpu_ipc.h" 16 #include "ivpu_jsm_msg.h" 17 #include "ivpu_pm.h" 18 19 #define IPC_MAX_RX_MSG 128 20 #define IS_KTHREAD() (get_current()->flags & PF_KTHREAD) 21 22 struct ivpu_ipc_tx_buf { 23 struct ivpu_ipc_hdr ipc; 24 struct vpu_jsm_msg jsm; 25 }; 26 27 struct ivpu_ipc_rx_msg { 28 struct list_head link; 29 struct ivpu_ipc_hdr *ipc_hdr; 30 struct vpu_jsm_msg *jsm_msg; 31 }; 32 33 static void ivpu_ipc_msg_dump(struct ivpu_device *vdev, char *c, 34 struct ivpu_ipc_hdr *ipc_hdr, u32 vpu_addr) 35 { 36 ivpu_dbg(vdev, IPC, 37 "%s: vpu:0x%x (data_addr:0x%08x, data_size:0x%x, channel:0x%x, src_node:0x%x, dst_node:0x%x, status:0x%x)", 38 c, vpu_addr, ipc_hdr->data_addr, ipc_hdr->data_size, ipc_hdr->channel, 39 ipc_hdr->src_node, ipc_hdr->dst_node, ipc_hdr->status); 40 } 41 42 static void ivpu_jsm_msg_dump(struct ivpu_device *vdev, char *c, 43 struct vpu_jsm_msg *jsm_msg, u32 vpu_addr) 44 { 45 u32 *payload = (u32 *)&jsm_msg->payload; 46 47 ivpu_dbg(vdev, JSM, 48 "%s: vpu:0x%08x (type:%s, status:0x%x, id: 0x%x, result: 0x%x, payload:0x%x 0x%x 0x%x 0x%x 0x%x)\n", 49 c, vpu_addr, ivpu_jsm_msg_type_to_str(jsm_msg->type), 50 jsm_msg->status, jsm_msg->request_id, jsm_msg->result, 51 payload[0], payload[1], payload[2], payload[3], payload[4]); 52 } 53 54 static void 55 ivpu_ipc_rx_mark_free(struct ivpu_device *vdev, struct ivpu_ipc_hdr *ipc_hdr, 56 struct vpu_jsm_msg *jsm_msg) 57 { 58 ipc_hdr->status = IVPU_IPC_HDR_FREE; 59 if (jsm_msg) 60 jsm_msg->status = VPU_JSM_MSG_FREE; 61 wmb(); /* Flush WC buffers for message statuses */ 62 } 63 64 static void ivpu_ipc_mem_fini(struct ivpu_device *vdev) 65 { 66 struct ivpu_ipc_info *ipc = vdev->ipc; 67 68 ivpu_bo_free_internal(ipc->mem_rx); 69 ivpu_bo_free_internal(ipc->mem_tx); 70 } 71 72 static int 73 ivpu_ipc_tx_prepare(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 74 struct vpu_jsm_msg *req) 75 { 76 struct ivpu_ipc_info *ipc = vdev->ipc; 77 struct ivpu_ipc_tx_buf *tx_buf; 78 u32 tx_buf_vpu_addr; 79 u32 jsm_vpu_addr; 80 81 tx_buf_vpu_addr = gen_pool_alloc(ipc->mm_tx, sizeof(*tx_buf)); 82 if (!tx_buf_vpu_addr) { 83 ivpu_err_ratelimited(vdev, "Failed to reserve IPC buffer, size %ld\n", 84 sizeof(*tx_buf)); 85 return -ENOMEM; 86 } 87 88 tx_buf = ivpu_to_cpu_addr(ipc->mem_tx, tx_buf_vpu_addr); 89 if (drm_WARN_ON(&vdev->drm, !tx_buf)) { 90 gen_pool_free(ipc->mm_tx, tx_buf_vpu_addr, sizeof(*tx_buf)); 91 return -EIO; 92 } 93 94 jsm_vpu_addr = tx_buf_vpu_addr + offsetof(struct ivpu_ipc_tx_buf, jsm); 95 96 if (tx_buf->ipc.status != IVPU_IPC_HDR_FREE) 97 ivpu_warn_ratelimited(vdev, "IPC message vpu:0x%x not released by firmware\n", 98 tx_buf_vpu_addr); 99 100 if (tx_buf->jsm.status != VPU_JSM_MSG_FREE) 101 ivpu_warn_ratelimited(vdev, "JSM message vpu:0x%x not released by firmware\n", 102 jsm_vpu_addr); 103 104 memset(tx_buf, 0, sizeof(*tx_buf)); 105 tx_buf->ipc.data_addr = jsm_vpu_addr; 106 /* TODO: Set data_size to actual JSM message size, not union of all messages */ 107 tx_buf->ipc.data_size = sizeof(*req); 108 tx_buf->ipc.channel = cons->channel; 109 tx_buf->ipc.src_node = 0; 110 tx_buf->ipc.dst_node = 1; 111 tx_buf->ipc.status = IVPU_IPC_HDR_ALLOCATED; 112 tx_buf->jsm.type = req->type; 113 tx_buf->jsm.status = VPU_JSM_MSG_ALLOCATED; 114 tx_buf->jsm.payload = req->payload; 115 116 req->request_id = atomic_inc_return(&ipc->request_id); 117 tx_buf->jsm.request_id = req->request_id; 118 cons->request_id = req->request_id; 119 wmb(); /* Flush WC buffers for IPC, JSM msgs */ 120 121 cons->tx_vpu_addr = tx_buf_vpu_addr; 122 123 ivpu_jsm_msg_dump(vdev, "TX", &tx_buf->jsm, jsm_vpu_addr); 124 ivpu_ipc_msg_dump(vdev, "TX", &tx_buf->ipc, tx_buf_vpu_addr); 125 126 return 0; 127 } 128 129 static void ivpu_ipc_tx_release(struct ivpu_device *vdev, u32 vpu_addr) 130 { 131 struct ivpu_ipc_info *ipc = vdev->ipc; 132 133 if (vpu_addr) 134 gen_pool_free(ipc->mm_tx, vpu_addr, sizeof(struct ivpu_ipc_tx_buf)); 135 } 136 137 static void ivpu_ipc_tx(struct ivpu_device *vdev, u32 vpu_addr) 138 { 139 ivpu_hw_reg_ipc_tx_set(vdev, vpu_addr); 140 } 141 142 void 143 ivpu_ipc_consumer_add(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, u32 channel) 144 { 145 struct ivpu_ipc_info *ipc = vdev->ipc; 146 147 INIT_LIST_HEAD(&cons->link); 148 cons->channel = channel; 149 cons->tx_vpu_addr = 0; 150 cons->request_id = 0; 151 spin_lock_init(&cons->rx_msg_lock); 152 INIT_LIST_HEAD(&cons->rx_msg_list); 153 init_waitqueue_head(&cons->rx_msg_wq); 154 155 spin_lock_irq(&ipc->cons_list_lock); 156 list_add_tail(&cons->link, &ipc->cons_list); 157 spin_unlock_irq(&ipc->cons_list_lock); 158 } 159 160 void ivpu_ipc_consumer_del(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons) 161 { 162 struct ivpu_ipc_info *ipc = vdev->ipc; 163 struct ivpu_ipc_rx_msg *rx_msg, *r; 164 165 spin_lock_irq(&ipc->cons_list_lock); 166 list_del(&cons->link); 167 spin_unlock_irq(&ipc->cons_list_lock); 168 169 spin_lock_irq(&cons->rx_msg_lock); 170 list_for_each_entry_safe(rx_msg, r, &cons->rx_msg_list, link) { 171 list_del(&rx_msg->link); 172 ivpu_ipc_rx_mark_free(vdev, rx_msg->ipc_hdr, rx_msg->jsm_msg); 173 atomic_dec(&ipc->rx_msg_count); 174 kfree(rx_msg); 175 } 176 spin_unlock_irq(&cons->rx_msg_lock); 177 178 ivpu_ipc_tx_release(vdev, cons->tx_vpu_addr); 179 } 180 181 static int 182 ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, struct vpu_jsm_msg *req) 183 { 184 struct ivpu_ipc_info *ipc = vdev->ipc; 185 int ret; 186 187 mutex_lock(&ipc->lock); 188 189 if (!ipc->on) { 190 ret = -EAGAIN; 191 goto unlock; 192 } 193 194 ret = ivpu_ipc_tx_prepare(vdev, cons, req); 195 if (ret) 196 goto unlock; 197 198 ivpu_ipc_tx(vdev, cons->tx_vpu_addr); 199 200 unlock: 201 mutex_unlock(&ipc->lock); 202 return ret; 203 } 204 205 int ivpu_ipc_receive(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 206 struct ivpu_ipc_hdr *ipc_buf, 207 struct vpu_jsm_msg *ipc_payload, unsigned long timeout_ms) 208 { 209 struct ivpu_ipc_info *ipc = vdev->ipc; 210 struct ivpu_ipc_rx_msg *rx_msg; 211 int wait_ret, ret = 0; 212 213 wait_ret = wait_event_timeout(cons->rx_msg_wq, 214 (IS_KTHREAD() && kthread_should_stop()) || 215 !list_empty(&cons->rx_msg_list), 216 msecs_to_jiffies(timeout_ms)); 217 218 if (IS_KTHREAD() && kthread_should_stop()) 219 return -EINTR; 220 221 if (wait_ret == 0) 222 return -ETIMEDOUT; 223 224 spin_lock_irq(&cons->rx_msg_lock); 225 rx_msg = list_first_entry_or_null(&cons->rx_msg_list, struct ivpu_ipc_rx_msg, link); 226 if (!rx_msg) { 227 spin_unlock_irq(&cons->rx_msg_lock); 228 return -EAGAIN; 229 } 230 list_del(&rx_msg->link); 231 spin_unlock_irq(&cons->rx_msg_lock); 232 233 if (ipc_buf) 234 memcpy(ipc_buf, rx_msg->ipc_hdr, sizeof(*ipc_buf)); 235 if (rx_msg->jsm_msg) { 236 u32 size = min_t(int, rx_msg->ipc_hdr->data_size, sizeof(*ipc_payload)); 237 238 if (rx_msg->jsm_msg->result != VPU_JSM_STATUS_SUCCESS) { 239 ivpu_dbg(vdev, IPC, "IPC resp result error: %d\n", rx_msg->jsm_msg->result); 240 ret = -EBADMSG; 241 } 242 243 if (ipc_payload) 244 memcpy(ipc_payload, rx_msg->jsm_msg, size); 245 } 246 247 ivpu_ipc_rx_mark_free(vdev, rx_msg->ipc_hdr, rx_msg->jsm_msg); 248 atomic_dec(&ipc->rx_msg_count); 249 kfree(rx_msg); 250 251 return ret; 252 } 253 254 static int 255 ivpu_ipc_send_receive_internal(struct ivpu_device *vdev, struct vpu_jsm_msg *req, 256 enum vpu_ipc_msg_type expected_resp_type, 257 struct vpu_jsm_msg *resp, u32 channel, 258 unsigned long timeout_ms) 259 { 260 struct ivpu_ipc_consumer cons; 261 int ret; 262 263 ivpu_ipc_consumer_add(vdev, &cons, channel); 264 265 ret = ivpu_ipc_send(vdev, &cons, req); 266 if (ret) { 267 ivpu_warn_ratelimited(vdev, "IPC send failed: %d\n", ret); 268 goto consumer_del; 269 } 270 271 ret = ivpu_ipc_receive(vdev, &cons, NULL, resp, timeout_ms); 272 if (ret) { 273 ivpu_warn_ratelimited(vdev, "IPC receive failed: type %s, ret %d\n", 274 ivpu_jsm_msg_type_to_str(req->type), ret); 275 goto consumer_del; 276 } 277 278 if (resp->type != expected_resp_type) { 279 ivpu_warn_ratelimited(vdev, "Invalid JSM response type: 0x%x\n", resp->type); 280 ret = -EBADE; 281 } 282 283 consumer_del: 284 ivpu_ipc_consumer_del(vdev, &cons); 285 return ret; 286 } 287 288 int ivpu_ipc_send_receive(struct ivpu_device *vdev, struct vpu_jsm_msg *req, 289 enum vpu_ipc_msg_type expected_resp_type, 290 struct vpu_jsm_msg *resp, u32 channel, 291 unsigned long timeout_ms) 292 { 293 struct vpu_jsm_msg hb_req = { .type = VPU_JSM_MSG_QUERY_ENGINE_HB }; 294 struct vpu_jsm_msg hb_resp; 295 int ret, hb_ret; 296 297 ret = ivpu_rpm_get(vdev); 298 if (ret < 0) 299 return ret; 300 301 ret = ivpu_ipc_send_receive_internal(vdev, req, expected_resp_type, resp, 302 channel, timeout_ms); 303 if (ret != -ETIMEDOUT) 304 goto rpm_put; 305 306 hb_ret = ivpu_ipc_send_receive_internal(vdev, &hb_req, VPU_JSM_MSG_QUERY_ENGINE_HB_DONE, 307 &hb_resp, VPU_IPC_CHAN_ASYNC_CMD, 308 vdev->timeout.jsm); 309 if (hb_ret == -ETIMEDOUT) { 310 ivpu_hw_diagnose_failure(vdev); 311 ivpu_pm_schedule_recovery(vdev); 312 } 313 314 rpm_put: 315 ivpu_rpm_put(vdev); 316 return ret; 317 } 318 319 static bool 320 ivpu_ipc_match_consumer(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 321 struct ivpu_ipc_hdr *ipc_hdr, struct vpu_jsm_msg *jsm_msg) 322 { 323 if (cons->channel != ipc_hdr->channel) 324 return false; 325 326 if (!jsm_msg || jsm_msg->request_id == cons->request_id) 327 return true; 328 329 return false; 330 } 331 332 static void 333 ivpu_ipc_dispatch(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 334 struct ivpu_ipc_hdr *ipc_hdr, struct vpu_jsm_msg *jsm_msg) 335 { 336 struct ivpu_ipc_info *ipc = vdev->ipc; 337 struct ivpu_ipc_rx_msg *rx_msg; 338 unsigned long flags; 339 340 lockdep_assert_held(&ipc->cons_list_lock); 341 342 rx_msg = kzalloc(sizeof(*rx_msg), GFP_ATOMIC); 343 if (!rx_msg) { 344 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg); 345 return; 346 } 347 348 atomic_inc(&ipc->rx_msg_count); 349 350 rx_msg->ipc_hdr = ipc_hdr; 351 rx_msg->jsm_msg = jsm_msg; 352 353 spin_lock_irqsave(&cons->rx_msg_lock, flags); 354 list_add_tail(&rx_msg->link, &cons->rx_msg_list); 355 spin_unlock_irqrestore(&cons->rx_msg_lock, flags); 356 357 wake_up(&cons->rx_msg_wq); 358 } 359 360 int ivpu_ipc_irq_handler(struct ivpu_device *vdev) 361 { 362 struct ivpu_ipc_info *ipc = vdev->ipc; 363 struct ivpu_ipc_consumer *cons; 364 struct ivpu_ipc_hdr *ipc_hdr; 365 struct vpu_jsm_msg *jsm_msg; 366 unsigned long flags; 367 bool dispatched; 368 u32 vpu_addr; 369 370 /* 371 * Driver needs to purge all messages from IPC FIFO to clear IPC interrupt. 372 * Without purge IPC FIFO to 0 next IPC interrupts won't be generated. 373 */ 374 while (ivpu_hw_reg_ipc_rx_count_get(vdev)) { 375 vpu_addr = ivpu_hw_reg_ipc_rx_addr_get(vdev); 376 if (vpu_addr == REG_IO_ERROR) { 377 ivpu_err_ratelimited(vdev, "Failed to read IPC rx addr register\n"); 378 return -EIO; 379 } 380 381 ipc_hdr = ivpu_to_cpu_addr(ipc->mem_rx, vpu_addr); 382 if (!ipc_hdr) { 383 ivpu_warn_ratelimited(vdev, "IPC msg 0x%x out of range\n", vpu_addr); 384 continue; 385 } 386 ivpu_ipc_msg_dump(vdev, "RX", ipc_hdr, vpu_addr); 387 388 jsm_msg = NULL; 389 if (ipc_hdr->channel != IVPU_IPC_CHAN_BOOT_MSG) { 390 jsm_msg = ivpu_to_cpu_addr(ipc->mem_rx, ipc_hdr->data_addr); 391 if (!jsm_msg) { 392 ivpu_warn_ratelimited(vdev, "JSM msg 0x%x out of range\n", 393 ipc_hdr->data_addr); 394 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, NULL); 395 continue; 396 } 397 ivpu_jsm_msg_dump(vdev, "RX", jsm_msg, ipc_hdr->data_addr); 398 } 399 400 if (atomic_read(&ipc->rx_msg_count) > IPC_MAX_RX_MSG) { 401 ivpu_warn_ratelimited(vdev, "IPC RX msg dropped, msg count %d\n", 402 IPC_MAX_RX_MSG); 403 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg); 404 continue; 405 } 406 407 dispatched = false; 408 spin_lock_irqsave(&ipc->cons_list_lock, flags); 409 list_for_each_entry(cons, &ipc->cons_list, link) { 410 if (ivpu_ipc_match_consumer(vdev, cons, ipc_hdr, jsm_msg)) { 411 ivpu_ipc_dispatch(vdev, cons, ipc_hdr, jsm_msg); 412 dispatched = true; 413 break; 414 } 415 } 416 spin_unlock_irqrestore(&ipc->cons_list_lock, flags); 417 418 if (!dispatched) { 419 ivpu_dbg(vdev, IPC, "IPC RX msg 0x%x dropped (no consumer)\n", vpu_addr); 420 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg); 421 } 422 } 423 424 return 0; 425 } 426 427 int ivpu_ipc_init(struct ivpu_device *vdev) 428 { 429 struct ivpu_ipc_info *ipc = vdev->ipc; 430 int ret; 431 432 ipc->mem_tx = ivpu_bo_alloc_internal(vdev, 0, SZ_16K, DRM_IVPU_BO_WC); 433 if (!ipc->mem_tx) { 434 ivpu_err(vdev, "Failed to allocate mem_tx\n"); 435 return -ENOMEM; 436 } 437 438 ipc->mem_rx = ivpu_bo_alloc_internal(vdev, 0, SZ_16K, DRM_IVPU_BO_WC); 439 if (!ipc->mem_rx) { 440 ivpu_err(vdev, "Failed to allocate mem_rx\n"); 441 ret = -ENOMEM; 442 goto err_free_tx; 443 } 444 445 ipc->mm_tx = devm_gen_pool_create(vdev->drm.dev, __ffs(IVPU_IPC_ALIGNMENT), 446 -1, "TX_IPC_JSM"); 447 if (IS_ERR(ipc->mm_tx)) { 448 ret = PTR_ERR(ipc->mm_tx); 449 ivpu_err(vdev, "Failed to create gen pool, %pe\n", ipc->mm_tx); 450 goto err_free_rx; 451 } 452 453 ret = gen_pool_add(ipc->mm_tx, ipc->mem_tx->vpu_addr, ivpu_bo_size(ipc->mem_tx), -1); 454 if (ret) { 455 ivpu_err(vdev, "gen_pool_add failed, ret %d\n", ret); 456 goto err_free_rx; 457 } 458 459 INIT_LIST_HEAD(&ipc->cons_list); 460 spin_lock_init(&ipc->cons_list_lock); 461 drmm_mutex_init(&vdev->drm, &ipc->lock); 462 463 ivpu_ipc_reset(vdev); 464 return 0; 465 466 err_free_rx: 467 ivpu_bo_free_internal(ipc->mem_rx); 468 err_free_tx: 469 ivpu_bo_free_internal(ipc->mem_tx); 470 return ret; 471 } 472 473 void ivpu_ipc_fini(struct ivpu_device *vdev) 474 { 475 ivpu_ipc_mem_fini(vdev); 476 } 477 478 void ivpu_ipc_enable(struct ivpu_device *vdev) 479 { 480 struct ivpu_ipc_info *ipc = vdev->ipc; 481 482 mutex_lock(&ipc->lock); 483 ipc->on = true; 484 mutex_unlock(&ipc->lock); 485 } 486 487 void ivpu_ipc_disable(struct ivpu_device *vdev) 488 { 489 struct ivpu_ipc_info *ipc = vdev->ipc; 490 struct ivpu_ipc_consumer *cons, *c; 491 unsigned long flags; 492 493 mutex_lock(&ipc->lock); 494 ipc->on = false; 495 mutex_unlock(&ipc->lock); 496 497 spin_lock_irqsave(&ipc->cons_list_lock, flags); 498 list_for_each_entry_safe(cons, c, &ipc->cons_list, link) 499 wake_up(&cons->rx_msg_wq); 500 spin_unlock_irqrestore(&ipc->cons_list_lock, flags); 501 } 502 503 void ivpu_ipc_reset(struct ivpu_device *vdev) 504 { 505 struct ivpu_ipc_info *ipc = vdev->ipc; 506 507 mutex_lock(&ipc->lock); 508 509 memset(ivpu_bo_vaddr(ipc->mem_tx), 0, ivpu_bo_size(ipc->mem_tx)); 510 memset(ivpu_bo_vaddr(ipc->mem_rx), 0, ivpu_bo_size(ipc->mem_rx)); 511 wmb(); /* Flush WC buffers for TX and RX rings */ 512 513 mutex_unlock(&ipc->lock); 514 } 515