1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020-2023 Intel Corporation 4 */ 5 6 #include <linux/genalloc.h> 7 #include <linux/highmem.h> 8 #include <linux/kthread.h> 9 #include <linux/wait.h> 10 11 #include "ivpu_drv.h" 12 #include "ivpu_gem.h" 13 #include "ivpu_hw.h" 14 #include "ivpu_hw_reg_io.h" 15 #include "ivpu_ipc.h" 16 #include "ivpu_jsm_msg.h" 17 18 #define IPC_MAX_RX_MSG 128 19 #define IS_KTHREAD() (get_current()->flags & PF_KTHREAD) 20 21 struct ivpu_ipc_tx_buf { 22 struct ivpu_ipc_hdr ipc; 23 struct vpu_jsm_msg jsm; 24 }; 25 26 struct ivpu_ipc_rx_msg { 27 struct list_head link; 28 struct ivpu_ipc_hdr *ipc_hdr; 29 struct vpu_jsm_msg *jsm_msg; 30 }; 31 32 static void ivpu_ipc_msg_dump(struct ivpu_device *vdev, char *c, 33 struct ivpu_ipc_hdr *ipc_hdr, u32 vpu_addr) 34 { 35 ivpu_dbg(vdev, IPC, 36 "%s: vpu:0x%x (data_addr:0x%08x, data_size:0x%x, channel:0x%x, src_node:0x%x, dst_node:0x%x, status:0x%x)", 37 c, vpu_addr, ipc_hdr->data_addr, ipc_hdr->data_size, ipc_hdr->channel, 38 ipc_hdr->src_node, ipc_hdr->dst_node, ipc_hdr->status); 39 } 40 41 static void ivpu_jsm_msg_dump(struct ivpu_device *vdev, char *c, 42 struct vpu_jsm_msg *jsm_msg, u32 vpu_addr) 43 { 44 u32 *payload = (u32 *)&jsm_msg->payload; 45 46 ivpu_dbg(vdev, JSM, 47 "%s: vpu:0x%08x (type:0x%x, status:0x%x, id: 0x%x, result: 0x%x, payload:0x%x 0x%x 0x%x 0x%x 0x%x)\n", 48 c, vpu_addr, jsm_msg->type, jsm_msg->status, jsm_msg->request_id, jsm_msg->result, 49 payload[0], payload[1], payload[2], payload[3], payload[4]); 50 } 51 52 static void 53 ivpu_ipc_rx_mark_free(struct ivpu_device *vdev, struct ivpu_ipc_hdr *ipc_hdr, 54 struct vpu_jsm_msg *jsm_msg) 55 { 56 ipc_hdr->status = IVPU_IPC_HDR_FREE; 57 if (jsm_msg) 58 jsm_msg->status = VPU_JSM_MSG_FREE; 59 wmb(); /* Flush WC buffers for message statuses */ 60 } 61 62 static void ivpu_ipc_mem_fini(struct ivpu_device *vdev) 63 { 64 struct ivpu_ipc_info *ipc = vdev->ipc; 65 66 ivpu_bo_free_internal(ipc->mem_rx); 67 ivpu_bo_free_internal(ipc->mem_tx); 68 } 69 70 static int 71 ivpu_ipc_tx_prepare(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 72 struct vpu_jsm_msg *req) 73 { 74 struct ivpu_ipc_info *ipc = vdev->ipc; 75 struct ivpu_ipc_tx_buf *tx_buf; 76 u32 tx_buf_vpu_addr; 77 u32 jsm_vpu_addr; 78 79 tx_buf_vpu_addr = gen_pool_alloc(ipc->mm_tx, sizeof(*tx_buf)); 80 if (!tx_buf_vpu_addr) { 81 ivpu_err(vdev, "Failed to reserve IPC buffer, size %ld\n", 82 sizeof(*tx_buf)); 83 return -ENOMEM; 84 } 85 86 tx_buf = ivpu_to_cpu_addr(ipc->mem_tx, tx_buf_vpu_addr); 87 if (drm_WARN_ON(&vdev->drm, !tx_buf)) { 88 gen_pool_free(ipc->mm_tx, tx_buf_vpu_addr, sizeof(*tx_buf)); 89 return -EIO; 90 } 91 92 jsm_vpu_addr = tx_buf_vpu_addr + offsetof(struct ivpu_ipc_tx_buf, jsm); 93 94 if (tx_buf->ipc.status != IVPU_IPC_HDR_FREE) 95 ivpu_warn(vdev, "IPC message vpu:0x%x not released by firmware\n", 96 tx_buf_vpu_addr); 97 98 if (tx_buf->jsm.status != VPU_JSM_MSG_FREE) 99 ivpu_warn(vdev, "JSM message vpu:0x%x not released by firmware\n", 100 jsm_vpu_addr); 101 102 memset(tx_buf, 0, sizeof(*tx_buf)); 103 tx_buf->ipc.data_addr = jsm_vpu_addr; 104 /* TODO: Set data_size to actual JSM message size, not union of all messages */ 105 tx_buf->ipc.data_size = sizeof(*req); 106 tx_buf->ipc.channel = cons->channel; 107 tx_buf->ipc.src_node = 0; 108 tx_buf->ipc.dst_node = 1; 109 tx_buf->ipc.status = IVPU_IPC_HDR_ALLOCATED; 110 tx_buf->jsm.type = req->type; 111 tx_buf->jsm.status = VPU_JSM_MSG_ALLOCATED; 112 tx_buf->jsm.payload = req->payload; 113 114 req->request_id = atomic_inc_return(&ipc->request_id); 115 tx_buf->jsm.request_id = req->request_id; 116 cons->request_id = req->request_id; 117 wmb(); /* Flush WC buffers for IPC, JSM msgs */ 118 119 cons->tx_vpu_addr = tx_buf_vpu_addr; 120 121 ivpu_jsm_msg_dump(vdev, "TX", &tx_buf->jsm, jsm_vpu_addr); 122 ivpu_ipc_msg_dump(vdev, "TX", &tx_buf->ipc, tx_buf_vpu_addr); 123 124 return 0; 125 } 126 127 static void ivpu_ipc_tx_release(struct ivpu_device *vdev, u32 vpu_addr) 128 { 129 struct ivpu_ipc_info *ipc = vdev->ipc; 130 131 if (vpu_addr) 132 gen_pool_free(ipc->mm_tx, vpu_addr, sizeof(struct ivpu_ipc_tx_buf)); 133 } 134 135 static void ivpu_ipc_tx(struct ivpu_device *vdev, u32 vpu_addr) 136 { 137 ivpu_hw_reg_ipc_tx_set(vdev, vpu_addr); 138 } 139 140 void 141 ivpu_ipc_consumer_add(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, u32 channel) 142 { 143 struct ivpu_ipc_info *ipc = vdev->ipc; 144 145 INIT_LIST_HEAD(&cons->link); 146 cons->channel = channel; 147 cons->tx_vpu_addr = 0; 148 cons->request_id = 0; 149 spin_lock_init(&cons->rx_msg_lock); 150 INIT_LIST_HEAD(&cons->rx_msg_list); 151 init_waitqueue_head(&cons->rx_msg_wq); 152 153 spin_lock_irq(&ipc->cons_list_lock); 154 list_add_tail(&cons->link, &ipc->cons_list); 155 spin_unlock_irq(&ipc->cons_list_lock); 156 } 157 158 void ivpu_ipc_consumer_del(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons) 159 { 160 struct ivpu_ipc_info *ipc = vdev->ipc; 161 struct ivpu_ipc_rx_msg *rx_msg, *r; 162 163 spin_lock_irq(&ipc->cons_list_lock); 164 list_del(&cons->link); 165 spin_unlock_irq(&ipc->cons_list_lock); 166 167 spin_lock_irq(&cons->rx_msg_lock); 168 list_for_each_entry_safe(rx_msg, r, &cons->rx_msg_list, link) { 169 list_del(&rx_msg->link); 170 ivpu_ipc_rx_mark_free(vdev, rx_msg->ipc_hdr, rx_msg->jsm_msg); 171 atomic_dec(&ipc->rx_msg_count); 172 kfree(rx_msg); 173 } 174 spin_unlock_irq(&cons->rx_msg_lock); 175 176 ivpu_ipc_tx_release(vdev, cons->tx_vpu_addr); 177 } 178 179 static int 180 ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, struct vpu_jsm_msg *req) 181 { 182 struct ivpu_ipc_info *ipc = vdev->ipc; 183 int ret; 184 185 ret = mutex_lock_interruptible(&ipc->lock); 186 if (ret) 187 return ret; 188 189 if (!ipc->on) { 190 ret = -EAGAIN; 191 goto unlock; 192 } 193 194 ret = ivpu_ipc_tx_prepare(vdev, cons, req); 195 if (ret) 196 goto unlock; 197 198 ivpu_ipc_tx(vdev, cons->tx_vpu_addr); 199 200 unlock: 201 mutex_unlock(&ipc->lock); 202 return ret; 203 } 204 205 int ivpu_ipc_receive(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 206 struct ivpu_ipc_hdr *ipc_buf, 207 struct vpu_jsm_msg *ipc_payload, unsigned long timeout_ms) 208 { 209 struct ivpu_ipc_info *ipc = vdev->ipc; 210 struct ivpu_ipc_rx_msg *rx_msg; 211 int wait_ret, ret = 0; 212 213 wait_ret = wait_event_interruptible_timeout(cons->rx_msg_wq, 214 (IS_KTHREAD() && kthread_should_stop()) || 215 !list_empty(&cons->rx_msg_list), 216 msecs_to_jiffies(timeout_ms)); 217 218 if (IS_KTHREAD() && kthread_should_stop()) 219 return -EINTR; 220 221 if (wait_ret == 0) 222 return -ETIMEDOUT; 223 224 if (wait_ret < 0) 225 return -ERESTARTSYS; 226 227 spin_lock_irq(&cons->rx_msg_lock); 228 rx_msg = list_first_entry_or_null(&cons->rx_msg_list, struct ivpu_ipc_rx_msg, link); 229 if (!rx_msg) { 230 spin_unlock_irq(&cons->rx_msg_lock); 231 return -EAGAIN; 232 } 233 list_del(&rx_msg->link); 234 spin_unlock_irq(&cons->rx_msg_lock); 235 236 if (ipc_buf) 237 memcpy(ipc_buf, rx_msg->ipc_hdr, sizeof(*ipc_buf)); 238 if (rx_msg->jsm_msg) { 239 u32 size = min_t(int, rx_msg->ipc_hdr->data_size, sizeof(*ipc_payload)); 240 241 if (rx_msg->jsm_msg->result != VPU_JSM_STATUS_SUCCESS) { 242 ivpu_dbg(vdev, IPC, "IPC resp result error: %d\n", rx_msg->jsm_msg->result); 243 ret = -EBADMSG; 244 } 245 246 if (ipc_payload) 247 memcpy(ipc_payload, rx_msg->jsm_msg, size); 248 } 249 250 ivpu_ipc_rx_mark_free(vdev, rx_msg->ipc_hdr, rx_msg->jsm_msg); 251 atomic_dec(&ipc->rx_msg_count); 252 kfree(rx_msg); 253 254 return ret; 255 } 256 257 static int 258 ivpu_ipc_send_receive_internal(struct ivpu_device *vdev, struct vpu_jsm_msg *req, 259 enum vpu_ipc_msg_type expected_resp_type, 260 struct vpu_jsm_msg *resp, u32 channel, 261 unsigned long timeout_ms) 262 { 263 struct ivpu_ipc_consumer cons; 264 int ret; 265 266 ivpu_ipc_consumer_add(vdev, &cons, channel); 267 268 ret = ivpu_ipc_send(vdev, &cons, req); 269 if (ret) { 270 ivpu_warn(vdev, "IPC send failed: %d\n", ret); 271 goto consumer_del; 272 } 273 274 ret = ivpu_ipc_receive(vdev, &cons, NULL, resp, timeout_ms); 275 if (ret) { 276 ivpu_warn(vdev, "IPC receive failed: type 0x%x, ret %d\n", req->type, ret); 277 goto consumer_del; 278 } 279 280 if (resp->type != expected_resp_type) { 281 ivpu_warn(vdev, "Invalid JSM response type: 0x%x\n", resp->type); 282 ret = -EBADE; 283 } 284 285 consumer_del: 286 ivpu_ipc_consumer_del(vdev, &cons); 287 return ret; 288 } 289 290 int ivpu_ipc_send_receive(struct ivpu_device *vdev, struct vpu_jsm_msg *req, 291 enum vpu_ipc_msg_type expected_resp_type, 292 struct vpu_jsm_msg *resp, u32 channel, 293 unsigned long timeout_ms) 294 { 295 struct vpu_jsm_msg hb_req = { .type = VPU_JSM_MSG_QUERY_ENGINE_HB }; 296 struct vpu_jsm_msg hb_resp; 297 int ret; 298 299 ret = ivpu_ipc_send_receive_internal(vdev, req, expected_resp_type, resp, 300 channel, timeout_ms); 301 if (ret != -ETIMEDOUT) 302 return ret; 303 304 ret = ivpu_ipc_send_receive_internal(vdev, &hb_req, VPU_JSM_MSG_QUERY_ENGINE_HB_DONE, 305 &hb_resp, VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); 306 if (ret == -ETIMEDOUT) 307 ivpu_hw_diagnose_failure(vdev); 308 309 return ret; 310 } 311 312 static bool 313 ivpu_ipc_match_consumer(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 314 struct ivpu_ipc_hdr *ipc_hdr, struct vpu_jsm_msg *jsm_msg) 315 { 316 if (cons->channel != ipc_hdr->channel) 317 return false; 318 319 if (!jsm_msg || jsm_msg->request_id == cons->request_id) 320 return true; 321 322 return false; 323 } 324 325 static void 326 ivpu_ipc_dispatch(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 327 struct ivpu_ipc_hdr *ipc_hdr, struct vpu_jsm_msg *jsm_msg) 328 { 329 struct ivpu_ipc_info *ipc = vdev->ipc; 330 struct ivpu_ipc_rx_msg *rx_msg; 331 unsigned long flags; 332 333 lockdep_assert_held(&ipc->cons_list_lock); 334 335 rx_msg = kzalloc(sizeof(*rx_msg), GFP_ATOMIC); 336 if (!rx_msg) { 337 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg); 338 return; 339 } 340 341 atomic_inc(&ipc->rx_msg_count); 342 343 rx_msg->ipc_hdr = ipc_hdr; 344 rx_msg->jsm_msg = jsm_msg; 345 346 spin_lock_irqsave(&cons->rx_msg_lock, flags); 347 list_add_tail(&rx_msg->link, &cons->rx_msg_list); 348 spin_unlock_irqrestore(&cons->rx_msg_lock, flags); 349 350 wake_up(&cons->rx_msg_wq); 351 } 352 353 int ivpu_ipc_irq_handler(struct ivpu_device *vdev) 354 { 355 struct ivpu_ipc_info *ipc = vdev->ipc; 356 struct ivpu_ipc_consumer *cons; 357 struct ivpu_ipc_hdr *ipc_hdr; 358 struct vpu_jsm_msg *jsm_msg; 359 unsigned long flags; 360 bool dispatched; 361 u32 vpu_addr; 362 363 /* 364 * Driver needs to purge all messages from IPC FIFO to clear IPC interrupt. 365 * Without purge IPC FIFO to 0 next IPC interrupts won't be generated. 366 */ 367 while (ivpu_hw_reg_ipc_rx_count_get(vdev)) { 368 vpu_addr = ivpu_hw_reg_ipc_rx_addr_get(vdev); 369 if (vpu_addr == REG_IO_ERROR) { 370 ivpu_err(vdev, "Failed to read IPC rx addr register\n"); 371 return -EIO; 372 } 373 374 ipc_hdr = ivpu_to_cpu_addr(ipc->mem_rx, vpu_addr); 375 if (!ipc_hdr) { 376 ivpu_warn(vdev, "IPC msg 0x%x out of range\n", vpu_addr); 377 continue; 378 } 379 ivpu_ipc_msg_dump(vdev, "RX", ipc_hdr, vpu_addr); 380 381 jsm_msg = NULL; 382 if (ipc_hdr->channel != IVPU_IPC_CHAN_BOOT_MSG) { 383 jsm_msg = ivpu_to_cpu_addr(ipc->mem_rx, ipc_hdr->data_addr); 384 if (!jsm_msg) { 385 ivpu_warn(vdev, "JSM msg 0x%x out of range\n", ipc_hdr->data_addr); 386 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, NULL); 387 continue; 388 } 389 ivpu_jsm_msg_dump(vdev, "RX", jsm_msg, ipc_hdr->data_addr); 390 } 391 392 if (atomic_read(&ipc->rx_msg_count) > IPC_MAX_RX_MSG) { 393 ivpu_warn(vdev, "IPC RX msg dropped, msg count %d\n", IPC_MAX_RX_MSG); 394 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg); 395 continue; 396 } 397 398 dispatched = false; 399 spin_lock_irqsave(&ipc->cons_list_lock, flags); 400 list_for_each_entry(cons, &ipc->cons_list, link) { 401 if (ivpu_ipc_match_consumer(vdev, cons, ipc_hdr, jsm_msg)) { 402 ivpu_ipc_dispatch(vdev, cons, ipc_hdr, jsm_msg); 403 dispatched = true; 404 break; 405 } 406 } 407 spin_unlock_irqrestore(&ipc->cons_list_lock, flags); 408 409 if (!dispatched) { 410 ivpu_dbg(vdev, IPC, "IPC RX msg 0x%x dropped (no consumer)\n", vpu_addr); 411 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg); 412 } 413 } 414 415 return 0; 416 } 417 418 int ivpu_ipc_init(struct ivpu_device *vdev) 419 { 420 struct ivpu_ipc_info *ipc = vdev->ipc; 421 int ret = -ENOMEM; 422 423 ipc->mem_tx = ivpu_bo_alloc_internal(vdev, 0, SZ_16K, DRM_IVPU_BO_WC); 424 if (!ipc->mem_tx) 425 return ret; 426 427 ipc->mem_rx = ivpu_bo_alloc_internal(vdev, 0, SZ_16K, DRM_IVPU_BO_WC); 428 if (!ipc->mem_rx) 429 goto err_free_tx; 430 431 ipc->mm_tx = devm_gen_pool_create(vdev->drm.dev, __ffs(IVPU_IPC_ALIGNMENT), 432 -1, "TX_IPC_JSM"); 433 if (IS_ERR(ipc->mm_tx)) { 434 ret = PTR_ERR(ipc->mm_tx); 435 ivpu_err(vdev, "Failed to create gen pool, %pe\n", ipc->mm_tx); 436 goto err_free_rx; 437 } 438 439 ret = gen_pool_add(ipc->mm_tx, ipc->mem_tx->vpu_addr, ipc->mem_tx->base.size, -1); 440 if (ret) { 441 ivpu_err(vdev, "gen_pool_add failed, ret %d\n", ret); 442 goto err_free_rx; 443 } 444 445 INIT_LIST_HEAD(&ipc->cons_list); 446 spin_lock_init(&ipc->cons_list_lock); 447 drmm_mutex_init(&vdev->drm, &ipc->lock); 448 449 ivpu_ipc_reset(vdev); 450 return 0; 451 452 err_free_rx: 453 ivpu_bo_free_internal(ipc->mem_rx); 454 err_free_tx: 455 ivpu_bo_free_internal(ipc->mem_tx); 456 return ret; 457 } 458 459 void ivpu_ipc_fini(struct ivpu_device *vdev) 460 { 461 ivpu_ipc_mem_fini(vdev); 462 } 463 464 void ivpu_ipc_enable(struct ivpu_device *vdev) 465 { 466 struct ivpu_ipc_info *ipc = vdev->ipc; 467 468 mutex_lock(&ipc->lock); 469 ipc->on = true; 470 mutex_unlock(&ipc->lock); 471 } 472 473 void ivpu_ipc_disable(struct ivpu_device *vdev) 474 { 475 struct ivpu_ipc_info *ipc = vdev->ipc; 476 struct ivpu_ipc_consumer *cons, *c; 477 unsigned long flags; 478 479 mutex_lock(&ipc->lock); 480 ipc->on = false; 481 mutex_unlock(&ipc->lock); 482 483 spin_lock_irqsave(&ipc->cons_list_lock, flags); 484 list_for_each_entry_safe(cons, c, &ipc->cons_list, link) 485 wake_up(&cons->rx_msg_wq); 486 spin_unlock_irqrestore(&ipc->cons_list_lock, flags); 487 } 488 489 void ivpu_ipc_reset(struct ivpu_device *vdev) 490 { 491 struct ivpu_ipc_info *ipc = vdev->ipc; 492 493 mutex_lock(&ipc->lock); 494 495 memset(ipc->mem_tx->kvaddr, 0, ipc->mem_tx->base.size); 496 memset(ipc->mem_rx->kvaddr, 0, ipc->mem_rx->base.size); 497 wmb(); /* Flush WC buffers for TX and RX rings */ 498 499 mutex_unlock(&ipc->lock); 500 } 501