1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020 - 2024 Intel Corporation 4 */ 5 6 #include "ivpu_drv.h" 7 #include "ivpu_hw.h" 8 #include "ivpu_hw_btrs.h" 9 #include "ivpu_hw_ip.h" 10 11 #include <linux/dmi.h> 12 13 static char *platform_to_str(u32 platform) 14 { 15 switch (platform) { 16 case IVPU_PLATFORM_SILICON: 17 return "SILICON"; 18 case IVPU_PLATFORM_SIMICS: 19 return "SIMICS"; 20 case IVPU_PLATFORM_FPGA: 21 return "FPGA"; 22 default: 23 return "Invalid platform"; 24 } 25 } 26 27 static const struct dmi_system_id dmi_platform_simulation[] = { 28 { 29 .ident = "Intel Simics", 30 .matches = { 31 DMI_MATCH(DMI_BOARD_NAME, "lnlrvp"), 32 DMI_MATCH(DMI_BOARD_VERSION, "1.0"), 33 DMI_MATCH(DMI_BOARD_SERIAL, "123456789"), 34 }, 35 }, 36 { 37 .ident = "Intel Simics", 38 .matches = { 39 DMI_MATCH(DMI_BOARD_NAME, "Simics"), 40 }, 41 }, 42 { } 43 }; 44 45 static void platform_init(struct ivpu_device *vdev) 46 { 47 if (dmi_check_system(dmi_platform_simulation)) 48 vdev->platform = IVPU_PLATFORM_SIMICS; 49 else 50 vdev->platform = IVPU_PLATFORM_SILICON; 51 52 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", 53 platform_to_str(vdev->platform), vdev->platform); 54 } 55 56 static void wa_init(struct ivpu_device *vdev) 57 { 58 vdev->wa.punit_disabled = ivpu_is_fpga(vdev); 59 vdev->wa.clear_runtime_mem = false; 60 61 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) 62 vdev->wa.interrupt_clear_with_0 = ivpu_hw_btrs_irqs_clear_with_0_mtl(vdev); 63 64 if (ivpu_device_id(vdev) == PCI_DEVICE_ID_LNL) 65 vdev->wa.disable_clock_relinquish = true; 66 67 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) 68 vdev->wa.wp0_during_power_up = true; 69 70 IVPU_PRINT_WA(punit_disabled); 71 IVPU_PRINT_WA(clear_runtime_mem); 72 IVPU_PRINT_WA(interrupt_clear_with_0); 73 IVPU_PRINT_WA(disable_clock_relinquish); 74 IVPU_PRINT_WA(wp0_during_power_up); 75 } 76 77 static void timeouts_init(struct ivpu_device *vdev) 78 { 79 if (ivpu_is_fpga(vdev)) { 80 vdev->timeout.boot = 100000; 81 vdev->timeout.jsm = 50000; 82 vdev->timeout.tdr = 2000000; 83 vdev->timeout.reschedule_suspend = 1000; 84 vdev->timeout.autosuspend = -1; 85 vdev->timeout.d0i3_entry_msg = 500; 86 } else if (ivpu_is_simics(vdev)) { 87 vdev->timeout.boot = 50; 88 vdev->timeout.jsm = 500; 89 vdev->timeout.tdr = 10000; 90 vdev->timeout.reschedule_suspend = 10; 91 vdev->timeout.autosuspend = -1; 92 vdev->timeout.d0i3_entry_msg = 100; 93 } else { 94 vdev->timeout.boot = 1000; 95 vdev->timeout.jsm = 500; 96 vdev->timeout.tdr = 2000; 97 vdev->timeout.reschedule_suspend = 10; 98 vdev->timeout.autosuspend = 10; 99 vdev->timeout.d0i3_entry_msg = 5; 100 } 101 } 102 103 static void memory_ranges_init(struct ivpu_device *vdev) 104 { 105 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { 106 ivpu_hw_range_init(&vdev->hw->ranges.global, 0x80000000, SZ_512M); 107 ivpu_hw_range_init(&vdev->hw->ranges.user, 0xc0000000, 255 * SZ_1M); 108 ivpu_hw_range_init(&vdev->hw->ranges.shave, 0x180000000, SZ_2G); 109 ivpu_hw_range_init(&vdev->hw->ranges.dma, 0x200000000, SZ_8G); 110 } else { 111 ivpu_hw_range_init(&vdev->hw->ranges.global, 0x80000000, SZ_512M); 112 ivpu_hw_range_init(&vdev->hw->ranges.user, 0x80000000, SZ_256M); 113 ivpu_hw_range_init(&vdev->hw->ranges.shave, 0x80000000 + SZ_256M, SZ_2G - SZ_256M); 114 ivpu_hw_range_init(&vdev->hw->ranges.dma, 0x200000000, SZ_8G); 115 } 116 } 117 118 static int wp_enable(struct ivpu_device *vdev) 119 { 120 return ivpu_hw_btrs_wp_drive(vdev, true); 121 } 122 123 static int wp_disable(struct ivpu_device *vdev) 124 { 125 return ivpu_hw_btrs_wp_drive(vdev, false); 126 } 127 128 int ivpu_hw_power_up(struct ivpu_device *vdev) 129 { 130 int ret; 131 132 if (IVPU_WA(wp0_during_power_up)) { 133 /* WP requests may fail when powering down, so issue WP 0 here */ 134 ret = wp_disable(vdev); 135 if (ret) 136 ivpu_warn(vdev, "Failed to disable workpoint: %d\n", ret); 137 } 138 139 ret = ivpu_hw_btrs_d0i3_disable(vdev); 140 if (ret) 141 ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret); 142 143 ret = wp_enable(vdev); 144 if (ret) { 145 ivpu_err(vdev, "Failed to enable workpoint: %d\n", ret); 146 return ret; 147 } 148 149 if (ivpu_hw_btrs_gen(vdev) >= IVPU_HW_BTRS_LNL) { 150 if (IVPU_WA(disable_clock_relinquish)) 151 ivpu_hw_btrs_clock_relinquish_disable_lnl(vdev); 152 ivpu_hw_btrs_profiling_freq_reg_set_lnl(vdev); 153 ivpu_hw_btrs_ats_print_lnl(vdev); 154 } 155 156 ret = ivpu_hw_ip_host_ss_configure(vdev); 157 if (ret) { 158 ivpu_err(vdev, "Failed to configure host SS: %d\n", ret); 159 return ret; 160 } 161 162 ivpu_hw_ip_idle_gen_disable(vdev); 163 164 ret = ivpu_hw_btrs_wait_for_clock_res_own_ack(vdev); 165 if (ret) { 166 ivpu_err(vdev, "Timed out waiting for clock resource own ACK\n"); 167 return ret; 168 } 169 170 ret = ivpu_hw_ip_pwr_domain_enable(vdev); 171 if (ret) { 172 ivpu_err(vdev, "Failed to enable power domain: %d\n", ret); 173 return ret; 174 } 175 176 ret = ivpu_hw_ip_host_ss_axi_enable(vdev); 177 if (ret) { 178 ivpu_err(vdev, "Failed to enable AXI: %d\n", ret); 179 return ret; 180 } 181 182 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_LNL) 183 ivpu_hw_btrs_set_port_arbitration_weights_lnl(vdev); 184 185 ret = ivpu_hw_ip_top_noc_enable(vdev); 186 if (ret) 187 ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret); 188 189 return ret; 190 } 191 192 static void save_d0i3_entry_timestamp(struct ivpu_device *vdev) 193 { 194 vdev->hw->d0i3_entry_host_ts = ktime_get_boottime(); 195 vdev->hw->d0i3_entry_vpu_ts = ivpu_hw_ip_read_perf_timer_counter(vdev); 196 } 197 198 int ivpu_hw_reset(struct ivpu_device *vdev) 199 { 200 int ret = 0; 201 202 if (ivpu_hw_btrs_ip_reset(vdev)) { 203 ivpu_err(vdev, "Failed to reset NPU IP\n"); 204 ret = -EIO; 205 } 206 207 if (wp_disable(vdev)) { 208 ivpu_err(vdev, "Failed to disable workpoint\n"); 209 ret = -EIO; 210 } 211 212 return ret; 213 } 214 215 int ivpu_hw_power_down(struct ivpu_device *vdev) 216 { 217 int ret = 0; 218 219 save_d0i3_entry_timestamp(vdev); 220 221 if (!ivpu_hw_is_idle(vdev)) 222 ivpu_warn(vdev, "NPU not idle during power down\n"); 223 224 if (ivpu_hw_reset(vdev)) { 225 ivpu_err(vdev, "Failed to reset NPU\n"); 226 ret = -EIO; 227 } 228 229 if (ivpu_hw_btrs_d0i3_enable(vdev)) { 230 ivpu_err(vdev, "Failed to enter D0I3\n"); 231 ret = -EIO; 232 } 233 234 return ret; 235 } 236 237 int ivpu_hw_init(struct ivpu_device *vdev) 238 { 239 ivpu_hw_btrs_info_init(vdev); 240 ivpu_hw_btrs_freq_ratios_init(vdev); 241 memory_ranges_init(vdev); 242 platform_init(vdev); 243 wa_init(vdev); 244 timeouts_init(vdev); 245 246 return 0; 247 } 248 249 int ivpu_hw_boot_fw(struct ivpu_device *vdev) 250 { 251 int ret; 252 253 ivpu_hw_ip_snoop_disable(vdev); 254 ivpu_hw_ip_tbu_mmu_enable(vdev); 255 ret = ivpu_hw_ip_soc_cpu_boot(vdev); 256 if (ret) 257 ivpu_err(vdev, "Failed to boot SOC CPU: %d\n", ret); 258 259 return ret; 260 } 261 262 void ivpu_hw_profiling_freq_drive(struct ivpu_device *vdev, bool enable) 263 { 264 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { 265 vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT; 266 return; 267 } 268 269 if (enable) 270 vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_HIGH; 271 else 272 vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT; 273 } 274 275 void ivpu_irq_handlers_init(struct ivpu_device *vdev) 276 { 277 INIT_KFIFO(vdev->hw->irq.fifo); 278 279 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) 280 vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_37xx; 281 else 282 vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_40xx; 283 284 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) 285 vdev->hw->irq.btrs_irq_handler = ivpu_hw_btrs_irq_handler_mtl; 286 else 287 vdev->hw->irq.btrs_irq_handler = ivpu_hw_btrs_irq_handler_lnl; 288 } 289 290 void ivpu_hw_irq_enable(struct ivpu_device *vdev) 291 { 292 kfifo_reset(&vdev->hw->irq.fifo); 293 ivpu_hw_ip_irq_enable(vdev); 294 ivpu_hw_btrs_irq_enable(vdev); 295 } 296 297 void ivpu_hw_irq_disable(struct ivpu_device *vdev) 298 { 299 ivpu_hw_btrs_irq_disable(vdev); 300 ivpu_hw_ip_irq_disable(vdev); 301 } 302 303 irqreturn_t ivpu_hw_irq_handler(int irq, void *ptr) 304 { 305 struct ivpu_device *vdev = ptr; 306 bool ip_handled, btrs_handled; 307 308 ivpu_hw_btrs_global_int_disable(vdev); 309 310 btrs_handled = ivpu_hw_btrs_irq_handler(vdev, irq); 311 if (!ivpu_hw_is_idle((vdev)) || !btrs_handled) 312 ip_handled = ivpu_hw_ip_irq_handler(vdev, irq); 313 else 314 ip_handled = false; 315 316 /* Re-enable global interrupts to re-trigger MSI for pending interrupts */ 317 ivpu_hw_btrs_global_int_enable(vdev); 318 319 if (!kfifo_is_empty(&vdev->hw->irq.fifo)) 320 return IRQ_WAKE_THREAD; 321 if (ip_handled || btrs_handled) 322 return IRQ_HANDLED; 323 return IRQ_NONE; 324 } 325