xref: /linux/drivers/accel/ivpu/ivpu_hw.c (revision 52ab5be191c42fe1bffac97ee248a237b9712889)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2020 - 2024 Intel Corporation
4  */
5 
6 #include "ivpu_drv.h"
7 #include "ivpu_hw.h"
8 #include "ivpu_hw_btrs.h"
9 #include "ivpu_hw_ip.h"
10 
11 #include <linux/dmi.h>
12 
13 static char *platform_to_str(u32 platform)
14 {
15 	switch (platform) {
16 	case IVPU_PLATFORM_SILICON:
17 		return "SILICON";
18 	case IVPU_PLATFORM_SIMICS:
19 		return "SIMICS";
20 	case IVPU_PLATFORM_FPGA:
21 		return "FPGA";
22 	default:
23 		return "Invalid platform";
24 	}
25 }
26 
27 static const struct dmi_system_id dmi_platform_simulation[] = {
28 	{
29 		.ident = "Intel Simics",
30 		.matches = {
31 			DMI_MATCH(DMI_BOARD_NAME, "lnlrvp"),
32 			DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
33 			DMI_MATCH(DMI_BOARD_SERIAL, "123456789"),
34 		},
35 	},
36 	{
37 		.ident = "Intel Simics",
38 		.matches = {
39 			DMI_MATCH(DMI_BOARD_NAME, "Simics"),
40 		},
41 	},
42 	{ }
43 };
44 
45 static void platform_init(struct ivpu_device *vdev)
46 {
47 	if (dmi_check_system(dmi_platform_simulation))
48 		vdev->platform = IVPU_PLATFORM_SIMICS;
49 	else
50 		vdev->platform = IVPU_PLATFORM_SILICON;
51 
52 	ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n",
53 		 platform_to_str(vdev->platform), vdev->platform);
54 }
55 
56 static void wa_init(struct ivpu_device *vdev)
57 {
58 	vdev->wa.punit_disabled = ivpu_is_fpga(vdev);
59 	vdev->wa.clear_runtime_mem = false;
60 
61 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
62 		vdev->wa.interrupt_clear_with_0 = ivpu_hw_btrs_irqs_clear_with_0_mtl(vdev);
63 
64 	if (ivpu_device_id(vdev) == PCI_DEVICE_ID_LNL &&
65 	    ivpu_revision(vdev) < IVPU_HW_IP_REV_LNL_B0)
66 		vdev->wa.disable_clock_relinquish = true;
67 
68 	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
69 		vdev->wa.wp0_during_power_up = true;
70 
71 	IVPU_PRINT_WA(punit_disabled);
72 	IVPU_PRINT_WA(clear_runtime_mem);
73 	IVPU_PRINT_WA(interrupt_clear_with_0);
74 	IVPU_PRINT_WA(disable_clock_relinquish);
75 	IVPU_PRINT_WA(wp0_during_power_up);
76 }
77 
78 static void timeouts_init(struct ivpu_device *vdev)
79 {
80 	if (ivpu_is_fpga(vdev)) {
81 		vdev->timeout.boot = 100000;
82 		vdev->timeout.jsm = 50000;
83 		vdev->timeout.tdr = 2000000;
84 		vdev->timeout.reschedule_suspend = 1000;
85 		vdev->timeout.autosuspend = -1;
86 		vdev->timeout.d0i3_entry_msg = 500;
87 	} else if (ivpu_is_simics(vdev)) {
88 		vdev->timeout.boot = 50;
89 		vdev->timeout.jsm = 500;
90 		vdev->timeout.tdr = 10000;
91 		vdev->timeout.reschedule_suspend = 10;
92 		vdev->timeout.autosuspend = -1;
93 		vdev->timeout.d0i3_entry_msg = 100;
94 	} else {
95 		vdev->timeout.boot = 1000;
96 		vdev->timeout.jsm = 500;
97 		vdev->timeout.tdr = 2000;
98 		vdev->timeout.reschedule_suspend = 10;
99 		vdev->timeout.autosuspend = 10;
100 		vdev->timeout.d0i3_entry_msg = 5;
101 	}
102 }
103 
104 static void memory_ranges_init(struct ivpu_device *vdev)
105 {
106 	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
107 		ivpu_hw_range_init(&vdev->hw->ranges.global, 0x80000000, SZ_512M);
108 		ivpu_hw_range_init(&vdev->hw->ranges.user,   0xc0000000, 255 * SZ_1M);
109 		ivpu_hw_range_init(&vdev->hw->ranges.shave, 0x180000000, SZ_2G);
110 		ivpu_hw_range_init(&vdev->hw->ranges.dma,   0x200000000, SZ_8G);
111 	} else {
112 		ivpu_hw_range_init(&vdev->hw->ranges.global, 0x80000000, SZ_512M);
113 		ivpu_hw_range_init(&vdev->hw->ranges.user,   0x80000000, SZ_256M);
114 		ivpu_hw_range_init(&vdev->hw->ranges.shave,  0x80000000 + SZ_256M, SZ_2G - SZ_256M);
115 		ivpu_hw_range_init(&vdev->hw->ranges.dma,   0x200000000, SZ_8G);
116 	}
117 }
118 
119 static int wp_enable(struct ivpu_device *vdev)
120 {
121 	return ivpu_hw_btrs_wp_drive(vdev, true);
122 }
123 
124 static int wp_disable(struct ivpu_device *vdev)
125 {
126 	return ivpu_hw_btrs_wp_drive(vdev, false);
127 }
128 
129 int ivpu_hw_power_up(struct ivpu_device *vdev)
130 {
131 	int ret;
132 
133 	if (IVPU_WA(wp0_during_power_up)) {
134 		/* WP requests may fail when powering down, so issue WP 0 here */
135 		ret = wp_disable(vdev);
136 		if (ret)
137 			ivpu_warn(vdev, "Failed to disable workpoint: %d\n", ret);
138 	}
139 
140 	ret = ivpu_hw_btrs_d0i3_disable(vdev);
141 	if (ret)
142 		ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret);
143 
144 	ret = wp_enable(vdev);
145 	if (ret) {
146 		ivpu_err(vdev, "Failed to enable workpoint: %d\n", ret);
147 		return ret;
148 	}
149 
150 	if (ivpu_hw_btrs_gen(vdev) >= IVPU_HW_BTRS_LNL) {
151 		if (IVPU_WA(disable_clock_relinquish))
152 			ivpu_hw_btrs_clock_relinquish_disable_lnl(vdev);
153 		ivpu_hw_btrs_profiling_freq_reg_set_lnl(vdev);
154 		ivpu_hw_btrs_ats_print_lnl(vdev);
155 	}
156 
157 	ret = ivpu_hw_ip_host_ss_configure(vdev);
158 	if (ret) {
159 		ivpu_err(vdev, "Failed to configure host SS: %d\n", ret);
160 		return ret;
161 	}
162 
163 	ivpu_hw_ip_idle_gen_disable(vdev);
164 
165 	ret = ivpu_hw_btrs_wait_for_clock_res_own_ack(vdev);
166 	if (ret) {
167 		ivpu_err(vdev, "Timed out waiting for clock resource own ACK\n");
168 		return ret;
169 	}
170 
171 	ret = ivpu_hw_ip_pwr_domain_enable(vdev);
172 	if (ret) {
173 		ivpu_err(vdev, "Failed to enable power domain: %d\n", ret);
174 		return ret;
175 	}
176 
177 	ret = ivpu_hw_ip_host_ss_axi_enable(vdev);
178 	if (ret) {
179 		ivpu_err(vdev, "Failed to enable AXI: %d\n", ret);
180 		return ret;
181 	}
182 
183 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_LNL)
184 		ivpu_hw_btrs_set_port_arbitration_weights_lnl(vdev);
185 
186 	ret = ivpu_hw_ip_top_noc_enable(vdev);
187 	if (ret)
188 		ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret);
189 
190 	return ret;
191 }
192 
193 static void save_d0i3_entry_timestamp(struct ivpu_device *vdev)
194 {
195 	vdev->hw->d0i3_entry_host_ts = ktime_get_boottime();
196 	vdev->hw->d0i3_entry_vpu_ts = ivpu_hw_ip_read_perf_timer_counter(vdev);
197 }
198 
199 int ivpu_hw_reset(struct ivpu_device *vdev)
200 {
201 	int ret = 0;
202 
203 	if (ivpu_hw_btrs_ip_reset(vdev)) {
204 		ivpu_err(vdev, "Failed to reset NPU IP\n");
205 		ret = -EIO;
206 	}
207 
208 	if (wp_disable(vdev)) {
209 		ivpu_err(vdev, "Failed to disable workpoint\n");
210 		ret = -EIO;
211 	}
212 
213 	return ret;
214 }
215 
216 int ivpu_hw_power_down(struct ivpu_device *vdev)
217 {
218 	int ret = 0;
219 
220 	save_d0i3_entry_timestamp(vdev);
221 
222 	if (!ivpu_hw_is_idle(vdev))
223 		ivpu_warn(vdev, "NPU not idle during power down\n");
224 
225 	if (ivpu_hw_reset(vdev)) {
226 		ivpu_err(vdev, "Failed to reset NPU\n");
227 		ret = -EIO;
228 	}
229 
230 	if (ivpu_hw_btrs_d0i3_enable(vdev)) {
231 		ivpu_err(vdev, "Failed to enter D0I3\n");
232 		ret = -EIO;
233 	}
234 
235 	return ret;
236 }
237 
238 int ivpu_hw_init(struct ivpu_device *vdev)
239 {
240 	ivpu_hw_btrs_info_init(vdev);
241 	ivpu_hw_btrs_freq_ratios_init(vdev);
242 	memory_ranges_init(vdev);
243 	platform_init(vdev);
244 	wa_init(vdev);
245 	timeouts_init(vdev);
246 
247 	return 0;
248 }
249 
250 int ivpu_hw_boot_fw(struct ivpu_device *vdev)
251 {
252 	int ret;
253 
254 	ivpu_hw_ip_snoop_disable(vdev);
255 	ivpu_hw_ip_tbu_mmu_enable(vdev);
256 	ret = ivpu_hw_ip_soc_cpu_boot(vdev);
257 	if (ret)
258 		ivpu_err(vdev, "Failed to boot SOC CPU: %d\n", ret);
259 
260 	return ret;
261 }
262 
263 void ivpu_hw_profiling_freq_drive(struct ivpu_device *vdev, bool enable)
264 {
265 	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
266 		vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
267 		return;
268 	}
269 
270 	if (enable)
271 		vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_HIGH;
272 	else
273 		vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
274 }
275 
276 void ivpu_irq_handlers_init(struct ivpu_device *vdev)
277 {
278 	INIT_KFIFO(vdev->hw->irq.fifo);
279 
280 	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
281 		vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_37xx;
282 	else
283 		vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_40xx;
284 
285 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
286 		vdev->hw->irq.btrs_irq_handler = ivpu_hw_btrs_irq_handler_mtl;
287 	else
288 		vdev->hw->irq.btrs_irq_handler = ivpu_hw_btrs_irq_handler_lnl;
289 }
290 
291 void ivpu_hw_irq_enable(struct ivpu_device *vdev)
292 {
293 	kfifo_reset(&vdev->hw->irq.fifo);
294 	ivpu_hw_ip_irq_enable(vdev);
295 	ivpu_hw_btrs_irq_enable(vdev);
296 }
297 
298 void ivpu_hw_irq_disable(struct ivpu_device *vdev)
299 {
300 	ivpu_hw_btrs_irq_disable(vdev);
301 	ivpu_hw_ip_irq_disable(vdev);
302 }
303 
304 irqreturn_t ivpu_hw_irq_handler(int irq, void *ptr)
305 {
306 	struct ivpu_device *vdev = ptr;
307 	bool ip_handled, btrs_handled;
308 
309 	ivpu_hw_btrs_global_int_disable(vdev);
310 
311 	btrs_handled = ivpu_hw_btrs_irq_handler(vdev, irq);
312 	if (!ivpu_hw_is_idle((vdev)) || !btrs_handled)
313 		ip_handled = ivpu_hw_ip_irq_handler(vdev, irq);
314 	else
315 		ip_handled = false;
316 
317 	/* Re-enable global interrupts to re-trigger MSI for pending interrupts */
318 	ivpu_hw_btrs_global_int_enable(vdev);
319 
320 	if (!kfifo_is_empty(&vdev->hw->irq.fifo))
321 		return IRQ_WAKE_THREAD;
322 	if (ip_handled || btrs_handled)
323 		return IRQ_HANDLED;
324 	return IRQ_NONE;
325 }
326