1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020 - 2024 Intel Corporation 4 */ 5 6 #include "ivpu_drv.h" 7 #include "ivpu_hw.h" 8 #include "ivpu_hw_btrs.h" 9 #include "ivpu_hw_ip.h" 10 11 #include <linux/dmi.h> 12 13 static char *platform_to_str(u32 platform) 14 { 15 switch (platform) { 16 case IVPU_PLATFORM_SILICON: 17 return "SILICON"; 18 case IVPU_PLATFORM_SIMICS: 19 return "SIMICS"; 20 case IVPU_PLATFORM_FPGA: 21 return "FPGA"; 22 default: 23 return "Invalid platform"; 24 } 25 } 26 27 static const struct dmi_system_id dmi_platform_simulation[] = { 28 { 29 .ident = "Intel Simics", 30 .matches = { 31 DMI_MATCH(DMI_BOARD_NAME, "lnlrvp"), 32 DMI_MATCH(DMI_BOARD_VERSION, "1.0"), 33 DMI_MATCH(DMI_BOARD_SERIAL, "123456789"), 34 }, 35 }, 36 { 37 .ident = "Intel Simics", 38 .matches = { 39 DMI_MATCH(DMI_BOARD_NAME, "Simics"), 40 }, 41 }, 42 { } 43 }; 44 45 static void platform_init(struct ivpu_device *vdev) 46 { 47 if (dmi_check_system(dmi_platform_simulation)) 48 vdev->platform = IVPU_PLATFORM_SIMICS; 49 else 50 vdev->platform = IVPU_PLATFORM_SILICON; 51 52 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", 53 platform_to_str(vdev->platform), vdev->platform); 54 } 55 56 static void wa_init(struct ivpu_device *vdev) 57 { 58 vdev->wa.punit_disabled = ivpu_is_fpga(vdev); 59 vdev->wa.clear_runtime_mem = false; 60 61 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) 62 vdev->wa.interrupt_clear_with_0 = ivpu_hw_btrs_irqs_clear_with_0_mtl(vdev); 63 64 if (ivpu_device_id(vdev) == PCI_DEVICE_ID_LNL && 65 ivpu_revision(vdev) < IVPU_HW_IP_REV_LNL_B0) 66 vdev->wa.disable_clock_relinquish = true; 67 68 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) 69 vdev->wa.wp0_during_power_up = true; 70 71 IVPU_PRINT_WA(punit_disabled); 72 IVPU_PRINT_WA(clear_runtime_mem); 73 IVPU_PRINT_WA(interrupt_clear_with_0); 74 IVPU_PRINT_WA(disable_clock_relinquish); 75 IVPU_PRINT_WA(wp0_during_power_up); 76 } 77 78 static void timeouts_init(struct ivpu_device *vdev) 79 { 80 if (ivpu_test_mode & IVPU_TEST_MODE_DISABLE_TIMEOUTS) { 81 vdev->timeout.boot = -1; 82 vdev->timeout.jsm = -1; 83 vdev->timeout.tdr = -1; 84 vdev->timeout.autosuspend = -1; 85 vdev->timeout.d0i3_entry_msg = -1; 86 } else if (ivpu_is_fpga(vdev)) { 87 vdev->timeout.boot = 100000; 88 vdev->timeout.jsm = 50000; 89 vdev->timeout.tdr = 2000000; 90 vdev->timeout.autosuspend = -1; 91 vdev->timeout.d0i3_entry_msg = 500; 92 } else if (ivpu_is_simics(vdev)) { 93 vdev->timeout.boot = 50; 94 vdev->timeout.jsm = 500; 95 vdev->timeout.tdr = 10000; 96 vdev->timeout.autosuspend = -1; 97 vdev->timeout.d0i3_entry_msg = 100; 98 } else { 99 vdev->timeout.boot = 1000; 100 vdev->timeout.jsm = 500; 101 vdev->timeout.tdr = 2000; 102 vdev->timeout.autosuspend = 10; 103 vdev->timeout.d0i3_entry_msg = 5; 104 } 105 } 106 107 static void memory_ranges_init(struct ivpu_device *vdev) 108 { 109 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { 110 ivpu_hw_range_init(&vdev->hw->ranges.global, 0x80000000, SZ_512M); 111 ivpu_hw_range_init(&vdev->hw->ranges.user, 0xc0000000, 255 * SZ_1M); 112 ivpu_hw_range_init(&vdev->hw->ranges.shave, 0x180000000, SZ_2G); 113 ivpu_hw_range_init(&vdev->hw->ranges.dma, 0x200000000, SZ_8G); 114 } else { 115 ivpu_hw_range_init(&vdev->hw->ranges.global, 0x80000000, SZ_512M); 116 ivpu_hw_range_init(&vdev->hw->ranges.user, 0x80000000, SZ_256M); 117 ivpu_hw_range_init(&vdev->hw->ranges.shave, 0x80000000 + SZ_256M, SZ_2G - SZ_256M); 118 ivpu_hw_range_init(&vdev->hw->ranges.dma, 0x200000000, SZ_8G); 119 } 120 } 121 122 static int wp_enable(struct ivpu_device *vdev) 123 { 124 return ivpu_hw_btrs_wp_drive(vdev, true); 125 } 126 127 static int wp_disable(struct ivpu_device *vdev) 128 { 129 return ivpu_hw_btrs_wp_drive(vdev, false); 130 } 131 132 int ivpu_hw_power_up(struct ivpu_device *vdev) 133 { 134 int ret; 135 136 if (IVPU_WA(wp0_during_power_up)) { 137 /* WP requests may fail when powering down, so issue WP 0 here */ 138 ret = wp_disable(vdev); 139 if (ret) 140 ivpu_warn(vdev, "Failed to disable workpoint: %d\n", ret); 141 } 142 143 ret = ivpu_hw_btrs_d0i3_disable(vdev); 144 if (ret) 145 ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret); 146 147 ret = wp_enable(vdev); 148 if (ret) { 149 ivpu_err(vdev, "Failed to enable workpoint: %d\n", ret); 150 return ret; 151 } 152 153 if (ivpu_hw_btrs_gen(vdev) >= IVPU_HW_BTRS_LNL) { 154 if (IVPU_WA(disable_clock_relinquish)) 155 ivpu_hw_btrs_clock_relinquish_disable_lnl(vdev); 156 ivpu_hw_btrs_profiling_freq_reg_set_lnl(vdev); 157 ivpu_hw_btrs_ats_print_lnl(vdev); 158 } 159 160 ret = ivpu_hw_ip_host_ss_configure(vdev); 161 if (ret) { 162 ivpu_err(vdev, "Failed to configure host SS: %d\n", ret); 163 return ret; 164 } 165 166 ivpu_hw_ip_idle_gen_disable(vdev); 167 168 ret = ivpu_hw_btrs_wait_for_clock_res_own_ack(vdev); 169 if (ret) { 170 ivpu_err(vdev, "Timed out waiting for clock resource own ACK\n"); 171 return ret; 172 } 173 174 ret = ivpu_hw_ip_pwr_domain_enable(vdev); 175 if (ret) { 176 ivpu_err(vdev, "Failed to enable power domain: %d\n", ret); 177 return ret; 178 } 179 180 ret = ivpu_hw_ip_host_ss_axi_enable(vdev); 181 if (ret) { 182 ivpu_err(vdev, "Failed to enable AXI: %d\n", ret); 183 return ret; 184 } 185 186 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_LNL) 187 ivpu_hw_btrs_set_port_arbitration_weights_lnl(vdev); 188 189 ret = ivpu_hw_ip_top_noc_enable(vdev); 190 if (ret) 191 ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret); 192 193 return ret; 194 } 195 196 static void save_d0i3_entry_timestamp(struct ivpu_device *vdev) 197 { 198 vdev->hw->d0i3_entry_host_ts = ktime_get_boottime(); 199 vdev->hw->d0i3_entry_vpu_ts = ivpu_hw_ip_read_perf_timer_counter(vdev); 200 } 201 202 int ivpu_hw_reset(struct ivpu_device *vdev) 203 { 204 int ret = 0; 205 206 if (ivpu_hw_btrs_ip_reset(vdev)) { 207 ivpu_err(vdev, "Failed to reset NPU IP\n"); 208 ret = -EIO; 209 } 210 211 if (wp_disable(vdev)) { 212 ivpu_err(vdev, "Failed to disable workpoint\n"); 213 ret = -EIO; 214 } 215 216 return ret; 217 } 218 219 int ivpu_hw_power_down(struct ivpu_device *vdev) 220 { 221 int ret = 0; 222 223 save_d0i3_entry_timestamp(vdev); 224 225 if (!ivpu_hw_is_idle(vdev)) 226 ivpu_warn(vdev, "NPU not idle during power down\n"); 227 228 if (ivpu_hw_reset(vdev)) { 229 ivpu_err(vdev, "Failed to reset NPU\n"); 230 ret = -EIO; 231 } 232 233 if (ivpu_hw_btrs_d0i3_enable(vdev)) { 234 ivpu_err(vdev, "Failed to enter D0I3\n"); 235 ret = -EIO; 236 } 237 238 return ret; 239 } 240 241 int ivpu_hw_init(struct ivpu_device *vdev) 242 { 243 ivpu_hw_btrs_info_init(vdev); 244 ivpu_hw_btrs_freq_ratios_init(vdev); 245 memory_ranges_init(vdev); 246 platform_init(vdev); 247 wa_init(vdev); 248 timeouts_init(vdev); 249 250 return 0; 251 } 252 253 int ivpu_hw_boot_fw(struct ivpu_device *vdev) 254 { 255 int ret; 256 257 ivpu_hw_ip_snoop_disable(vdev); 258 ivpu_hw_ip_tbu_mmu_enable(vdev); 259 ret = ivpu_hw_ip_soc_cpu_boot(vdev); 260 if (ret) 261 ivpu_err(vdev, "Failed to boot SOC CPU: %d\n", ret); 262 263 return ret; 264 } 265 266 void ivpu_hw_profiling_freq_drive(struct ivpu_device *vdev, bool enable) 267 { 268 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { 269 vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT; 270 return; 271 } 272 273 if (enable) 274 vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_HIGH; 275 else 276 vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT; 277 } 278 279 void ivpu_irq_handlers_init(struct ivpu_device *vdev) 280 { 281 INIT_KFIFO(vdev->hw->irq.fifo); 282 283 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) 284 vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_37xx; 285 else 286 vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_40xx; 287 288 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) 289 vdev->hw->irq.btrs_irq_handler = ivpu_hw_btrs_irq_handler_mtl; 290 else 291 vdev->hw->irq.btrs_irq_handler = ivpu_hw_btrs_irq_handler_lnl; 292 } 293 294 void ivpu_hw_irq_enable(struct ivpu_device *vdev) 295 { 296 kfifo_reset(&vdev->hw->irq.fifo); 297 ivpu_hw_ip_irq_enable(vdev); 298 ivpu_hw_btrs_irq_enable(vdev); 299 } 300 301 void ivpu_hw_irq_disable(struct ivpu_device *vdev) 302 { 303 ivpu_hw_btrs_irq_disable(vdev); 304 ivpu_hw_ip_irq_disable(vdev); 305 } 306 307 irqreturn_t ivpu_hw_irq_handler(int irq, void *ptr) 308 { 309 struct ivpu_device *vdev = ptr; 310 bool ip_handled, btrs_handled; 311 312 ivpu_hw_btrs_global_int_disable(vdev); 313 314 btrs_handled = ivpu_hw_btrs_irq_handler(vdev, irq); 315 if (!ivpu_hw_is_idle((vdev)) || !btrs_handled) 316 ip_handled = ivpu_hw_ip_irq_handler(vdev, irq); 317 else 318 ip_handled = false; 319 320 /* Re-enable global interrupts to re-trigger MSI for pending interrupts */ 321 ivpu_hw_btrs_global_int_enable(vdev); 322 323 if (!kfifo_is_empty(&vdev->hw->irq.fifo)) 324 return IRQ_WAKE_THREAD; 325 if (ip_handled || btrs_handled) 326 return IRQ_HANDLED; 327 return IRQ_NONE; 328 } 329