1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020-2023 Intel Corporation 4 */ 5 6 #include <linux/firmware.h> 7 #include <linux/highmem.h> 8 #include <linux/moduleparam.h> 9 #include <linux/pci.h> 10 11 #include "vpu_boot_api.h" 12 #include "ivpu_drv.h" 13 #include "ivpu_fw.h" 14 #include "ivpu_fw_log.h" 15 #include "ivpu_gem.h" 16 #include "ivpu_hw.h" 17 #include "ivpu_ipc.h" 18 #include "ivpu_pm.h" 19 20 #define FW_GLOBAL_MEM_START (2ull * SZ_1G) 21 #define FW_GLOBAL_MEM_END (3ull * SZ_1G) 22 #define FW_SHARED_MEM_SIZE SZ_256M /* Must be aligned to FW_SHARED_MEM_ALIGNMENT */ 23 #define FW_SHARED_MEM_ALIGNMENT SZ_128K /* VPU MTRR limitation */ 24 #define FW_RUNTIME_MAX_SIZE SZ_512M 25 #define FW_SHAVE_NN_MAX_SIZE SZ_2M 26 #define FW_RUNTIME_MIN_ADDR (FW_GLOBAL_MEM_START) 27 #define FW_RUNTIME_MAX_ADDR (FW_GLOBAL_MEM_END - FW_SHARED_MEM_SIZE) 28 #define FW_VERSION_HEADER_SIZE SZ_4K 29 #define FW_FILE_IMAGE_OFFSET (VPU_FW_HEADER_SIZE + FW_VERSION_HEADER_SIZE) 30 31 #define WATCHDOG_MSS_REDIRECT 32 32 #define WATCHDOG_NCE_REDIRECT 33 33 34 #define ADDR_TO_L2_CACHE_CFG(addr) ((addr) >> 31) 35 36 /* Check if FW API is compatible with the driver */ 37 #define IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, name, min_major) \ 38 ivpu_fw_check_api(vdev, fw_hdr, #name, \ 39 VPU_##name##_API_VER_INDEX, \ 40 VPU_##name##_API_VER_MAJOR, \ 41 VPU_##name##_API_VER_MINOR, min_major) 42 43 /* Check if API version is lower that the given version */ 44 #define IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, name, major, minor) \ 45 ivpu_fw_check_api_ver_lt(vdev, fw_hdr, #name, VPU_##name##_API_VER_INDEX, major, minor) 46 47 #define IVPU_FOCUS_PRESENT_TIMER_MS 1000 48 49 static char *ivpu_firmware; 50 module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644); 51 MODULE_PARM_DESC(firmware, "NPU firmware binary in /lib/firmware/.."); 52 53 static struct { 54 int gen; 55 const char *name; 56 } fw_names[] = { 57 { IVPU_HW_IP_37XX, "vpu_37xx.bin" }, 58 { IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v0.0.bin" }, 59 { IVPU_HW_IP_40XX, "vpu_40xx.bin" }, 60 { IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v0.0.bin" }, 61 }; 62 63 static int ivpu_fw_request(struct ivpu_device *vdev) 64 { 65 int ret = -ENOENT; 66 int i; 67 68 if (ivpu_firmware) { 69 ret = request_firmware(&vdev->fw->file, ivpu_firmware, vdev->drm.dev); 70 if (!ret) 71 vdev->fw->name = ivpu_firmware; 72 return ret; 73 } 74 75 for (i = 0; i < ARRAY_SIZE(fw_names); i++) { 76 if (fw_names[i].gen != ivpu_hw_ip_gen(vdev)) 77 continue; 78 79 ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i].name, vdev->drm.dev); 80 if (!ret) { 81 vdev->fw->name = fw_names[i].name; 82 return 0; 83 } 84 } 85 86 ivpu_err(vdev, "Failed to request firmware: %d\n", ret); 87 return ret; 88 } 89 90 static int 91 ivpu_fw_check_api(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr, 92 const char *str, int index, u16 expected_major, u16 expected_minor, 93 u16 min_major) 94 { 95 u16 major = (u16)(fw_hdr->api_version[index] >> 16); 96 u16 minor = (u16)(fw_hdr->api_version[index]); 97 98 if (major < min_major) { 99 ivpu_err(vdev, "Incompatible FW %s API version: %d.%d, required %d.0 or later\n", 100 str, major, minor, min_major); 101 return -EINVAL; 102 } 103 if (major != expected_major) { 104 ivpu_warn(vdev, "Major FW %s API version different: %d.%d (expected %d.%d)\n", 105 str, major, minor, expected_major, expected_minor); 106 } 107 ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n", 108 str, major, minor, expected_major, expected_minor); 109 110 return 0; 111 } 112 113 static bool 114 ivpu_fw_check_api_ver_lt(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr, 115 const char *str, int index, u16 major, u16 minor) 116 { 117 u16 fw_major = (u16)(fw_hdr->api_version[index] >> 16); 118 u16 fw_minor = (u16)(fw_hdr->api_version[index]); 119 120 if (fw_major < major || (fw_major == major && fw_minor < minor)) 121 return true; 122 123 return false; 124 } 125 126 static int ivpu_fw_parse(struct ivpu_device *vdev) 127 { 128 struct ivpu_fw_info *fw = vdev->fw; 129 const struct vpu_firmware_header *fw_hdr = (const void *)fw->file->data; 130 u64 runtime_addr, image_load_addr, runtime_size, image_size; 131 132 if (fw->file->size <= FW_FILE_IMAGE_OFFSET) { 133 ivpu_err(vdev, "Firmware file is too small: %zu\n", fw->file->size); 134 return -EINVAL; 135 } 136 137 if (fw_hdr->header_version != VPU_FW_HEADER_VERSION) { 138 ivpu_err(vdev, "Invalid firmware header version: %u\n", fw_hdr->header_version); 139 return -EINVAL; 140 } 141 142 runtime_addr = fw_hdr->boot_params_load_address; 143 runtime_size = fw_hdr->runtime_size; 144 image_load_addr = fw_hdr->image_load_address; 145 image_size = fw_hdr->image_size; 146 147 if (runtime_addr < FW_RUNTIME_MIN_ADDR || runtime_addr > FW_RUNTIME_MAX_ADDR) { 148 ivpu_err(vdev, "Invalid firmware runtime address: 0x%llx\n", runtime_addr); 149 return -EINVAL; 150 } 151 152 if (runtime_size < fw->file->size || runtime_size > FW_RUNTIME_MAX_SIZE) { 153 ivpu_err(vdev, "Invalid firmware runtime size: %llu\n", runtime_size); 154 return -EINVAL; 155 } 156 157 if (FW_FILE_IMAGE_OFFSET + image_size > fw->file->size) { 158 ivpu_err(vdev, "Invalid image size: %llu\n", image_size); 159 return -EINVAL; 160 } 161 162 if (image_load_addr < runtime_addr || 163 image_load_addr + image_size > runtime_addr + runtime_size) { 164 ivpu_err(vdev, "Invalid firmware load address size: 0x%llx and size %llu\n", 165 image_load_addr, image_size); 166 return -EINVAL; 167 } 168 169 if (fw_hdr->shave_nn_fw_size > FW_SHAVE_NN_MAX_SIZE) { 170 ivpu_err(vdev, "SHAVE NN firmware is too big: %u\n", fw_hdr->shave_nn_fw_size); 171 return -EINVAL; 172 } 173 174 if (fw_hdr->entry_point < image_load_addr || 175 fw_hdr->entry_point >= image_load_addr + image_size) { 176 ivpu_err(vdev, "Invalid entry point: 0x%llx\n", fw_hdr->entry_point); 177 return -EINVAL; 178 } 179 ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n", 180 fw_hdr->header_version, fw_hdr->image_format); 181 182 ivpu_info(vdev, "Firmware: %s, version: %s", fw->name, 183 (const char *)fw_hdr + VPU_FW_HEADER_SIZE); 184 185 if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, BOOT, 3)) 186 return -EINVAL; 187 if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, JSM, 3)) 188 return -EINVAL; 189 190 fw->runtime_addr = runtime_addr; 191 fw->runtime_size = runtime_size; 192 fw->image_load_offset = image_load_addr - runtime_addr; 193 fw->image_size = image_size; 194 fw->shave_nn_size = PAGE_ALIGN(fw_hdr->shave_nn_fw_size); 195 196 fw->cold_boot_entry_point = fw_hdr->entry_point; 197 fw->entry_point = fw->cold_boot_entry_point; 198 199 fw->trace_level = min_t(u32, ivpu_log_level, IVPU_FW_LOG_FATAL); 200 fw->trace_destination_mask = VPU_TRACE_DESTINATION_VERBOSE_TRACING; 201 fw->trace_hw_component_mask = -1; 202 203 fw->dvfs_mode = 0; 204 205 fw->primary_preempt_buf_size = fw_hdr->preemption_buffer_1_size; 206 fw->secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_size; 207 208 ivpu_dbg(vdev, FW_BOOT, "Size: file %lu image %u runtime %u shavenn %u\n", 209 fw->file->size, fw->image_size, fw->runtime_size, fw->shave_nn_size); 210 ivpu_dbg(vdev, FW_BOOT, "Address: runtime 0x%llx, load 0x%llx, entry point 0x%llx\n", 211 fw->runtime_addr, image_load_addr, fw->entry_point); 212 213 return 0; 214 } 215 216 static void ivpu_fw_release(struct ivpu_device *vdev) 217 { 218 release_firmware(vdev->fw->file); 219 } 220 221 /* Initialize workarounds that depend on FW version */ 222 static void 223 ivpu_fw_init_wa(struct ivpu_device *vdev) 224 { 225 const struct vpu_firmware_header *fw_hdr = (const void *)vdev->fw->file->data; 226 227 if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, BOOT, 3, 17) || 228 (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_DISABLE)) 229 vdev->wa.disable_d0i3_msg = true; 230 231 /* Force enable the feature for testing purposes */ 232 if (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_ENABLE) 233 vdev->wa.disable_d0i3_msg = false; 234 235 IVPU_PRINT_WA(disable_d0i3_msg); 236 } 237 238 static int ivpu_fw_update_global_range(struct ivpu_device *vdev) 239 { 240 struct ivpu_fw_info *fw = vdev->fw; 241 u64 start = ALIGN(fw->runtime_addr + fw->runtime_size, FW_SHARED_MEM_ALIGNMENT); 242 u64 size = FW_SHARED_MEM_SIZE; 243 244 if (start + size > FW_GLOBAL_MEM_END) { 245 ivpu_err(vdev, "No space for shared region, start %lld, size %lld\n", start, size); 246 return -EINVAL; 247 } 248 249 ivpu_hw_range_init(&vdev->hw->ranges.global, start, size); 250 return 0; 251 } 252 253 static int ivpu_fw_mem_init(struct ivpu_device *vdev) 254 { 255 struct ivpu_fw_info *fw = vdev->fw; 256 struct ivpu_addr_range fw_range; 257 int log_verb_size; 258 int ret; 259 260 ret = ivpu_fw_update_global_range(vdev); 261 if (ret) 262 return ret; 263 264 fw_range.start = fw->runtime_addr; 265 fw_range.end = fw->runtime_addr + fw->runtime_size; 266 fw->mem = ivpu_bo_create(vdev, &vdev->gctx, &fw_range, fw->runtime_size, 267 DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE); 268 if (!fw->mem) { 269 ivpu_err(vdev, "Failed to create firmware runtime memory buffer\n"); 270 return -ENOMEM; 271 } 272 273 fw->mem_log_crit = ivpu_bo_create_global(vdev, IVPU_FW_CRITICAL_BUFFER_SIZE, 274 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE); 275 if (!fw->mem_log_crit) { 276 ivpu_err(vdev, "Failed to create critical log buffer\n"); 277 ret = -ENOMEM; 278 goto err_free_fw_mem; 279 } 280 281 if (ivpu_log_level <= IVPU_FW_LOG_INFO) 282 log_verb_size = IVPU_FW_VERBOSE_BUFFER_LARGE_SIZE; 283 else 284 log_verb_size = IVPU_FW_VERBOSE_BUFFER_SMALL_SIZE; 285 286 fw->mem_log_verb = ivpu_bo_create_global(vdev, log_verb_size, 287 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE); 288 if (!fw->mem_log_verb) { 289 ivpu_err(vdev, "Failed to create verbose log buffer\n"); 290 ret = -ENOMEM; 291 goto err_free_log_crit; 292 } 293 294 if (fw->shave_nn_size) { 295 fw->mem_shave_nn = ivpu_bo_create(vdev, &vdev->gctx, &vdev->hw->ranges.shave, 296 fw->shave_nn_size, DRM_IVPU_BO_WC); 297 if (!fw->mem_shave_nn) { 298 ivpu_err(vdev, "Failed to create shavenn buffer\n"); 299 ret = -ENOMEM; 300 goto err_free_log_verb; 301 } 302 } 303 304 return 0; 305 306 err_free_log_verb: 307 ivpu_bo_free(fw->mem_log_verb); 308 err_free_log_crit: 309 ivpu_bo_free(fw->mem_log_crit); 310 err_free_fw_mem: 311 ivpu_bo_free(fw->mem); 312 return ret; 313 } 314 315 static void ivpu_fw_mem_fini(struct ivpu_device *vdev) 316 { 317 struct ivpu_fw_info *fw = vdev->fw; 318 319 if (fw->mem_shave_nn) { 320 ivpu_bo_free(fw->mem_shave_nn); 321 fw->mem_shave_nn = NULL; 322 } 323 324 ivpu_bo_free(fw->mem_log_verb); 325 ivpu_bo_free(fw->mem_log_crit); 326 ivpu_bo_free(fw->mem); 327 328 fw->mem_log_verb = NULL; 329 fw->mem_log_crit = NULL; 330 fw->mem = NULL; 331 } 332 333 int ivpu_fw_init(struct ivpu_device *vdev) 334 { 335 int ret; 336 337 ret = ivpu_fw_request(vdev); 338 if (ret) 339 return ret; 340 341 ret = ivpu_fw_parse(vdev); 342 if (ret) 343 goto err_fw_release; 344 345 ivpu_fw_init_wa(vdev); 346 347 ret = ivpu_fw_mem_init(vdev); 348 if (ret) 349 goto err_fw_release; 350 351 ivpu_fw_load(vdev); 352 353 return 0; 354 355 err_fw_release: 356 ivpu_fw_release(vdev); 357 return ret; 358 } 359 360 void ivpu_fw_fini(struct ivpu_device *vdev) 361 { 362 ivpu_fw_mem_fini(vdev); 363 ivpu_fw_release(vdev); 364 } 365 366 void ivpu_fw_load(struct ivpu_device *vdev) 367 { 368 struct ivpu_fw_info *fw = vdev->fw; 369 u64 image_end_offset = fw->image_load_offset + fw->image_size; 370 371 memset(ivpu_bo_vaddr(fw->mem), 0, fw->image_load_offset); 372 memcpy(ivpu_bo_vaddr(fw->mem) + fw->image_load_offset, 373 fw->file->data + FW_FILE_IMAGE_OFFSET, fw->image_size); 374 375 if (IVPU_WA(clear_runtime_mem)) { 376 u8 *start = ivpu_bo_vaddr(fw->mem) + image_end_offset; 377 u64 size = ivpu_bo_size(fw->mem) - image_end_offset; 378 379 memset(start, 0, size); 380 } 381 382 wmb(); /* Flush WC buffers after writing fw->mem */ 383 } 384 385 static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 386 { 387 ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n", 388 boot_params->magic); 389 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n", 390 boot_params->vpu_id); 391 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n", 392 boot_params->vpu_count); 393 ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n", 394 boot_params->frequency); 395 ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n", 396 boot_params->perf_clk_frequency); 397 398 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_start = 0x%llx\n", 399 boot_params->ipc_header_area_start); 400 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_size = 0x%x\n", 401 boot_params->ipc_header_area_size); 402 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_base = 0x%llx\n", 403 boot_params->shared_region_base); 404 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_size = 0x%x\n", 405 boot_params->shared_region_size); 406 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_start = 0x%llx\n", 407 boot_params->ipc_payload_area_start); 408 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_size = 0x%x\n", 409 boot_params->ipc_payload_area_size); 410 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_base = 0x%llx\n", 411 boot_params->global_aliased_pio_base); 412 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_size = 0x%x\n", 413 boot_params->global_aliased_pio_size); 414 415 ivpu_dbg(vdev, FW_BOOT, "boot_params.autoconfig = 0x%x\n", 416 boot_params->autoconfig); 417 418 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 0x%x\n", 419 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use); 420 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 0x%x\n", 421 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg); 422 423 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_base = 0x%llx\n", 424 boot_params->global_memory_allocator_base); 425 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_size = 0x%x\n", 426 boot_params->global_memory_allocator_size); 427 428 ivpu_dbg(vdev, FW_BOOT, "boot_params.shave_nn_fw_base = 0x%llx\n", 429 boot_params->shave_nn_fw_base); 430 431 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_mss = 0x%x\n", 432 boot_params->watchdog_irq_mss); 433 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_nce = 0x%x\n", 434 boot_params->watchdog_irq_nce); 435 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_to_vpu_irq = 0x%x\n", 436 boot_params->host_to_vpu_irq); 437 ivpu_dbg(vdev, FW_BOOT, "boot_params.job_done_irq = 0x%x\n", 438 boot_params->job_done_irq); 439 440 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_version_id = 0x%x\n", 441 boot_params->host_version_id); 442 ivpu_dbg(vdev, FW_BOOT, "boot_params.si_stepping = 0x%x\n", 443 boot_params->si_stepping); 444 ivpu_dbg(vdev, FW_BOOT, "boot_params.device_id = 0x%llx\n", 445 boot_params->device_id); 446 ivpu_dbg(vdev, FW_BOOT, "boot_params.feature_exclusion = 0x%llx\n", 447 boot_params->feature_exclusion); 448 ivpu_dbg(vdev, FW_BOOT, "boot_params.sku = 0x%llx\n", 449 boot_params->sku); 450 ivpu_dbg(vdev, FW_BOOT, "boot_params.min_freq_pll_ratio = 0x%x\n", 451 boot_params->min_freq_pll_ratio); 452 ivpu_dbg(vdev, FW_BOOT, "boot_params.pn_freq_pll_ratio = 0x%x\n", 453 boot_params->pn_freq_pll_ratio); 454 ivpu_dbg(vdev, FW_BOOT, "boot_params.max_freq_pll_ratio = 0x%x\n", 455 boot_params->max_freq_pll_ratio); 456 ivpu_dbg(vdev, FW_BOOT, "boot_params.default_trace_level = 0x%x\n", 457 boot_params->default_trace_level); 458 ivpu_dbg(vdev, FW_BOOT, "boot_params.tracing_buff_message_format_mask = 0x%llx\n", 459 boot_params->tracing_buff_message_format_mask); 460 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_destination_mask = 0x%x\n", 461 boot_params->trace_destination_mask); 462 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_hw_component_mask = 0x%llx\n", 463 boot_params->trace_hw_component_mask); 464 ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n", 465 boot_params->boot_type); 466 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_base = 0x%llx\n", 467 boot_params->punit_telemetry_sram_base); 468 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_size = 0x%llx\n", 469 boot_params->punit_telemetry_sram_size); 470 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n", 471 boot_params->vpu_telemetry_enable); 472 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_scheduling_mode = 0x%x\n", 473 boot_params->vpu_scheduling_mode); 474 ivpu_dbg(vdev, FW_BOOT, "boot_params.dvfs_mode = %u\n", 475 boot_params->dvfs_mode); 476 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_delayed_entry = %d\n", 477 boot_params->d0i3_delayed_entry); 478 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n", 479 boot_params->d0i3_residency_time_us); 480 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n", 481 boot_params->d0i3_entry_vpu_ts); 482 ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n", 483 boot_params->system_time_us); 484 } 485 486 void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 487 { 488 struct ivpu_bo *ipc_mem_rx = vdev->ipc->mem_rx; 489 490 /* In case of warm boot only update variable params */ 491 if (!ivpu_fw_is_cold_boot(vdev)) { 492 boot_params->d0i3_residency_time_us = 493 ktime_us_delta(ktime_get_boottime(), vdev->hw->d0i3_entry_host_ts); 494 boot_params->d0i3_entry_vpu_ts = vdev->hw->d0i3_entry_vpu_ts; 495 boot_params->system_time_us = ktime_to_us(ktime_get_real()); 496 497 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n", 498 boot_params->d0i3_residency_time_us); 499 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n", 500 boot_params->d0i3_entry_vpu_ts); 501 ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n", 502 boot_params->system_time_us); 503 504 boot_params->save_restore_ret_address = 0; 505 vdev->pm->is_warmboot = true; 506 wmb(); /* Flush WC buffers after writing save_restore_ret_address */ 507 return; 508 } 509 510 vdev->pm->is_warmboot = false; 511 512 boot_params->magic = VPU_BOOT_PARAMS_MAGIC; 513 boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number; 514 boot_params->frequency = ivpu_hw_pll_freq_get(vdev); 515 516 /* 517 * This param is a debug firmware feature. It switches default clock 518 * to higher resolution one for fine-grained and more accurate firmware 519 * task profiling. 520 */ 521 boot_params->perf_clk_frequency = ivpu_hw_profiling_freq_get(vdev); 522 523 /* 524 * Uncached region of VPU address space, covers IPC buffers, job queues 525 * and log buffers, programmable to L2$ Uncached by VPU MTRR 526 */ 527 boot_params->shared_region_base = vdev->hw->ranges.global.start; 528 boot_params->shared_region_size = vdev->hw->ranges.global.end - 529 vdev->hw->ranges.global.start; 530 531 boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr; 532 boot_params->ipc_header_area_size = ivpu_bo_size(ipc_mem_rx) / 2; 533 534 boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ivpu_bo_size(ipc_mem_rx) / 2; 535 boot_params->ipc_payload_area_size = ivpu_bo_size(ipc_mem_rx) / 2; 536 537 boot_params->global_aliased_pio_base = vdev->hw->ranges.user.start; 538 boot_params->global_aliased_pio_size = ivpu_hw_range_size(&vdev->hw->ranges.user); 539 540 /* Allow configuration for L2C_PAGE_TABLE with boot param value */ 541 boot_params->autoconfig = 1; 542 543 /* Enable L2 cache for first 2GB of high memory */ 544 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1; 545 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 546 ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.shave.start); 547 548 if (vdev->fw->mem_shave_nn) 549 boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr; 550 551 boot_params->watchdog_irq_mss = WATCHDOG_MSS_REDIRECT; 552 boot_params->watchdog_irq_nce = WATCHDOG_NCE_REDIRECT; 553 boot_params->si_stepping = ivpu_revision(vdev); 554 boot_params->device_id = ivpu_device_id(vdev); 555 boot_params->feature_exclusion = vdev->hw->tile_fuse; 556 boot_params->sku = vdev->hw->sku; 557 558 boot_params->min_freq_pll_ratio = vdev->hw->pll.min_ratio; 559 boot_params->pn_freq_pll_ratio = vdev->hw->pll.pn_ratio; 560 boot_params->max_freq_pll_ratio = vdev->hw->pll.max_ratio; 561 562 boot_params->default_trace_level = vdev->fw->trace_level; 563 boot_params->tracing_buff_message_format_mask = BIT(VPU_TRACING_FORMAT_STRING); 564 boot_params->trace_destination_mask = vdev->fw->trace_destination_mask; 565 boot_params->trace_hw_component_mask = vdev->fw->trace_hw_component_mask; 566 boot_params->crit_tracing_buff_addr = vdev->fw->mem_log_crit->vpu_addr; 567 boot_params->crit_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_crit); 568 boot_params->verbose_tracing_buff_addr = vdev->fw->mem_log_verb->vpu_addr; 569 boot_params->verbose_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_verb); 570 571 boot_params->punit_telemetry_sram_base = ivpu_hw_telemetry_offset_get(vdev); 572 boot_params->punit_telemetry_sram_size = ivpu_hw_telemetry_size_get(vdev); 573 boot_params->vpu_telemetry_enable = ivpu_hw_telemetry_enable_get(vdev); 574 boot_params->vpu_scheduling_mode = vdev->hw->sched_mode; 575 if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) 576 boot_params->vpu_focus_present_timer_ms = IVPU_FOCUS_PRESENT_TIMER_MS; 577 boot_params->dvfs_mode = vdev->fw->dvfs_mode; 578 if (!IVPU_WA(disable_d0i3_msg)) 579 boot_params->d0i3_delayed_entry = 1; 580 boot_params->d0i3_residency_time_us = 0; 581 boot_params->d0i3_entry_vpu_ts = 0; 582 583 boot_params->system_time_us = ktime_to_us(ktime_get_real()); 584 wmb(); /* Flush WC buffers after writing bootparams */ 585 586 ivpu_fw_boot_params_print(vdev, boot_params); 587 } 588