1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020-2024 Intel Corporation 4 */ 5 6 #include <linux/firmware.h> 7 #include <linux/highmem.h> 8 #include <linux/moduleparam.h> 9 #include <linux/pci.h> 10 11 #include "vpu_boot_api.h" 12 #include "ivpu_drv.h" 13 #include "ivpu_fw.h" 14 #include "ivpu_fw_log.h" 15 #include "ivpu_gem.h" 16 #include "ivpu_hw.h" 17 #include "ivpu_ipc.h" 18 #include "ivpu_pm.h" 19 20 #define FW_GLOBAL_MEM_START (2ull * SZ_1G) 21 #define FW_GLOBAL_MEM_END (3ull * SZ_1G) 22 #define FW_SHARED_MEM_SIZE SZ_256M /* Must be aligned to FW_SHARED_MEM_ALIGNMENT */ 23 #define FW_SHARED_MEM_ALIGNMENT SZ_128K /* VPU MTRR limitation */ 24 #define FW_RUNTIME_MAX_SIZE SZ_512M 25 #define FW_SHAVE_NN_MAX_SIZE SZ_2M 26 #define FW_RUNTIME_MIN_ADDR (FW_GLOBAL_MEM_START) 27 #define FW_RUNTIME_MAX_ADDR (FW_GLOBAL_MEM_END - FW_SHARED_MEM_SIZE) 28 #define FW_VERSION_HEADER_SIZE SZ_4K 29 #define FW_FILE_IMAGE_OFFSET (VPU_FW_HEADER_SIZE + FW_VERSION_HEADER_SIZE) 30 31 #define WATCHDOG_MSS_REDIRECT 32 32 #define WATCHDOG_NCE_REDIRECT 33 33 34 #define ADDR_TO_L2_CACHE_CFG(addr) ((addr) >> 31) 35 36 /* Check if FW API is compatible with the driver */ 37 #define IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, name, min_major) \ 38 ivpu_fw_check_api(vdev, fw_hdr, #name, \ 39 VPU_##name##_API_VER_INDEX, \ 40 VPU_##name##_API_VER_MAJOR, \ 41 VPU_##name##_API_VER_MINOR, min_major) 42 43 /* Check if API version is lower that the given version */ 44 #define IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, name, major, minor) \ 45 ivpu_fw_check_api_ver_lt(vdev, fw_hdr, #name, VPU_##name##_API_VER_INDEX, major, minor) 46 47 #define IVPU_FOCUS_PRESENT_TIMER_MS 1000 48 49 static char *ivpu_firmware; 50 module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644); 51 MODULE_PARM_DESC(firmware, "NPU firmware binary in /lib/firmware/.."); 52 53 static struct { 54 int gen; 55 const char *name; 56 } fw_names[] = { 57 { IVPU_HW_IP_37XX, "vpu_37xx.bin" }, 58 { IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v0.0.bin" }, 59 { IVPU_HW_IP_40XX, "vpu_40xx.bin" }, 60 { IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v0.0.bin" }, 61 }; 62 63 static int ivpu_fw_request(struct ivpu_device *vdev) 64 { 65 int ret = -ENOENT; 66 int i; 67 68 if (ivpu_firmware) { 69 ret = request_firmware(&vdev->fw->file, ivpu_firmware, vdev->drm.dev); 70 if (!ret) 71 vdev->fw->name = ivpu_firmware; 72 return ret; 73 } 74 75 for (i = 0; i < ARRAY_SIZE(fw_names); i++) { 76 if (fw_names[i].gen != ivpu_hw_ip_gen(vdev)) 77 continue; 78 79 ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i].name, vdev->drm.dev); 80 if (!ret) { 81 vdev->fw->name = fw_names[i].name; 82 return 0; 83 } 84 } 85 86 ivpu_err(vdev, "Failed to request firmware: %d\n", ret); 87 return ret; 88 } 89 90 static int 91 ivpu_fw_check_api(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr, 92 const char *str, int index, u16 expected_major, u16 expected_minor, 93 u16 min_major) 94 { 95 u16 major = (u16)(fw_hdr->api_version[index] >> 16); 96 u16 minor = (u16)(fw_hdr->api_version[index]); 97 98 if (major < min_major) { 99 ivpu_err(vdev, "Incompatible FW %s API version: %d.%d, required %d.0 or later\n", 100 str, major, minor, min_major); 101 return -EINVAL; 102 } 103 if (major != expected_major) { 104 ivpu_warn(vdev, "Major FW %s API version different: %d.%d (expected %d.%d)\n", 105 str, major, minor, expected_major, expected_minor); 106 } 107 ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n", 108 str, major, minor, expected_major, expected_minor); 109 110 return 0; 111 } 112 113 static bool 114 ivpu_fw_check_api_ver_lt(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr, 115 const char *str, int index, u16 major, u16 minor) 116 { 117 u16 fw_major = (u16)(fw_hdr->api_version[index] >> 16); 118 u16 fw_minor = (u16)(fw_hdr->api_version[index]); 119 120 if (fw_major < major || (fw_major == major && fw_minor < minor)) 121 return true; 122 123 return false; 124 } 125 126 static bool is_within_range(u64 addr, size_t size, u64 range_start, size_t range_size) 127 { 128 if (addr < range_start || addr + size > range_start + range_size) 129 return false; 130 131 return true; 132 } 133 134 static int ivpu_fw_parse(struct ivpu_device *vdev) 135 { 136 struct ivpu_fw_info *fw = vdev->fw; 137 const struct vpu_firmware_header *fw_hdr = (const void *)fw->file->data; 138 u64 runtime_addr, image_load_addr, runtime_size, image_size; 139 140 if (fw->file->size <= FW_FILE_IMAGE_OFFSET) { 141 ivpu_err(vdev, "Firmware file is too small: %zu\n", fw->file->size); 142 return -EINVAL; 143 } 144 145 if (fw_hdr->header_version != VPU_FW_HEADER_VERSION) { 146 ivpu_err(vdev, "Invalid firmware header version: %u\n", fw_hdr->header_version); 147 return -EINVAL; 148 } 149 150 runtime_addr = fw_hdr->boot_params_load_address; 151 runtime_size = fw_hdr->runtime_size; 152 image_load_addr = fw_hdr->image_load_address; 153 image_size = fw_hdr->image_size; 154 155 if (runtime_addr < FW_RUNTIME_MIN_ADDR || runtime_addr > FW_RUNTIME_MAX_ADDR) { 156 ivpu_err(vdev, "Invalid firmware runtime address: 0x%llx\n", runtime_addr); 157 return -EINVAL; 158 } 159 160 if (runtime_size < fw->file->size || runtime_size > FW_RUNTIME_MAX_SIZE) { 161 ivpu_err(vdev, "Invalid firmware runtime size: %llu\n", runtime_size); 162 return -EINVAL; 163 } 164 165 if (FW_FILE_IMAGE_OFFSET + image_size > fw->file->size) { 166 ivpu_err(vdev, "Invalid image size: %llu\n", image_size); 167 return -EINVAL; 168 } 169 170 if (image_load_addr < runtime_addr || 171 image_load_addr + image_size > runtime_addr + runtime_size) { 172 ivpu_err(vdev, "Invalid firmware load address size: 0x%llx and size %llu\n", 173 image_load_addr, image_size); 174 return -EINVAL; 175 } 176 177 if (fw_hdr->shave_nn_fw_size > FW_SHAVE_NN_MAX_SIZE) { 178 ivpu_err(vdev, "SHAVE NN firmware is too big: %u\n", fw_hdr->shave_nn_fw_size); 179 return -EINVAL; 180 } 181 182 if (fw_hdr->entry_point < image_load_addr || 183 fw_hdr->entry_point >= image_load_addr + image_size) { 184 ivpu_err(vdev, "Invalid entry point: 0x%llx\n", fw_hdr->entry_point); 185 return -EINVAL; 186 } 187 ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n", 188 fw_hdr->header_version, fw_hdr->image_format); 189 190 ivpu_info(vdev, "Firmware: %s, version: %s", fw->name, 191 (const char *)fw_hdr + VPU_FW_HEADER_SIZE); 192 193 if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, BOOT, 3)) 194 return -EINVAL; 195 if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, JSM, 3)) 196 return -EINVAL; 197 198 fw->runtime_addr = runtime_addr; 199 fw->runtime_size = runtime_size; 200 fw->image_load_offset = image_load_addr - runtime_addr; 201 fw->image_size = image_size; 202 fw->shave_nn_size = PAGE_ALIGN(fw_hdr->shave_nn_fw_size); 203 204 fw->cold_boot_entry_point = fw_hdr->entry_point; 205 fw->entry_point = fw->cold_boot_entry_point; 206 207 fw->trace_level = min_t(u32, ivpu_log_level, IVPU_FW_LOG_FATAL); 208 fw->trace_destination_mask = VPU_TRACE_DESTINATION_VERBOSE_TRACING; 209 fw->trace_hw_component_mask = -1; 210 211 fw->dvfs_mode = 0; 212 213 fw->primary_preempt_buf_size = fw_hdr->preemption_buffer_1_size; 214 fw->secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_size; 215 216 if (fw_hdr->ro_section_start_address && !is_within_range(fw_hdr->ro_section_start_address, 217 fw_hdr->ro_section_size, 218 fw_hdr->image_load_address, 219 fw_hdr->image_size)) { 220 ivpu_err(vdev, "Invalid read-only section: start address 0x%llx, size %u\n", 221 fw_hdr->ro_section_start_address, fw_hdr->ro_section_size); 222 return -EINVAL; 223 } 224 225 fw->read_only_addr = fw_hdr->ro_section_start_address; 226 fw->read_only_size = fw_hdr->ro_section_size; 227 228 ivpu_dbg(vdev, FW_BOOT, "Size: file %lu image %u runtime %u shavenn %u\n", 229 fw->file->size, fw->image_size, fw->runtime_size, fw->shave_nn_size); 230 ivpu_dbg(vdev, FW_BOOT, "Address: runtime 0x%llx, load 0x%llx, entry point 0x%llx\n", 231 fw->runtime_addr, image_load_addr, fw->entry_point); 232 ivpu_dbg(vdev, FW_BOOT, "Read-only section: address 0x%llx, size %u\n", 233 fw->read_only_addr, fw->read_only_size); 234 235 return 0; 236 } 237 238 static void ivpu_fw_release(struct ivpu_device *vdev) 239 { 240 release_firmware(vdev->fw->file); 241 } 242 243 /* Initialize workarounds that depend on FW version */ 244 static void 245 ivpu_fw_init_wa(struct ivpu_device *vdev) 246 { 247 const struct vpu_firmware_header *fw_hdr = (const void *)vdev->fw->file->data; 248 249 if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, BOOT, 3, 17) || 250 (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_DISABLE)) 251 vdev->wa.disable_d0i3_msg = true; 252 253 /* Force enable the feature for testing purposes */ 254 if (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_ENABLE) 255 vdev->wa.disable_d0i3_msg = false; 256 257 IVPU_PRINT_WA(disable_d0i3_msg); 258 } 259 260 static int ivpu_fw_update_global_range(struct ivpu_device *vdev) 261 { 262 struct ivpu_fw_info *fw = vdev->fw; 263 u64 start = ALIGN(fw->runtime_addr + fw->runtime_size, FW_SHARED_MEM_ALIGNMENT); 264 u64 size = FW_SHARED_MEM_SIZE; 265 266 if (start + size > FW_GLOBAL_MEM_END) { 267 ivpu_err(vdev, "No space for shared region, start %lld, size %lld\n", start, size); 268 return -EINVAL; 269 } 270 271 ivpu_hw_range_init(&vdev->hw->ranges.global, start, size); 272 return 0; 273 } 274 275 static int ivpu_fw_mem_init(struct ivpu_device *vdev) 276 { 277 struct ivpu_fw_info *fw = vdev->fw; 278 struct ivpu_addr_range fw_range; 279 int log_verb_size; 280 int ret; 281 282 ret = ivpu_fw_update_global_range(vdev); 283 if (ret) 284 return ret; 285 286 fw_range.start = fw->runtime_addr; 287 fw_range.end = fw->runtime_addr + fw->runtime_size; 288 fw->mem = ivpu_bo_create(vdev, &vdev->gctx, &fw_range, fw->runtime_size, 289 DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE); 290 if (!fw->mem) { 291 ivpu_err(vdev, "Failed to create firmware runtime memory buffer\n"); 292 return -ENOMEM; 293 } 294 295 ret = ivpu_mmu_context_set_pages_ro(vdev, &vdev->gctx, fw->read_only_addr, 296 fw->read_only_size); 297 if (ret) { 298 ivpu_err(vdev, "Failed to set firmware image read-only\n"); 299 goto err_free_fw_mem; 300 } 301 302 fw->mem_log_crit = ivpu_bo_create_global(vdev, IVPU_FW_CRITICAL_BUFFER_SIZE, 303 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE); 304 if (!fw->mem_log_crit) { 305 ivpu_err(vdev, "Failed to create critical log buffer\n"); 306 ret = -ENOMEM; 307 goto err_free_fw_mem; 308 } 309 310 if (ivpu_log_level <= IVPU_FW_LOG_INFO) 311 log_verb_size = IVPU_FW_VERBOSE_BUFFER_LARGE_SIZE; 312 else 313 log_verb_size = IVPU_FW_VERBOSE_BUFFER_SMALL_SIZE; 314 315 fw->mem_log_verb = ivpu_bo_create_global(vdev, log_verb_size, 316 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE); 317 if (!fw->mem_log_verb) { 318 ivpu_err(vdev, "Failed to create verbose log buffer\n"); 319 ret = -ENOMEM; 320 goto err_free_log_crit; 321 } 322 323 if (fw->shave_nn_size) { 324 fw->mem_shave_nn = ivpu_bo_create(vdev, &vdev->gctx, &vdev->hw->ranges.shave, 325 fw->shave_nn_size, DRM_IVPU_BO_WC); 326 if (!fw->mem_shave_nn) { 327 ivpu_err(vdev, "Failed to create shavenn buffer\n"); 328 ret = -ENOMEM; 329 goto err_free_log_verb; 330 } 331 } 332 333 return 0; 334 335 err_free_log_verb: 336 ivpu_bo_free(fw->mem_log_verb); 337 err_free_log_crit: 338 ivpu_bo_free(fw->mem_log_crit); 339 err_free_fw_mem: 340 ivpu_bo_free(fw->mem); 341 return ret; 342 } 343 344 static void ivpu_fw_mem_fini(struct ivpu_device *vdev) 345 { 346 struct ivpu_fw_info *fw = vdev->fw; 347 348 if (fw->mem_shave_nn) { 349 ivpu_bo_free(fw->mem_shave_nn); 350 fw->mem_shave_nn = NULL; 351 } 352 353 ivpu_bo_free(fw->mem_log_verb); 354 ivpu_bo_free(fw->mem_log_crit); 355 ivpu_bo_free(fw->mem); 356 357 fw->mem_log_verb = NULL; 358 fw->mem_log_crit = NULL; 359 fw->mem = NULL; 360 } 361 362 int ivpu_fw_init(struct ivpu_device *vdev) 363 { 364 int ret; 365 366 ret = ivpu_fw_request(vdev); 367 if (ret) 368 return ret; 369 370 ret = ivpu_fw_parse(vdev); 371 if (ret) 372 goto err_fw_release; 373 374 ivpu_fw_init_wa(vdev); 375 376 ret = ivpu_fw_mem_init(vdev); 377 if (ret) 378 goto err_fw_release; 379 380 ivpu_fw_load(vdev); 381 382 return 0; 383 384 err_fw_release: 385 ivpu_fw_release(vdev); 386 return ret; 387 } 388 389 void ivpu_fw_fini(struct ivpu_device *vdev) 390 { 391 ivpu_fw_mem_fini(vdev); 392 ivpu_fw_release(vdev); 393 } 394 395 void ivpu_fw_load(struct ivpu_device *vdev) 396 { 397 struct ivpu_fw_info *fw = vdev->fw; 398 u64 image_end_offset = fw->image_load_offset + fw->image_size; 399 400 memset(ivpu_bo_vaddr(fw->mem), 0, fw->image_load_offset); 401 memcpy(ivpu_bo_vaddr(fw->mem) + fw->image_load_offset, 402 fw->file->data + FW_FILE_IMAGE_OFFSET, fw->image_size); 403 404 if (IVPU_WA(clear_runtime_mem)) { 405 u8 *start = ivpu_bo_vaddr(fw->mem) + image_end_offset; 406 u64 size = ivpu_bo_size(fw->mem) - image_end_offset; 407 408 memset(start, 0, size); 409 } 410 411 wmb(); /* Flush WC buffers after writing fw->mem */ 412 } 413 414 static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 415 { 416 ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n", 417 boot_params->magic); 418 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n", 419 boot_params->vpu_id); 420 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n", 421 boot_params->vpu_count); 422 ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n", 423 boot_params->frequency); 424 ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n", 425 boot_params->perf_clk_frequency); 426 427 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_start = 0x%llx\n", 428 boot_params->ipc_header_area_start); 429 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_size = 0x%x\n", 430 boot_params->ipc_header_area_size); 431 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_base = 0x%llx\n", 432 boot_params->shared_region_base); 433 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_size = 0x%x\n", 434 boot_params->shared_region_size); 435 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_start = 0x%llx\n", 436 boot_params->ipc_payload_area_start); 437 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_size = 0x%x\n", 438 boot_params->ipc_payload_area_size); 439 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_base = 0x%llx\n", 440 boot_params->global_aliased_pio_base); 441 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_size = 0x%x\n", 442 boot_params->global_aliased_pio_size); 443 444 ivpu_dbg(vdev, FW_BOOT, "boot_params.autoconfig = 0x%x\n", 445 boot_params->autoconfig); 446 447 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 0x%x\n", 448 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use); 449 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 0x%x\n", 450 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg); 451 452 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_base = 0x%llx\n", 453 boot_params->global_memory_allocator_base); 454 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_size = 0x%x\n", 455 boot_params->global_memory_allocator_size); 456 457 ivpu_dbg(vdev, FW_BOOT, "boot_params.shave_nn_fw_base = 0x%llx\n", 458 boot_params->shave_nn_fw_base); 459 460 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_mss = 0x%x\n", 461 boot_params->watchdog_irq_mss); 462 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_nce = 0x%x\n", 463 boot_params->watchdog_irq_nce); 464 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_to_vpu_irq = 0x%x\n", 465 boot_params->host_to_vpu_irq); 466 ivpu_dbg(vdev, FW_BOOT, "boot_params.job_done_irq = 0x%x\n", 467 boot_params->job_done_irq); 468 469 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_version_id = 0x%x\n", 470 boot_params->host_version_id); 471 ivpu_dbg(vdev, FW_BOOT, "boot_params.si_stepping = 0x%x\n", 472 boot_params->si_stepping); 473 ivpu_dbg(vdev, FW_BOOT, "boot_params.device_id = 0x%llx\n", 474 boot_params->device_id); 475 ivpu_dbg(vdev, FW_BOOT, "boot_params.feature_exclusion = 0x%llx\n", 476 boot_params->feature_exclusion); 477 ivpu_dbg(vdev, FW_BOOT, "boot_params.sku = 0x%llx\n", 478 boot_params->sku); 479 ivpu_dbg(vdev, FW_BOOT, "boot_params.min_freq_pll_ratio = 0x%x\n", 480 boot_params->min_freq_pll_ratio); 481 ivpu_dbg(vdev, FW_BOOT, "boot_params.pn_freq_pll_ratio = 0x%x\n", 482 boot_params->pn_freq_pll_ratio); 483 ivpu_dbg(vdev, FW_BOOT, "boot_params.max_freq_pll_ratio = 0x%x\n", 484 boot_params->max_freq_pll_ratio); 485 ivpu_dbg(vdev, FW_BOOT, "boot_params.default_trace_level = 0x%x\n", 486 boot_params->default_trace_level); 487 ivpu_dbg(vdev, FW_BOOT, "boot_params.tracing_buff_message_format_mask = 0x%llx\n", 488 boot_params->tracing_buff_message_format_mask); 489 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_destination_mask = 0x%x\n", 490 boot_params->trace_destination_mask); 491 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_hw_component_mask = 0x%llx\n", 492 boot_params->trace_hw_component_mask); 493 ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n", 494 boot_params->boot_type); 495 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_base = 0x%llx\n", 496 boot_params->punit_telemetry_sram_base); 497 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_size = 0x%llx\n", 498 boot_params->punit_telemetry_sram_size); 499 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n", 500 boot_params->vpu_telemetry_enable); 501 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_scheduling_mode = 0x%x\n", 502 boot_params->vpu_scheduling_mode); 503 ivpu_dbg(vdev, FW_BOOT, "boot_params.dvfs_mode = %u\n", 504 boot_params->dvfs_mode); 505 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_delayed_entry = %d\n", 506 boot_params->d0i3_delayed_entry); 507 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n", 508 boot_params->d0i3_residency_time_us); 509 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n", 510 boot_params->d0i3_entry_vpu_ts); 511 ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n", 512 boot_params->system_time_us); 513 } 514 515 void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 516 { 517 struct ivpu_bo *ipc_mem_rx = vdev->ipc->mem_rx; 518 519 /* In case of warm boot only update variable params */ 520 if (!ivpu_fw_is_cold_boot(vdev)) { 521 boot_params->d0i3_residency_time_us = 522 ktime_us_delta(ktime_get_boottime(), vdev->hw->d0i3_entry_host_ts); 523 boot_params->d0i3_entry_vpu_ts = vdev->hw->d0i3_entry_vpu_ts; 524 boot_params->system_time_us = ktime_to_us(ktime_get_real()); 525 526 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n", 527 boot_params->d0i3_residency_time_us); 528 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n", 529 boot_params->d0i3_entry_vpu_ts); 530 ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n", 531 boot_params->system_time_us); 532 533 boot_params->save_restore_ret_address = 0; 534 vdev->pm->is_warmboot = true; 535 wmb(); /* Flush WC buffers after writing save_restore_ret_address */ 536 return; 537 } 538 539 vdev->pm->is_warmboot = false; 540 541 boot_params->magic = VPU_BOOT_PARAMS_MAGIC; 542 boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number; 543 boot_params->frequency = ivpu_hw_pll_freq_get(vdev); 544 545 /* 546 * This param is a debug firmware feature. It switches default clock 547 * to higher resolution one for fine-grained and more accurate firmware 548 * task profiling. 549 */ 550 boot_params->perf_clk_frequency = ivpu_hw_profiling_freq_get(vdev); 551 552 /* 553 * Uncached region of VPU address space, covers IPC buffers, job queues 554 * and log buffers, programmable to L2$ Uncached by VPU MTRR 555 */ 556 boot_params->shared_region_base = vdev->hw->ranges.global.start; 557 boot_params->shared_region_size = vdev->hw->ranges.global.end - 558 vdev->hw->ranges.global.start; 559 560 boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr; 561 boot_params->ipc_header_area_size = ivpu_bo_size(ipc_mem_rx) / 2; 562 563 boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ivpu_bo_size(ipc_mem_rx) / 2; 564 boot_params->ipc_payload_area_size = ivpu_bo_size(ipc_mem_rx) / 2; 565 566 boot_params->global_aliased_pio_base = vdev->hw->ranges.user.start; 567 boot_params->global_aliased_pio_size = ivpu_hw_range_size(&vdev->hw->ranges.user); 568 569 /* Allow configuration for L2C_PAGE_TABLE with boot param value */ 570 boot_params->autoconfig = 1; 571 572 /* Enable L2 cache for first 2GB of high memory */ 573 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1; 574 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 575 ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.shave.start); 576 577 if (vdev->fw->mem_shave_nn) 578 boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr; 579 580 boot_params->watchdog_irq_mss = WATCHDOG_MSS_REDIRECT; 581 boot_params->watchdog_irq_nce = WATCHDOG_NCE_REDIRECT; 582 boot_params->si_stepping = ivpu_revision(vdev); 583 boot_params->device_id = ivpu_device_id(vdev); 584 boot_params->feature_exclusion = vdev->hw->tile_fuse; 585 boot_params->sku = vdev->hw->sku; 586 587 boot_params->min_freq_pll_ratio = vdev->hw->pll.min_ratio; 588 boot_params->pn_freq_pll_ratio = vdev->hw->pll.pn_ratio; 589 boot_params->max_freq_pll_ratio = vdev->hw->pll.max_ratio; 590 591 boot_params->default_trace_level = vdev->fw->trace_level; 592 boot_params->tracing_buff_message_format_mask = BIT(VPU_TRACING_FORMAT_STRING); 593 boot_params->trace_destination_mask = vdev->fw->trace_destination_mask; 594 boot_params->trace_hw_component_mask = vdev->fw->trace_hw_component_mask; 595 boot_params->crit_tracing_buff_addr = vdev->fw->mem_log_crit->vpu_addr; 596 boot_params->crit_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_crit); 597 boot_params->verbose_tracing_buff_addr = vdev->fw->mem_log_verb->vpu_addr; 598 boot_params->verbose_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_verb); 599 600 boot_params->punit_telemetry_sram_base = ivpu_hw_telemetry_offset_get(vdev); 601 boot_params->punit_telemetry_sram_size = ivpu_hw_telemetry_size_get(vdev); 602 boot_params->vpu_telemetry_enable = ivpu_hw_telemetry_enable_get(vdev); 603 boot_params->vpu_scheduling_mode = vdev->hw->sched_mode; 604 if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) 605 boot_params->vpu_focus_present_timer_ms = IVPU_FOCUS_PRESENT_TIMER_MS; 606 boot_params->dvfs_mode = vdev->fw->dvfs_mode; 607 if (!IVPU_WA(disable_d0i3_msg)) 608 boot_params->d0i3_delayed_entry = 1; 609 boot_params->d0i3_residency_time_us = 0; 610 boot_params->d0i3_entry_vpu_ts = 0; 611 612 boot_params->system_time_us = ktime_to_us(ktime_get_real()); 613 wmb(); /* Flush WC buffers after writing bootparams */ 614 615 ivpu_fw_boot_params_print(vdev, boot_params); 616 } 617