1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020-2023 Intel Corporation 4 */ 5 6 #include <linux/firmware.h> 7 #include <linux/highmem.h> 8 #include <linux/moduleparam.h> 9 #include <linux/pci.h> 10 11 #include "vpu_boot_api.h" 12 #include "ivpu_drv.h" 13 #include "ivpu_fw.h" 14 #include "ivpu_gem.h" 15 #include "ivpu_hw.h" 16 #include "ivpu_ipc.h" 17 #include "ivpu_pm.h" 18 19 #define FW_GLOBAL_MEM_START (2ull * SZ_1G) 20 #define FW_GLOBAL_MEM_END (3ull * SZ_1G) 21 #define FW_SHARED_MEM_SIZE SZ_256M /* Must be aligned to FW_SHARED_MEM_ALIGNMENT */ 22 #define FW_SHARED_MEM_ALIGNMENT SZ_128K /* VPU MTRR limitation */ 23 #define FW_RUNTIME_MAX_SIZE SZ_512M 24 #define FW_SHAVE_NN_MAX_SIZE SZ_2M 25 #define FW_RUNTIME_MIN_ADDR (FW_GLOBAL_MEM_START) 26 #define FW_RUNTIME_MAX_ADDR (FW_GLOBAL_MEM_END - FW_SHARED_MEM_SIZE) 27 #define FW_VERSION_HEADER_SIZE SZ_4K 28 #define FW_FILE_IMAGE_OFFSET (VPU_FW_HEADER_SIZE + FW_VERSION_HEADER_SIZE) 29 30 #define WATCHDOG_MSS_REDIRECT 32 31 #define WATCHDOG_NCE_REDIRECT 33 32 33 #define ADDR_TO_L2_CACHE_CFG(addr) ((addr) >> 31) 34 35 #define IVPU_FW_CHECK_API(vdev, fw_hdr, name, min_major) \ 36 ivpu_fw_check_api(vdev, fw_hdr, #name, \ 37 VPU_##name##_API_VER_INDEX, \ 38 VPU_##name##_API_VER_MAJOR, \ 39 VPU_##name##_API_VER_MINOR, min_major) 40 41 static char *ivpu_firmware; 42 module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644); 43 MODULE_PARM_DESC(firmware, "VPU firmware binary in /lib/firmware/.."); 44 45 static int ivpu_fw_request(struct ivpu_device *vdev) 46 { 47 static const char * const fw_names[] = { 48 "mtl_vpu.bin", 49 "intel/vpu/mtl_vpu_v0.0.bin" 50 }; 51 int ret = -ENOENT; 52 int i; 53 54 if (ivpu_firmware) 55 return request_firmware(&vdev->fw->file, ivpu_firmware, vdev->drm.dev); 56 57 for (i = 0; i < ARRAY_SIZE(fw_names); i++) { 58 ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i], vdev->drm.dev); 59 if (!ret) 60 return 0; 61 } 62 63 ivpu_err(vdev, "Failed to request firmware: %d\n", ret); 64 return ret; 65 } 66 67 static int 68 ivpu_fw_check_api(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr, 69 const char *str, int index, u16 expected_major, u16 expected_minor, 70 u16 min_major) 71 { 72 u16 major = (u16)(fw_hdr->api_version[index] >> 16); 73 u16 minor = (u16)(fw_hdr->api_version[index]); 74 75 if (major < min_major) { 76 ivpu_err(vdev, "Incompatible FW %s API version: %d.%d, required %d.0 or later\n", 77 str, major, minor, min_major); 78 return -EINVAL; 79 } 80 if (major != expected_major) { 81 ivpu_warn(vdev, "Major FW %s API version different: %d.%d (expected %d.%d)\n", 82 str, major, minor, expected_major, expected_minor); 83 } 84 ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n", 85 str, major, minor, expected_major, expected_minor); 86 87 return 0; 88 } 89 90 static int ivpu_fw_parse(struct ivpu_device *vdev) 91 { 92 struct ivpu_fw_info *fw = vdev->fw; 93 const struct vpu_firmware_header *fw_hdr = (const void *)fw->file->data; 94 u64 runtime_addr, image_load_addr, runtime_size, image_size; 95 96 if (fw->file->size <= FW_FILE_IMAGE_OFFSET) { 97 ivpu_err(vdev, "Firmware file is too small: %zu\n", fw->file->size); 98 return -EINVAL; 99 } 100 101 if (fw_hdr->header_version != VPU_FW_HEADER_VERSION) { 102 ivpu_err(vdev, "Invalid firmware header version: %u\n", fw_hdr->header_version); 103 return -EINVAL; 104 } 105 106 runtime_addr = fw_hdr->boot_params_load_address; 107 runtime_size = fw_hdr->runtime_size; 108 image_load_addr = fw_hdr->image_load_address; 109 image_size = fw_hdr->image_size; 110 111 if (runtime_addr < FW_RUNTIME_MIN_ADDR || runtime_addr > FW_RUNTIME_MAX_ADDR) { 112 ivpu_err(vdev, "Invalid firmware runtime address: 0x%llx\n", runtime_addr); 113 return -EINVAL; 114 } 115 116 if (runtime_size < fw->file->size || runtime_size > FW_RUNTIME_MAX_SIZE) { 117 ivpu_err(vdev, "Invalid firmware runtime size: %llu\n", runtime_size); 118 return -EINVAL; 119 } 120 121 if (FW_FILE_IMAGE_OFFSET + image_size > fw->file->size) { 122 ivpu_err(vdev, "Invalid image size: %llu\n", image_size); 123 return -EINVAL; 124 } 125 126 if (image_load_addr < runtime_addr || 127 image_load_addr + image_size > runtime_addr + runtime_size) { 128 ivpu_err(vdev, "Invalid firmware load address size: 0x%llx and size %llu\n", 129 image_load_addr, image_size); 130 return -EINVAL; 131 } 132 133 if (fw_hdr->shave_nn_fw_size > FW_SHAVE_NN_MAX_SIZE) { 134 ivpu_err(vdev, "SHAVE NN firmware is too big: %u\n", fw_hdr->shave_nn_fw_size); 135 return -EINVAL; 136 } 137 138 if (fw_hdr->entry_point < image_load_addr || 139 fw_hdr->entry_point >= image_load_addr + image_size) { 140 ivpu_err(vdev, "Invalid entry point: 0x%llx\n", fw_hdr->entry_point); 141 return -EINVAL; 142 } 143 ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n", 144 fw_hdr->header_version, fw_hdr->image_format); 145 ivpu_dbg(vdev, FW_BOOT, "FW version: %s\n", (char *)fw_hdr + VPU_FW_HEADER_SIZE); 146 147 if (IVPU_FW_CHECK_API(vdev, fw_hdr, BOOT, 3)) 148 return -EINVAL; 149 if (IVPU_FW_CHECK_API(vdev, fw_hdr, JSM, 3)) 150 return -EINVAL; 151 152 fw->runtime_addr = runtime_addr; 153 fw->runtime_size = runtime_size; 154 fw->image_load_offset = image_load_addr - runtime_addr; 155 fw->image_size = image_size; 156 fw->shave_nn_size = PAGE_ALIGN(fw_hdr->shave_nn_fw_size); 157 158 fw->cold_boot_entry_point = fw_hdr->entry_point; 159 fw->entry_point = fw->cold_boot_entry_point; 160 161 ivpu_dbg(vdev, FW_BOOT, "Size: file %lu image %u runtime %u shavenn %u\n", 162 fw->file->size, fw->image_size, fw->runtime_size, fw->shave_nn_size); 163 ivpu_dbg(vdev, FW_BOOT, "Address: runtime 0x%llx, load 0x%llx, entry point 0x%llx\n", 164 fw->runtime_addr, image_load_addr, fw->entry_point); 165 166 return 0; 167 } 168 169 static void ivpu_fw_release(struct ivpu_device *vdev) 170 { 171 release_firmware(vdev->fw->file); 172 } 173 174 static int ivpu_fw_update_global_range(struct ivpu_device *vdev) 175 { 176 struct ivpu_fw_info *fw = vdev->fw; 177 u64 start = ALIGN(fw->runtime_addr + fw->runtime_size, FW_SHARED_MEM_ALIGNMENT); 178 u64 size = FW_SHARED_MEM_SIZE; 179 180 if (start + size > FW_GLOBAL_MEM_END) { 181 ivpu_err(vdev, "No space for shared region, start %lld, size %lld\n", start, size); 182 return -EINVAL; 183 } 184 185 ivpu_hw_init_range(&vdev->hw->ranges.global_low, start, size); 186 return 0; 187 } 188 189 static int ivpu_fw_mem_init(struct ivpu_device *vdev) 190 { 191 struct ivpu_fw_info *fw = vdev->fw; 192 int ret; 193 194 ret = ivpu_fw_update_global_range(vdev); 195 if (ret) 196 return ret; 197 198 fw->mem = ivpu_bo_alloc_internal(vdev, fw->runtime_addr, fw->runtime_size, DRM_IVPU_BO_WC); 199 if (!fw->mem) { 200 ivpu_err(vdev, "Failed to allocate firmware runtime memory\n"); 201 return -ENOMEM; 202 } 203 204 if (fw->shave_nn_size) { 205 fw->mem_shave_nn = ivpu_bo_alloc_internal(vdev, vdev->hw->ranges.global_high.start, 206 fw->shave_nn_size, DRM_IVPU_BO_UNCACHED); 207 if (!fw->mem_shave_nn) { 208 ivpu_err(vdev, "Failed to allocate shavenn buffer\n"); 209 ivpu_bo_free_internal(fw->mem); 210 return -ENOMEM; 211 } 212 } 213 214 return 0; 215 } 216 217 static void ivpu_fw_mem_fini(struct ivpu_device *vdev) 218 { 219 struct ivpu_fw_info *fw = vdev->fw; 220 221 if (fw->mem_shave_nn) { 222 ivpu_bo_free_internal(fw->mem_shave_nn); 223 fw->mem_shave_nn = NULL; 224 } 225 226 ivpu_bo_free_internal(fw->mem); 227 fw->mem = NULL; 228 } 229 230 int ivpu_fw_init(struct ivpu_device *vdev) 231 { 232 int ret; 233 234 ret = ivpu_fw_request(vdev); 235 if (ret) 236 return ret; 237 238 ret = ivpu_fw_parse(vdev); 239 if (ret) 240 goto err_fw_release; 241 242 ret = ivpu_fw_mem_init(vdev); 243 if (ret) 244 goto err_fw_release; 245 246 return 0; 247 248 err_fw_release: 249 ivpu_fw_release(vdev); 250 return ret; 251 } 252 253 void ivpu_fw_fini(struct ivpu_device *vdev) 254 { 255 ivpu_fw_mem_fini(vdev); 256 ivpu_fw_release(vdev); 257 } 258 259 int ivpu_fw_load(struct ivpu_device *vdev) 260 { 261 struct ivpu_fw_info *fw = vdev->fw; 262 u64 image_end_offset = fw->image_load_offset + fw->image_size; 263 264 memset(fw->mem->kvaddr, 0, fw->image_load_offset); 265 memcpy(fw->mem->kvaddr + fw->image_load_offset, 266 fw->file->data + FW_FILE_IMAGE_OFFSET, fw->image_size); 267 268 if (IVPU_WA(clear_runtime_mem)) { 269 u8 *start = fw->mem->kvaddr + image_end_offset; 270 u64 size = fw->mem->base.size - image_end_offset; 271 272 memset(start, 0, size); 273 } 274 275 wmb(); /* Flush WC buffers after writing fw->mem */ 276 277 return 0; 278 } 279 280 static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 281 { 282 ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n", 283 boot_params->magic); 284 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n", 285 boot_params->vpu_id); 286 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n", 287 boot_params->vpu_count); 288 ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n", 289 boot_params->frequency); 290 ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n", 291 boot_params->perf_clk_frequency); 292 293 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_start = 0x%llx\n", 294 boot_params->ipc_header_area_start); 295 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_size = 0x%x\n", 296 boot_params->ipc_header_area_size); 297 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_base = 0x%llx\n", 298 boot_params->shared_region_base); 299 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_size = 0x%x\n", 300 boot_params->shared_region_size); 301 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_start = 0x%llx\n", 302 boot_params->ipc_payload_area_start); 303 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_size = 0x%x\n", 304 boot_params->ipc_payload_area_size); 305 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_base = 0x%llx\n", 306 boot_params->global_aliased_pio_base); 307 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_size = 0x%x\n", 308 boot_params->global_aliased_pio_size); 309 310 ivpu_dbg(vdev, FW_BOOT, "boot_params.autoconfig = 0x%x\n", 311 boot_params->autoconfig); 312 313 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 0x%x\n", 314 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use); 315 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 0x%x\n", 316 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg); 317 318 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_base = 0x%llx\n", 319 boot_params->global_memory_allocator_base); 320 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_size = 0x%x\n", 321 boot_params->global_memory_allocator_size); 322 323 ivpu_dbg(vdev, FW_BOOT, "boot_params.shave_nn_fw_base = 0x%llx\n", 324 boot_params->shave_nn_fw_base); 325 326 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_mss = 0x%x\n", 327 boot_params->watchdog_irq_mss); 328 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_nce = 0x%x\n", 329 boot_params->watchdog_irq_nce); 330 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_to_vpu_irq = 0x%x\n", 331 boot_params->host_to_vpu_irq); 332 ivpu_dbg(vdev, FW_BOOT, "boot_params.job_done_irq = 0x%x\n", 333 boot_params->job_done_irq); 334 335 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_version_id = 0x%x\n", 336 boot_params->host_version_id); 337 ivpu_dbg(vdev, FW_BOOT, "boot_params.si_stepping = 0x%x\n", 338 boot_params->si_stepping); 339 ivpu_dbg(vdev, FW_BOOT, "boot_params.device_id = 0x%llx\n", 340 boot_params->device_id); 341 ivpu_dbg(vdev, FW_BOOT, "boot_params.feature_exclusion = 0x%llx\n", 342 boot_params->feature_exclusion); 343 ivpu_dbg(vdev, FW_BOOT, "boot_params.sku = 0x%llx\n", 344 boot_params->sku); 345 ivpu_dbg(vdev, FW_BOOT, "boot_params.min_freq_pll_ratio = 0x%x\n", 346 boot_params->min_freq_pll_ratio); 347 ivpu_dbg(vdev, FW_BOOT, "boot_params.pn_freq_pll_ratio = 0x%x\n", 348 boot_params->pn_freq_pll_ratio); 349 ivpu_dbg(vdev, FW_BOOT, "boot_params.max_freq_pll_ratio = 0x%x\n", 350 boot_params->max_freq_pll_ratio); 351 ivpu_dbg(vdev, FW_BOOT, "boot_params.default_trace_level = 0x%x\n", 352 boot_params->default_trace_level); 353 ivpu_dbg(vdev, FW_BOOT, "boot_params.tracing_buff_message_format_mask = 0x%llx\n", 354 boot_params->tracing_buff_message_format_mask); 355 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_destination_mask = 0x%x\n", 356 boot_params->trace_destination_mask); 357 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_hw_component_mask = 0x%llx\n", 358 boot_params->trace_hw_component_mask); 359 ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n", 360 boot_params->boot_type); 361 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_base = 0x%llx\n", 362 boot_params->punit_telemetry_sram_base); 363 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_size = 0x%llx\n", 364 boot_params->punit_telemetry_sram_size); 365 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n", 366 boot_params->vpu_telemetry_enable); 367 } 368 369 void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 370 { 371 struct ivpu_bo *ipc_mem_rx = vdev->ipc->mem_rx; 372 373 /* In case of warm boot we only have to reset the entrypoint addr */ 374 if (!ivpu_fw_is_cold_boot(vdev)) { 375 boot_params->save_restore_ret_address = 0; 376 vdev->pm->is_warmboot = true; 377 return; 378 } 379 380 vdev->pm->is_warmboot = false; 381 382 boot_params->magic = VPU_BOOT_PARAMS_MAGIC; 383 boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number; 384 boot_params->frequency = ivpu_hw_reg_pll_freq_get(vdev); 385 386 /* 387 * Uncached region of VPU address space, covers IPC buffers, job queues 388 * and log buffers, programmable to L2$ Uncached by VPU MTRR 389 */ 390 boot_params->shared_region_base = vdev->hw->ranges.global_low.start; 391 boot_params->shared_region_size = vdev->hw->ranges.global_low.end - 392 vdev->hw->ranges.global_low.start; 393 394 boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr; 395 boot_params->ipc_header_area_size = ipc_mem_rx->base.size / 2; 396 397 boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ipc_mem_rx->base.size / 2; 398 boot_params->ipc_payload_area_size = ipc_mem_rx->base.size / 2; 399 400 boot_params->global_aliased_pio_base = 401 vdev->hw->ranges.global_aliased_pio.start; 402 boot_params->global_aliased_pio_size = 403 ivpu_hw_range_size(&vdev->hw->ranges.global_aliased_pio); 404 405 /* Allow configuration for L2C_PAGE_TABLE with boot param value */ 406 boot_params->autoconfig = 1; 407 408 /* Enable L2 cache for first 2GB of high memory */ 409 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1; 410 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 411 ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.global_high.start); 412 413 if (vdev->fw->mem_shave_nn) 414 boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr; 415 416 boot_params->watchdog_irq_mss = WATCHDOG_MSS_REDIRECT; 417 boot_params->watchdog_irq_nce = WATCHDOG_NCE_REDIRECT; 418 boot_params->si_stepping = ivpu_revision(vdev); 419 boot_params->device_id = ivpu_device_id(vdev); 420 boot_params->feature_exclusion = vdev->hw->tile_fuse; 421 boot_params->sku = vdev->hw->sku; 422 423 boot_params->min_freq_pll_ratio = vdev->hw->pll.min_ratio; 424 boot_params->pn_freq_pll_ratio = vdev->hw->pll.pn_ratio; 425 boot_params->max_freq_pll_ratio = vdev->hw->pll.max_ratio; 426 427 boot_params->punit_telemetry_sram_base = ivpu_hw_reg_telemetry_offset_get(vdev); 428 boot_params->punit_telemetry_sram_size = ivpu_hw_reg_telemetry_size_get(vdev); 429 boot_params->vpu_telemetry_enable = ivpu_hw_reg_telemetry_enable_get(vdev); 430 431 wmb(); /* Flush WC buffers after writing bootparams */ 432 433 ivpu_fw_boot_params_print(vdev, boot_params); 434 } 435