1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020-2023 Intel Corporation 4 */ 5 6 #include <linux/firmware.h> 7 #include <linux/highmem.h> 8 #include <linux/moduleparam.h> 9 #include <linux/pci.h> 10 11 #include "vpu_boot_api.h" 12 #include "ivpu_drv.h" 13 #include "ivpu_fw.h" 14 #include "ivpu_gem.h" 15 #include "ivpu_hw.h" 16 #include "ivpu_ipc.h" 17 18 #define FW_GLOBAL_MEM_START (2ull * SZ_1G) 19 #define FW_GLOBAL_MEM_END (3ull * SZ_1G) 20 #define FW_SHARED_MEM_SIZE SZ_256M /* Must be aligned to FW_SHARED_MEM_ALIGNMENT */ 21 #define FW_SHARED_MEM_ALIGNMENT SZ_128K /* VPU MTRR limitation */ 22 #define FW_RUNTIME_MAX_SIZE SZ_512M 23 #define FW_SHAVE_NN_MAX_SIZE SZ_2M 24 #define FW_RUNTIME_MIN_ADDR (FW_GLOBAL_MEM_START) 25 #define FW_RUNTIME_MAX_ADDR (FW_GLOBAL_MEM_END - FW_SHARED_MEM_SIZE) 26 #define FW_VERSION_HEADER_SIZE SZ_4K 27 #define FW_FILE_IMAGE_OFFSET (VPU_FW_HEADER_SIZE + FW_VERSION_HEADER_SIZE) 28 29 #define WATCHDOG_MSS_REDIRECT 32 30 #define WATCHDOG_NCE_REDIRECT 33 31 32 #define ADDR_TO_L2_CACHE_CFG(addr) ((addr) >> 31) 33 34 #define IVPU_FW_CHECK_API(vdev, fw_hdr, name) ivpu_fw_check_api(vdev, fw_hdr, #name, \ 35 VPU_##name##_API_VER_INDEX, \ 36 VPU_##name##_API_VER_MAJOR, \ 37 VPU_##name##_API_VER_MINOR) 38 39 static char *ivpu_firmware; 40 module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644); 41 MODULE_PARM_DESC(firmware, "VPU firmware binary in /lib/firmware/.."); 42 43 static int ivpu_fw_request(struct ivpu_device *vdev) 44 { 45 static const char * const fw_names[] = { 46 "mtl_vpu.bin", 47 "intel/vpu/mtl_vpu_v0.0.bin" 48 }; 49 int ret = -ENOENT; 50 int i; 51 52 if (ivpu_firmware) 53 return request_firmware(&vdev->fw->file, ivpu_firmware, vdev->drm.dev); 54 55 for (i = 0; i < ARRAY_SIZE(fw_names); i++) { 56 ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i], vdev->drm.dev); 57 if (!ret) 58 return 0; 59 } 60 61 ivpu_err(vdev, "Failed to request firmware: %d\n", ret); 62 return ret; 63 } 64 65 static void 66 ivpu_fw_check_api(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr, 67 const char *str, int index, u16 expected_major, u16 expected_minor) 68 { 69 u16 major = (u16)(fw_hdr->api_version[index] >> 16); 70 u16 minor = (u16)(fw_hdr->api_version[index]); 71 72 if (major != expected_major) { 73 ivpu_warn(vdev, "Incompatible FW %s API version: %d.%d (expected %d.%d)\n", 74 str, major, minor, expected_major, expected_minor); 75 } 76 ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n", 77 str, major, minor, expected_major, expected_minor); 78 } 79 80 static int ivpu_fw_parse(struct ivpu_device *vdev) 81 { 82 struct ivpu_fw_info *fw = vdev->fw; 83 const struct vpu_firmware_header *fw_hdr = (const void *)fw->file->data; 84 u64 runtime_addr, image_load_addr, runtime_size, image_size; 85 86 if (fw->file->size <= FW_FILE_IMAGE_OFFSET) { 87 ivpu_err(vdev, "Firmware file is too small: %zu\n", fw->file->size); 88 return -EINVAL; 89 } 90 91 if (fw_hdr->header_version != VPU_FW_HEADER_VERSION) { 92 ivpu_err(vdev, "Invalid firmware header version: %u\n", fw_hdr->header_version); 93 return -EINVAL; 94 } 95 96 runtime_addr = fw_hdr->boot_params_load_address; 97 runtime_size = fw_hdr->runtime_size; 98 image_load_addr = fw_hdr->image_load_address; 99 image_size = fw_hdr->image_size; 100 101 if (runtime_addr < FW_RUNTIME_MIN_ADDR || runtime_addr > FW_RUNTIME_MAX_ADDR) { 102 ivpu_err(vdev, "Invalid firmware runtime address: 0x%llx\n", runtime_addr); 103 return -EINVAL; 104 } 105 106 if (runtime_size < fw->file->size || runtime_size > FW_RUNTIME_MAX_SIZE) { 107 ivpu_err(vdev, "Invalid firmware runtime size: %llu\n", runtime_size); 108 return -EINVAL; 109 } 110 111 if (FW_FILE_IMAGE_OFFSET + image_size > fw->file->size) { 112 ivpu_err(vdev, "Invalid image size: %llu\n", image_size); 113 return -EINVAL; 114 } 115 116 if (image_load_addr < runtime_addr || 117 image_load_addr + image_size > runtime_addr + runtime_size) { 118 ivpu_err(vdev, "Invalid firmware load address size: 0x%llx and size %llu\n", 119 image_load_addr, image_size); 120 return -EINVAL; 121 } 122 123 if (fw_hdr->shave_nn_fw_size > FW_SHAVE_NN_MAX_SIZE) { 124 ivpu_err(vdev, "SHAVE NN firmware is too big: %u\n", fw_hdr->shave_nn_fw_size); 125 return -EINVAL; 126 } 127 128 if (fw_hdr->entry_point < image_load_addr || 129 fw_hdr->entry_point >= image_load_addr + image_size) { 130 ivpu_err(vdev, "Invalid entry point: 0x%llx\n", fw_hdr->entry_point); 131 return -EINVAL; 132 } 133 134 fw->runtime_addr = runtime_addr; 135 fw->runtime_size = runtime_size; 136 fw->image_load_offset = image_load_addr - runtime_addr; 137 fw->image_size = image_size; 138 fw->shave_nn_size = PAGE_ALIGN(fw_hdr->shave_nn_fw_size); 139 140 fw->cold_boot_entry_point = fw_hdr->entry_point; 141 fw->entry_point = fw->cold_boot_entry_point; 142 143 ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n", 144 fw_hdr->header_version, fw_hdr->image_format); 145 ivpu_dbg(vdev, FW_BOOT, "Size: file %lu image %u runtime %u shavenn %u\n", 146 fw->file->size, fw->image_size, fw->runtime_size, fw->shave_nn_size); 147 ivpu_dbg(vdev, FW_BOOT, "Address: runtime 0x%llx, load 0x%llx, entry point 0x%llx\n", 148 fw->runtime_addr, image_load_addr, fw->entry_point); 149 ivpu_dbg(vdev, FW_BOOT, "FW version: %s\n", (char *)fw_hdr + VPU_FW_HEADER_SIZE); 150 151 IVPU_FW_CHECK_API(vdev, fw_hdr, BOOT); 152 IVPU_FW_CHECK_API(vdev, fw_hdr, JSM); 153 154 return 0; 155 } 156 157 static void ivpu_fw_release(struct ivpu_device *vdev) 158 { 159 release_firmware(vdev->fw->file); 160 } 161 162 static int ivpu_fw_update_global_range(struct ivpu_device *vdev) 163 { 164 struct ivpu_fw_info *fw = vdev->fw; 165 u64 start = ALIGN(fw->runtime_addr + fw->runtime_size, FW_SHARED_MEM_ALIGNMENT); 166 u64 size = FW_SHARED_MEM_SIZE; 167 168 if (start + size > FW_GLOBAL_MEM_END) { 169 ivpu_err(vdev, "No space for shared region, start %lld, size %lld\n", start, size); 170 return -EINVAL; 171 } 172 173 ivpu_hw_init_range(&vdev->hw->ranges.global_low, start, size); 174 return 0; 175 } 176 177 static int ivpu_fw_mem_init(struct ivpu_device *vdev) 178 { 179 struct ivpu_fw_info *fw = vdev->fw; 180 int ret; 181 182 ret = ivpu_fw_update_global_range(vdev); 183 if (ret) 184 return ret; 185 186 fw->mem = ivpu_bo_alloc_internal(vdev, fw->runtime_addr, fw->runtime_size, DRM_IVPU_BO_WC); 187 if (!fw->mem) { 188 ivpu_err(vdev, "Failed to allocate firmware runtime memory\n"); 189 return -ENOMEM; 190 } 191 192 if (fw->shave_nn_size) { 193 fw->mem_shave_nn = ivpu_bo_alloc_internal(vdev, vdev->hw->ranges.global_high.start, 194 fw->shave_nn_size, DRM_IVPU_BO_UNCACHED); 195 if (!fw->mem_shave_nn) { 196 ivpu_err(vdev, "Failed to allocate shavenn buffer\n"); 197 ivpu_bo_free_internal(fw->mem); 198 return -ENOMEM; 199 } 200 } 201 202 return 0; 203 } 204 205 static void ivpu_fw_mem_fini(struct ivpu_device *vdev) 206 { 207 struct ivpu_fw_info *fw = vdev->fw; 208 209 if (fw->mem_shave_nn) { 210 ivpu_bo_free_internal(fw->mem_shave_nn); 211 fw->mem_shave_nn = NULL; 212 } 213 214 ivpu_bo_free_internal(fw->mem); 215 fw->mem = NULL; 216 } 217 218 int ivpu_fw_init(struct ivpu_device *vdev) 219 { 220 int ret; 221 222 ret = ivpu_fw_request(vdev); 223 if (ret) 224 return ret; 225 226 ret = ivpu_fw_parse(vdev); 227 if (ret) 228 goto err_fw_release; 229 230 ret = ivpu_fw_mem_init(vdev); 231 if (ret) 232 goto err_fw_release; 233 234 return 0; 235 236 err_fw_release: 237 ivpu_fw_release(vdev); 238 return ret; 239 } 240 241 void ivpu_fw_fini(struct ivpu_device *vdev) 242 { 243 ivpu_fw_mem_fini(vdev); 244 ivpu_fw_release(vdev); 245 } 246 247 int ivpu_fw_load(struct ivpu_device *vdev) 248 { 249 struct ivpu_fw_info *fw = vdev->fw; 250 u64 image_end_offset = fw->image_load_offset + fw->image_size; 251 252 memset(fw->mem->kvaddr, 0, fw->image_load_offset); 253 memcpy(fw->mem->kvaddr + fw->image_load_offset, 254 fw->file->data + FW_FILE_IMAGE_OFFSET, fw->image_size); 255 256 if (IVPU_WA(clear_runtime_mem)) { 257 u8 *start = fw->mem->kvaddr + image_end_offset; 258 u64 size = fw->mem->base.size - image_end_offset; 259 260 memset(start, 0, size); 261 } 262 263 wmb(); /* Flush WC buffers after writing fw->mem */ 264 265 return 0; 266 } 267 268 static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 269 { 270 ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n", 271 boot_params->magic); 272 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n", 273 boot_params->vpu_id); 274 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n", 275 boot_params->vpu_count); 276 ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n", 277 boot_params->frequency); 278 ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n", 279 boot_params->perf_clk_frequency); 280 281 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_start = 0x%llx\n", 282 boot_params->ipc_header_area_start); 283 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_size = 0x%x\n", 284 boot_params->ipc_header_area_size); 285 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_base = 0x%llx\n", 286 boot_params->shared_region_base); 287 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_size = 0x%x\n", 288 boot_params->shared_region_size); 289 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_start = 0x%llx\n", 290 boot_params->ipc_payload_area_start); 291 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_size = 0x%x\n", 292 boot_params->ipc_payload_area_size); 293 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_base = 0x%llx\n", 294 boot_params->global_aliased_pio_base); 295 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_size = 0x%x\n", 296 boot_params->global_aliased_pio_size); 297 298 ivpu_dbg(vdev, FW_BOOT, "boot_params.autoconfig = 0x%x\n", 299 boot_params->autoconfig); 300 301 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 0x%x\n", 302 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use); 303 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 0x%x\n", 304 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg); 305 306 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_base = 0x%llx\n", 307 boot_params->global_memory_allocator_base); 308 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_size = 0x%x\n", 309 boot_params->global_memory_allocator_size); 310 311 ivpu_dbg(vdev, FW_BOOT, "boot_params.shave_nn_fw_base = 0x%llx\n", 312 boot_params->shave_nn_fw_base); 313 314 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_mss = 0x%x\n", 315 boot_params->watchdog_irq_mss); 316 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_nce = 0x%x\n", 317 boot_params->watchdog_irq_nce); 318 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_to_vpu_irq = 0x%x\n", 319 boot_params->host_to_vpu_irq); 320 ivpu_dbg(vdev, FW_BOOT, "boot_params.job_done_irq = 0x%x\n", 321 boot_params->job_done_irq); 322 323 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_version_id = 0x%x\n", 324 boot_params->host_version_id); 325 ivpu_dbg(vdev, FW_BOOT, "boot_params.si_stepping = 0x%x\n", 326 boot_params->si_stepping); 327 ivpu_dbg(vdev, FW_BOOT, "boot_params.device_id = 0x%llx\n", 328 boot_params->device_id); 329 ivpu_dbg(vdev, FW_BOOT, "boot_params.feature_exclusion = 0x%llx\n", 330 boot_params->feature_exclusion); 331 ivpu_dbg(vdev, FW_BOOT, "boot_params.sku = 0x%llx\n", 332 boot_params->sku); 333 ivpu_dbg(vdev, FW_BOOT, "boot_params.min_freq_pll_ratio = 0x%x\n", 334 boot_params->min_freq_pll_ratio); 335 ivpu_dbg(vdev, FW_BOOT, "boot_params.pn_freq_pll_ratio = 0x%x\n", 336 boot_params->pn_freq_pll_ratio); 337 ivpu_dbg(vdev, FW_BOOT, "boot_params.max_freq_pll_ratio = 0x%x\n", 338 boot_params->max_freq_pll_ratio); 339 ivpu_dbg(vdev, FW_BOOT, "boot_params.default_trace_level = 0x%x\n", 340 boot_params->default_trace_level); 341 ivpu_dbg(vdev, FW_BOOT, "boot_params.tracing_buff_message_format_mask = 0x%llx\n", 342 boot_params->tracing_buff_message_format_mask); 343 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_destination_mask = 0x%x\n", 344 boot_params->trace_destination_mask); 345 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_hw_component_mask = 0x%llx\n", 346 boot_params->trace_hw_component_mask); 347 ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n", 348 boot_params->boot_type); 349 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_base = 0x%llx\n", 350 boot_params->punit_telemetry_sram_base); 351 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_size = 0x%llx\n", 352 boot_params->punit_telemetry_sram_size); 353 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n", 354 boot_params->vpu_telemetry_enable); 355 } 356 357 void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 358 { 359 struct ivpu_bo *ipc_mem_rx = vdev->ipc->mem_rx; 360 361 /* In case of warm boot we only have to reset the entrypoint addr */ 362 if (!ivpu_fw_is_cold_boot(vdev)) { 363 boot_params->save_restore_ret_address = 0; 364 return; 365 } 366 367 boot_params->magic = VPU_BOOT_PARAMS_MAGIC; 368 boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number; 369 boot_params->frequency = ivpu_hw_reg_pll_freq_get(vdev); 370 371 /* 372 * Uncached region of VPU address space, covers IPC buffers, job queues 373 * and log buffers, programmable to L2$ Uncached by VPU MTRR 374 */ 375 boot_params->shared_region_base = vdev->hw->ranges.global_low.start; 376 boot_params->shared_region_size = vdev->hw->ranges.global_low.end - 377 vdev->hw->ranges.global_low.start; 378 379 boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr; 380 boot_params->ipc_header_area_size = ipc_mem_rx->base.size / 2; 381 382 boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ipc_mem_rx->base.size / 2; 383 boot_params->ipc_payload_area_size = ipc_mem_rx->base.size / 2; 384 385 boot_params->global_aliased_pio_base = 386 vdev->hw->ranges.global_aliased_pio.start; 387 boot_params->global_aliased_pio_size = 388 ivpu_hw_range_size(&vdev->hw->ranges.global_aliased_pio); 389 390 /* Allow configuration for L2C_PAGE_TABLE with boot param value */ 391 boot_params->autoconfig = 1; 392 393 /* Enable L2 cache for first 2GB of high memory */ 394 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1; 395 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 396 ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.global_high.start); 397 398 if (vdev->fw->mem_shave_nn) 399 boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr; 400 401 boot_params->watchdog_irq_mss = WATCHDOG_MSS_REDIRECT; 402 boot_params->watchdog_irq_nce = WATCHDOG_NCE_REDIRECT; 403 boot_params->si_stepping = ivpu_revision(vdev); 404 boot_params->device_id = ivpu_device_id(vdev); 405 boot_params->feature_exclusion = vdev->hw->tile_fuse; 406 boot_params->sku = vdev->hw->sku; 407 408 boot_params->min_freq_pll_ratio = vdev->hw->pll.min_ratio; 409 boot_params->pn_freq_pll_ratio = vdev->hw->pll.pn_ratio; 410 boot_params->max_freq_pll_ratio = vdev->hw->pll.max_ratio; 411 412 boot_params->punit_telemetry_sram_base = ivpu_hw_reg_telemetry_offset_get(vdev); 413 boot_params->punit_telemetry_sram_size = ivpu_hw_reg_telemetry_size_get(vdev); 414 boot_params->vpu_telemetry_enable = ivpu_hw_reg_telemetry_enable_get(vdev); 415 416 wmb(); /* Flush WC buffers after writing bootparams */ 417 418 ivpu_fw_boot_params_print(vdev, boot_params); 419 } 420