xref: /linux/drivers/accel/ivpu/ivpu_drv.h (revision face6a3615a649456eb4549f6d474221d877d604) 
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2020-2025 Intel Corporation
4  */
5 
6 #ifndef __IVPU_DRV_H__
7 #define __IVPU_DRV_H__
8 
9 #include <drm/drm_device.h>
10 #include <drm/drm_drv.h>
11 #include <drm/drm_managed.h>
12 #include <drm/drm_mm.h>
13 #include <drm/drm_print.h>
14 
15 #include <linux/pci.h>
16 #include <linux/xarray.h>
17 #include <uapi/drm/ivpu_accel.h>
18 
19 #include "ivpu_mmu_context.h"
20 #include "ivpu_ipc.h"
21 
22 #define DRIVER_NAME "intel_vpu"
23 #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"
24 
25 #define PCI_DEVICE_ID_MTL	0x7d1d
26 #define PCI_DEVICE_ID_ARL	0xad1d
27 #define PCI_DEVICE_ID_LNL	0x643e
28 #define PCI_DEVICE_ID_PTL_P	0xb03e
29 #define PCI_DEVICE_ID_WCL	0xfd3e
30 #define PCI_DEVICE_ID_NVL	0xd71d
31 
32 #define IVPU_HW_IP_37XX 37
33 #define IVPU_HW_IP_40XX 40
34 #define IVPU_HW_IP_50XX 50
35 #define IVPU_HW_IP_60XX 60
36 
37 #define IVPU_HW_IP_REV_LNL_B0 4
38 
39 #define IVPU_HW_BTRS_MTL 1
40 #define IVPU_HW_BTRS_LNL 2
41 
42 #define IVPU_GLOBAL_CONTEXT_MMU_SSID   0
43 /* SSID 1 is used by the VPU to represent reserved context */
44 #define IVPU_RESERVED_CONTEXT_MMU_SSID 1
45 #define IVPU_USER_CONTEXT_MIN_SSID     2
46 #define IVPU_USER_CONTEXT_MAX_SSID     (IVPU_USER_CONTEXT_MIN_SSID + 63)
47 
48 #define IVPU_MIN_DB 1
49 #define IVPU_MAX_DB 255
50 
51 #define IVPU_JOB_ID_JOB_MASK		GENMASK(7, 0)
52 #define IVPU_JOB_ID_CONTEXT_MASK	GENMASK(31, 8)
53 
54 #define IVPU_NUM_PRIORITIES    4
55 #define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_PRIORITIES)
56 
57 #define IVPU_CMDQ_MIN_ID 1
58 #define IVPU_CMDQ_MAX_ID 255
59 
60 #define IVPU_PLATFORM_SILICON 0
61 #define IVPU_PLATFORM_SIMICS  2
62 #define IVPU_PLATFORM_FPGA    3
63 #define IVPU_PLATFORM_HSLE    4
64 #define IVPU_PLATFORM_INVALID 8
65 
66 #define IVPU_SCHED_MODE_AUTO -1
67 
68 #define IVPU_DBG_REG	 BIT(0)
69 #define IVPU_DBG_IRQ	 BIT(1)
70 #define IVPU_DBG_MMU	 BIT(2)
71 #define IVPU_DBG_FILE	 BIT(3)
72 #define IVPU_DBG_MISC	 BIT(4)
73 #define IVPU_DBG_FW_BOOT BIT(5)
74 #define IVPU_DBG_PM	 BIT(6)
75 #define IVPU_DBG_IPC	 BIT(7)
76 #define IVPU_DBG_BO	 BIT(8)
77 #define IVPU_DBG_JOB	 BIT(9)
78 #define IVPU_DBG_JSM	 BIT(10)
79 #define IVPU_DBG_KREF	 BIT(11)
80 #define IVPU_DBG_RPM	 BIT(12)
81 #define IVPU_DBG_MMU_MAP BIT(13)
82 
83 #define ivpu_err(vdev, fmt, ...) \
84 	drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
85 
86 #define ivpu_err_ratelimited(vdev, fmt, ...) \
87 	drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
88 
89 #define ivpu_warn(vdev, fmt, ...) \
90 	drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
91 
92 #define ivpu_warn_ratelimited(vdev, fmt, ...) \
93 	drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
94 
95 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
96 
97 #define ivpu_dbg(vdev, type, fmt, args...) do {                                \
98 	if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask))                         \
99 		dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args);          \
100 } while (0)
101 
102 #define IVPU_WA(wa_name) (vdev->wa.wa_name)
103 
104 #define IVPU_PRINT_WA(wa_name) do {					\
105 	if (IVPU_WA(wa_name))						\
106 		ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n");	\
107 } while (0)
108 
109 struct ivpu_wa_table {
110 	bool punit_disabled;
111 	bool clear_runtime_mem;
112 	bool interrupt_clear_with_0;
113 	bool disable_clock_relinquish;
114 	bool disable_d0i3_msg;
115 	bool wp0_during_power_up;
116 	bool disable_d0i2;
117 };
118 
119 struct ivpu_hw_info;
120 struct ivpu_mmu_info;
121 struct ivpu_fw_info;
122 struct ivpu_ipc_info;
123 struct ivpu_pm_info;
124 
125 struct ivpu_device {
126 	struct drm_device drm;
127 	void __iomem *regb;
128 	void __iomem *regv;
129 	u32 platform;
130 	u32 irq;
131 
132 	struct ivpu_wa_table wa;
133 	struct ivpu_hw_info *hw;
134 	struct ivpu_mmu_info *mmu;
135 	struct ivpu_fw_info *fw;
136 	struct ivpu_ipc_info *ipc;
137 	struct ivpu_pm_info *pm;
138 
139 	struct ivpu_mmu_context gctx;
140 	struct ivpu_mmu_context rctx;
141 	struct mutex context_list_lock; /* Protects user context addition/removal */
142 	struct xarray context_xa;
143 	struct xa_limit context_xa_limit;
144 
145 	struct xarray db_xa;
146 	struct xa_limit db_limit;
147 	u32 db_next;
148 
149 	struct work_struct irq_ipc_work;
150 	struct work_struct irq_dct_work;
151 	struct work_struct context_abort_work;
152 
153 	struct mutex bo_list_lock; /* Protects bo_list */
154 	struct list_head bo_list;
155 
156 	struct mutex submitted_jobs_lock; /* Protects submitted_jobs */
157 	struct xarray submitted_jobs_xa;
158 	struct ivpu_ipc_consumer job_done_consumer;
159 	atomic_t job_timeout_counter;
160 
161 	atomic64_t unique_id_counter;
162 
163 	ktime_t busy_start_ts;
164 	ktime_t busy_time;
165 
166 	struct {
167 		int boot;
168 		int jsm;
169 		int tdr;
170 		int inference;
171 		int autosuspend;
172 		int d0i3_entry_msg;
173 		int state_dump_msg;
174 	} timeout;
175 };
176 
177 /*
178  * file_priv has its own refcount (ref) that allows user space to close the fd
179  * without blocking even if VPU is still processing some jobs.
180  */
181 struct ivpu_file_priv {
182 	struct kref ref;
183 	struct ivpu_device *vdev;
184 	struct mutex lock; /* Protects cmdq */
185 	struct xarray cmdq_xa;
186 	struct ivpu_mmu_context ctx;
187 	struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */
188 	struct list_head ms_instance_list;
189 	struct ivpu_bo *ms_info_bo;
190 	struct xa_limit job_limit;
191 	u32 job_id_next;
192 	struct xa_limit cmdq_limit;
193 	u32 cmdq_id_next;
194 	bool has_mmu_faults;
195 	bool bound;
196 	bool aborted;
197 };
198 
199 extern int ivpu_dbg_mask;
200 extern u8 ivpu_pll_min_ratio;
201 extern u8 ivpu_pll_max_ratio;
202 extern int ivpu_sched_mode;
203 extern bool ivpu_disable_mmu_cont_pages;
204 extern bool ivpu_force_snoop;
205 
206 #define IVPU_TEST_MODE_FW_TEST            BIT(0)
207 #define IVPU_TEST_MODE_NULL_HW            BIT(1)
208 #define IVPU_TEST_MODE_NULL_SUBMISSION    BIT(2)
209 #define IVPU_TEST_MODE_D0I3_MSG_DISABLE   BIT(4)
210 #define IVPU_TEST_MODE_D0I3_MSG_ENABLE    BIT(5)
211 #define IVPU_TEST_MODE_MIP_DISABLE        BIT(6)
212 #define IVPU_TEST_MODE_DISABLE_TIMEOUTS   BIT(8)
213 #define IVPU_TEST_MODE_TURBO_ENABLE       BIT(9)
214 #define IVPU_TEST_MODE_TURBO_DISABLE      BIT(10)
215 #define IVPU_TEST_MODE_CLK_RELINQ_DISABLE BIT(11)
216 #define IVPU_TEST_MODE_CLK_RELINQ_ENABLE  BIT(12)
217 #define IVPU_TEST_MODE_D0I2_DISABLE       BIT(13)
218 extern int ivpu_test_mode;
219 
220 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
221 void ivpu_file_priv_put(struct ivpu_file_priv **link);
222 
223 int ivpu_boot(struct ivpu_device *vdev);
224 int ivpu_shutdown(struct ivpu_device *vdev);
225 void ivpu_prepare_for_reset(struct ivpu_device *vdev);
226 bool ivpu_is_capable(struct ivpu_device *vdev, u32 capability);
227 
228 static inline u8 ivpu_revision(struct ivpu_device *vdev)
229 {
230 	return to_pci_dev(vdev->drm.dev)->revision;
231 }
232 
233 static inline u16 ivpu_device_id(struct ivpu_device *vdev)
234 {
235 	return to_pci_dev(vdev->drm.dev)->device;
236 }
237 
238 static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev)
239 {
240 	switch (ivpu_device_id(vdev)) {
241 	case PCI_DEVICE_ID_MTL:
242 	case PCI_DEVICE_ID_ARL:
243 		return IVPU_HW_IP_37XX;
244 	case PCI_DEVICE_ID_LNL:
245 		return IVPU_HW_IP_40XX;
246 	case PCI_DEVICE_ID_PTL_P:
247 	case PCI_DEVICE_ID_WCL:
248 		return IVPU_HW_IP_50XX;
249 	case PCI_DEVICE_ID_NVL:
250 		return IVPU_HW_IP_60XX;
251 	default:
252 		dump_stack();
253 		ivpu_err(vdev, "Unknown NPU IP generation\n");
254 		return 0;
255 	}
256 }
257 
258 static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev)
259 {
260 	switch (ivpu_device_id(vdev)) {
261 	case PCI_DEVICE_ID_MTL:
262 	case PCI_DEVICE_ID_ARL:
263 		return IVPU_HW_BTRS_MTL;
264 	case PCI_DEVICE_ID_LNL:
265 	case PCI_DEVICE_ID_PTL_P:
266 	case PCI_DEVICE_ID_WCL:
267 	case PCI_DEVICE_ID_NVL:
268 		return IVPU_HW_BTRS_LNL;
269 	default:
270 		dump_stack();
271 		ivpu_err(vdev, "Unknown buttress generation\n");
272 		return 0;
273 	}
274 }
275 
276 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
277 {
278 	return container_of(dev, struct ivpu_device, drm);
279 }
280 
281 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
282 {
283 	struct xa_limit ctx_limit = vdev->context_xa_limit;
284 
285 	return (ctx_limit.max - ctx_limit.min + 1);
286 }
287 
288 static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
289 {
290 	WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
291 	return vdev->platform;
292 }
293 
294 static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
295 {
296 	return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
297 }
298 
299 static inline bool ivpu_is_simics(struct ivpu_device *vdev)
300 {
301 	return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
302 }
303 
304 static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
305 {
306 	return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA ||
307 	       ivpu_get_platform(vdev) == IVPU_PLATFORM_HSLE;
308 }
309 
310 static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev)
311 {
312 	return ivpu_force_snoop;
313 }
314 
315 #endif /* __IVPU_DRV_H__ */
316