1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2020-2023 Intel Corporation 4 */ 5 6 #ifndef __IVPU_DRV_H__ 7 #define __IVPU_DRV_H__ 8 9 #include <drm/drm_device.h> 10 #include <drm/drm_drv.h> 11 #include <drm/drm_managed.h> 12 #include <drm/drm_mm.h> 13 #include <drm/drm_print.h> 14 15 #include <linux/pci.h> 16 #include <linux/xarray.h> 17 #include <uapi/drm/ivpu_accel.h> 18 19 #include "ivpu_mmu_context.h" 20 #include "ivpu_ipc.h" 21 22 #define DRIVER_NAME "intel_vpu" 23 #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)" 24 #define DRIVER_DATE "20230117" 25 26 #define PCI_DEVICE_ID_MTL 0x7d1d 27 #define PCI_DEVICE_ID_ARL 0xad1d 28 #define PCI_DEVICE_ID_LNL 0x643e 29 30 #define IVPU_HW_37XX 37 31 #define IVPU_HW_40XX 40 32 33 #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0 34 /* SSID 1 is used by the VPU to represent reserved context */ 35 #define IVPU_RESERVED_CONTEXT_MMU_SSID 1 36 #define IVPU_USER_CONTEXT_MIN_SSID 2 37 #define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63) 38 39 #define IVPU_MIN_DB 1 40 #define IVPU_MAX_DB 255 41 42 #define IVPU_NUM_ENGINES 2 43 44 #define IVPU_PLATFORM_SILICON 0 45 #define IVPU_PLATFORM_SIMICS 2 46 #define IVPU_PLATFORM_FPGA 3 47 #define IVPU_PLATFORM_INVALID 8 48 49 #define IVPU_DBG_REG BIT(0) 50 #define IVPU_DBG_IRQ BIT(1) 51 #define IVPU_DBG_MMU BIT(2) 52 #define IVPU_DBG_FILE BIT(3) 53 #define IVPU_DBG_MISC BIT(4) 54 #define IVPU_DBG_FW_BOOT BIT(5) 55 #define IVPU_DBG_PM BIT(6) 56 #define IVPU_DBG_IPC BIT(7) 57 #define IVPU_DBG_BO BIT(8) 58 #define IVPU_DBG_JOB BIT(9) 59 #define IVPU_DBG_JSM BIT(10) 60 #define IVPU_DBG_KREF BIT(11) 61 #define IVPU_DBG_RPM BIT(12) 62 #define IVPU_DBG_MMU_MAP BIT(13) 63 64 #define ivpu_err(vdev, fmt, ...) \ 65 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 66 67 #define ivpu_err_ratelimited(vdev, fmt, ...) \ 68 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 69 70 #define ivpu_warn(vdev, fmt, ...) \ 71 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 72 73 #define ivpu_warn_ratelimited(vdev, fmt, ...) \ 74 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 75 76 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__) 77 78 #define ivpu_dbg(vdev, type, fmt, args...) do { \ 79 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \ 80 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \ 81 } while (0) 82 83 #define IVPU_WA(wa_name) (vdev->wa.wa_name) 84 85 #define IVPU_PRINT_WA(wa_name) do { \ 86 if (IVPU_WA(wa_name)) \ 87 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \ 88 } while (0) 89 90 struct ivpu_wa_table { 91 bool punit_disabled; 92 bool clear_runtime_mem; 93 bool d3hot_after_power_off; 94 bool interrupt_clear_with_0; 95 bool disable_clock_relinquish; 96 bool disable_d0i3_msg; 97 }; 98 99 struct ivpu_hw_info; 100 struct ivpu_mmu_info; 101 struct ivpu_fw_info; 102 struct ivpu_ipc_info; 103 struct ivpu_pm_info; 104 105 struct ivpu_device { 106 struct drm_device drm; 107 void __iomem *regb; 108 void __iomem *regv; 109 u32 platform; 110 u32 irq; 111 112 struct ivpu_wa_table wa; 113 struct ivpu_hw_info *hw; 114 struct ivpu_mmu_info *mmu; 115 struct ivpu_fw_info *fw; 116 struct ivpu_ipc_info *ipc; 117 struct ivpu_pm_info *pm; 118 119 struct ivpu_mmu_context gctx; 120 struct ivpu_mmu_context rctx; 121 struct mutex context_list_lock; /* Protects user context addition/removal */ 122 struct xarray context_xa; 123 struct xa_limit context_xa_limit; 124 125 struct xarray db_xa; 126 127 struct mutex bo_list_lock; /* Protects bo_list */ 128 struct list_head bo_list; 129 130 struct xarray submitted_jobs_xa; 131 struct ivpu_ipc_consumer job_done_consumer; 132 133 atomic64_t unique_id_counter; 134 135 struct { 136 int boot; 137 int jsm; 138 int tdr; 139 int reschedule_suspend; 140 int autosuspend; 141 int d0i3_entry_msg; 142 } timeout; 143 }; 144 145 /* 146 * file_priv has its own refcount (ref) that allows user space to close the fd 147 * without blocking even if VPU is still processing some jobs. 148 */ 149 struct ivpu_file_priv { 150 struct kref ref; 151 struct ivpu_device *vdev; 152 struct mutex lock; /* Protects cmdq */ 153 struct ivpu_cmdq *cmdq[IVPU_NUM_ENGINES]; 154 struct ivpu_mmu_context ctx; 155 bool has_mmu_faults; 156 bool bound; 157 }; 158 159 extern int ivpu_dbg_mask; 160 extern u8 ivpu_pll_min_ratio; 161 extern u8 ivpu_pll_max_ratio; 162 extern bool ivpu_disable_mmu_cont_pages; 163 164 #define IVPU_TEST_MODE_FW_TEST BIT(0) 165 #define IVPU_TEST_MODE_NULL_HW BIT(1) 166 #define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2) 167 #define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4) 168 #define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5) 169 extern int ivpu_test_mode; 170 171 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv); 172 void ivpu_file_priv_put(struct ivpu_file_priv **link); 173 174 int ivpu_boot(struct ivpu_device *vdev); 175 int ivpu_shutdown(struct ivpu_device *vdev); 176 void ivpu_prepare_for_reset(struct ivpu_device *vdev); 177 178 static inline u8 ivpu_revision(struct ivpu_device *vdev) 179 { 180 return to_pci_dev(vdev->drm.dev)->revision; 181 } 182 183 static inline u16 ivpu_device_id(struct ivpu_device *vdev) 184 { 185 return to_pci_dev(vdev->drm.dev)->device; 186 } 187 188 static inline int ivpu_hw_gen(struct ivpu_device *vdev) 189 { 190 switch (ivpu_device_id(vdev)) { 191 case PCI_DEVICE_ID_MTL: 192 case PCI_DEVICE_ID_ARL: 193 return IVPU_HW_37XX; 194 case PCI_DEVICE_ID_LNL: 195 return IVPU_HW_40XX; 196 default: 197 ivpu_err(vdev, "Unknown NPU device\n"); 198 return 0; 199 } 200 } 201 202 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev) 203 { 204 return container_of(dev, struct ivpu_device, drm); 205 } 206 207 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev) 208 { 209 struct xa_limit ctx_limit = vdev->context_xa_limit; 210 211 return (ctx_limit.max - ctx_limit.min + 1); 212 } 213 214 static inline u32 ivpu_get_platform(struct ivpu_device *vdev) 215 { 216 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID); 217 return vdev->platform; 218 } 219 220 static inline bool ivpu_is_silicon(struct ivpu_device *vdev) 221 { 222 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON; 223 } 224 225 static inline bool ivpu_is_simics(struct ivpu_device *vdev) 226 { 227 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS; 228 } 229 230 static inline bool ivpu_is_fpga(struct ivpu_device *vdev) 231 { 232 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA; 233 } 234 235 #endif /* __IVPU_DRV_H__ */ 236