1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2020-2024 Intel Corporation 4 */ 5 6 #ifndef __IVPU_DRV_H__ 7 #define __IVPU_DRV_H__ 8 9 #include <drm/drm_device.h> 10 #include <drm/drm_drv.h> 11 #include <drm/drm_managed.h> 12 #include <drm/drm_mm.h> 13 #include <drm/drm_print.h> 14 15 #include <linux/pci.h> 16 #include <linux/xarray.h> 17 #include <uapi/drm/ivpu_accel.h> 18 19 #include "ivpu_mmu_context.h" 20 #include "ivpu_ipc.h" 21 22 #define DRIVER_NAME "intel_vpu" 23 #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)" 24 #define DRIVER_DATE "20230117" 25 26 #define PCI_DEVICE_ID_MTL 0x7d1d 27 #define PCI_DEVICE_ID_ARL 0xad1d 28 #define PCI_DEVICE_ID_LNL 0x643e 29 30 #define IVPU_HW_IP_37XX 37 31 #define IVPU_HW_IP_40XX 40 32 #define IVPU_HW_IP_50XX 50 33 #define IVPU_HW_IP_60XX 60 34 35 #define IVPU_HW_BTRS_MTL 1 36 #define IVPU_HW_BTRS_LNL 2 37 38 #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0 39 /* SSID 1 is used by the VPU to represent reserved context */ 40 #define IVPU_RESERVED_CONTEXT_MMU_SSID 1 41 #define IVPU_USER_CONTEXT_MIN_SSID 2 42 #define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63) 43 44 #define IVPU_MIN_DB 1 45 #define IVPU_MAX_DB 255 46 47 #define IVPU_NUM_ENGINES 2 48 #define IVPU_NUM_PRIORITIES 4 49 #define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_ENGINES * IVPU_NUM_PRIORITIES) 50 51 #define IVPU_CMDQ_INDEX(engine, priority) ((engine) * IVPU_NUM_PRIORITIES + (priority)) 52 53 #define IVPU_PLATFORM_SILICON 0 54 #define IVPU_PLATFORM_SIMICS 2 55 #define IVPU_PLATFORM_FPGA 3 56 #define IVPU_PLATFORM_INVALID 8 57 58 #define IVPU_DBG_REG BIT(0) 59 #define IVPU_DBG_IRQ BIT(1) 60 #define IVPU_DBG_MMU BIT(2) 61 #define IVPU_DBG_FILE BIT(3) 62 #define IVPU_DBG_MISC BIT(4) 63 #define IVPU_DBG_FW_BOOT BIT(5) 64 #define IVPU_DBG_PM BIT(6) 65 #define IVPU_DBG_IPC BIT(7) 66 #define IVPU_DBG_BO BIT(8) 67 #define IVPU_DBG_JOB BIT(9) 68 #define IVPU_DBG_JSM BIT(10) 69 #define IVPU_DBG_KREF BIT(11) 70 #define IVPU_DBG_RPM BIT(12) 71 #define IVPU_DBG_MMU_MAP BIT(13) 72 73 #define ivpu_err(vdev, fmt, ...) \ 74 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 75 76 #define ivpu_err_ratelimited(vdev, fmt, ...) \ 77 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 78 79 #define ivpu_warn(vdev, fmt, ...) \ 80 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 81 82 #define ivpu_warn_ratelimited(vdev, fmt, ...) \ 83 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 84 85 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__) 86 87 #define ivpu_dbg(vdev, type, fmt, args...) do { \ 88 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \ 89 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \ 90 } while (0) 91 92 #define IVPU_WA(wa_name) (vdev->wa.wa_name) 93 94 #define IVPU_PRINT_WA(wa_name) do { \ 95 if (IVPU_WA(wa_name)) \ 96 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \ 97 } while (0) 98 99 struct ivpu_wa_table { 100 bool punit_disabled; 101 bool clear_runtime_mem; 102 bool interrupt_clear_with_0; 103 bool disable_clock_relinquish; 104 bool disable_d0i3_msg; 105 bool wp0_during_power_up; 106 }; 107 108 struct ivpu_hw_info; 109 struct ivpu_mmu_info; 110 struct ivpu_fw_info; 111 struct ivpu_ipc_info; 112 struct ivpu_pm_info; 113 114 struct ivpu_device { 115 struct drm_device drm; 116 void __iomem *regb; 117 void __iomem *regv; 118 u32 platform; 119 u32 irq; 120 121 struct ivpu_wa_table wa; 122 struct ivpu_hw_info *hw; 123 struct ivpu_mmu_info *mmu; 124 struct ivpu_fw_info *fw; 125 struct ivpu_ipc_info *ipc; 126 struct ivpu_pm_info *pm; 127 128 struct ivpu_mmu_context gctx; 129 struct ivpu_mmu_context rctx; 130 struct mutex context_list_lock; /* Protects user context addition/removal */ 131 struct xarray context_xa; 132 struct xa_limit context_xa_limit; 133 134 struct xarray db_xa; 135 136 struct mutex bo_list_lock; /* Protects bo_list */ 137 struct list_head bo_list; 138 139 struct xarray submitted_jobs_xa; 140 struct ivpu_ipc_consumer job_done_consumer; 141 142 atomic64_t unique_id_counter; 143 144 ktime_t busy_start_ts; 145 ktime_t busy_time; 146 147 struct { 148 int boot; 149 int jsm; 150 int tdr; 151 int reschedule_suspend; 152 int autosuspend; 153 int d0i3_entry_msg; 154 } timeout; 155 }; 156 157 /* 158 * file_priv has its own refcount (ref) that allows user space to close the fd 159 * without blocking even if VPU is still processing some jobs. 160 */ 161 struct ivpu_file_priv { 162 struct kref ref; 163 struct ivpu_device *vdev; 164 struct mutex lock; /* Protects cmdq */ 165 struct ivpu_cmdq *cmdq[IVPU_NUM_CMDQS_PER_CTX]; 166 struct ivpu_mmu_context ctx; 167 struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */ 168 struct list_head ms_instance_list; 169 struct ivpu_bo *ms_info_bo; 170 bool has_mmu_faults; 171 bool bound; 172 }; 173 174 extern int ivpu_dbg_mask; 175 extern u8 ivpu_pll_min_ratio; 176 extern u8 ivpu_pll_max_ratio; 177 extern int ivpu_sched_mode; 178 extern bool ivpu_disable_mmu_cont_pages; 179 extern bool ivpu_force_snoop; 180 181 #define IVPU_TEST_MODE_FW_TEST BIT(0) 182 #define IVPU_TEST_MODE_NULL_HW BIT(1) 183 #define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2) 184 #define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4) 185 #define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5) 186 #define IVPU_TEST_MODE_PREEMPTION_DISABLE BIT(6) 187 #define IVPU_TEST_MODE_HWS_EXTRA_EVENTS BIT(7) 188 extern int ivpu_test_mode; 189 190 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv); 191 void ivpu_file_priv_put(struct ivpu_file_priv **link); 192 193 int ivpu_boot(struct ivpu_device *vdev); 194 int ivpu_shutdown(struct ivpu_device *vdev); 195 void ivpu_prepare_for_reset(struct ivpu_device *vdev); 196 197 static inline u8 ivpu_revision(struct ivpu_device *vdev) 198 { 199 return to_pci_dev(vdev->drm.dev)->revision; 200 } 201 202 static inline u16 ivpu_device_id(struct ivpu_device *vdev) 203 { 204 return to_pci_dev(vdev->drm.dev)->device; 205 } 206 207 static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev) 208 { 209 switch (ivpu_device_id(vdev)) { 210 case PCI_DEVICE_ID_MTL: 211 case PCI_DEVICE_ID_ARL: 212 return IVPU_HW_IP_37XX; 213 case PCI_DEVICE_ID_LNL: 214 return IVPU_HW_IP_40XX; 215 default: 216 dump_stack(); 217 ivpu_err(vdev, "Unknown NPU IP generation\n"); 218 return 0; 219 } 220 } 221 222 static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev) 223 { 224 switch (ivpu_device_id(vdev)) { 225 case PCI_DEVICE_ID_MTL: 226 case PCI_DEVICE_ID_ARL: 227 return IVPU_HW_BTRS_MTL; 228 case PCI_DEVICE_ID_LNL: 229 return IVPU_HW_BTRS_LNL; 230 default: 231 dump_stack(); 232 ivpu_err(vdev, "Unknown buttress generation\n"); 233 return 0; 234 } 235 } 236 237 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev) 238 { 239 return container_of(dev, struct ivpu_device, drm); 240 } 241 242 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev) 243 { 244 struct xa_limit ctx_limit = vdev->context_xa_limit; 245 246 return (ctx_limit.max - ctx_limit.min + 1); 247 } 248 249 static inline u32 ivpu_get_platform(struct ivpu_device *vdev) 250 { 251 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID); 252 return vdev->platform; 253 } 254 255 static inline bool ivpu_is_silicon(struct ivpu_device *vdev) 256 { 257 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON; 258 } 259 260 static inline bool ivpu_is_simics(struct ivpu_device *vdev) 261 { 262 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS; 263 } 264 265 static inline bool ivpu_is_fpga(struct ivpu_device *vdev) 266 { 267 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA; 268 } 269 270 static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev) 271 { 272 return ivpu_force_snoop; 273 } 274 275 #endif /* __IVPU_DRV_H__ */ 276