xref: /linux/drivers/accel/ivpu/ivpu_drv.h (revision b4ada0618eed0fbd1b1630f73deb048c592b06a1) 
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2020-2025 Intel Corporation
4  */
5 
6 #ifndef __IVPU_DRV_H__
7 #define __IVPU_DRV_H__
8 
9 #include <drm/drm_device.h>
10 #include <drm/drm_drv.h>
11 #include <drm/drm_managed.h>
12 #include <drm/drm_mm.h>
13 #include <drm/drm_print.h>
14 
15 #include <linux/pci.h>
16 #include <linux/xarray.h>
17 #include <uapi/drm/ivpu_accel.h>
18 
19 #include "ivpu_mmu_context.h"
20 #include "ivpu_ipc.h"
21 
22 #define DRIVER_NAME "intel_vpu"
23 #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"
24 
25 #define PCI_DEVICE_ID_MTL	0x7d1d
26 #define PCI_DEVICE_ID_ARL	0xad1d
27 #define PCI_DEVICE_ID_LNL	0x643e
28 #define PCI_DEVICE_ID_PTL_P	0xb03e
29 #define PCI_DEVICE_ID_WCL	0xfd3e
30 
31 #define IVPU_HW_IP_37XX 37
32 #define IVPU_HW_IP_40XX 40
33 #define IVPU_HW_IP_50XX 50
34 #define IVPU_HW_IP_60XX 60
35 
36 #define IVPU_HW_IP_REV_LNL_B0 4
37 
38 #define IVPU_HW_BTRS_MTL 1
39 #define IVPU_HW_BTRS_LNL 2
40 
41 #define IVPU_GLOBAL_CONTEXT_MMU_SSID   0
42 /* SSID 1 is used by the VPU to represent reserved context */
43 #define IVPU_RESERVED_CONTEXT_MMU_SSID 1
44 #define IVPU_USER_CONTEXT_MIN_SSID     2
45 #define IVPU_USER_CONTEXT_MAX_SSID     (IVPU_USER_CONTEXT_MIN_SSID + 63)
46 
47 #define IVPU_MIN_DB 1
48 #define IVPU_MAX_DB 255
49 
50 #define IVPU_JOB_ID_JOB_MASK		GENMASK(7, 0)
51 #define IVPU_JOB_ID_CONTEXT_MASK	GENMASK(31, 8)
52 
53 #define IVPU_NUM_PRIORITIES    4
54 #define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_PRIORITIES)
55 
56 #define IVPU_CMDQ_MIN_ID 1
57 #define IVPU_CMDQ_MAX_ID 255
58 
59 #define IVPU_PLATFORM_SILICON 0
60 #define IVPU_PLATFORM_SIMICS  2
61 #define IVPU_PLATFORM_FPGA    3
62 #define IVPU_PLATFORM_HSLE    4
63 #define IVPU_PLATFORM_INVALID 8
64 
65 #define IVPU_SCHED_MODE_AUTO -1
66 
67 #define IVPU_DBG_REG	 BIT(0)
68 #define IVPU_DBG_IRQ	 BIT(1)
69 #define IVPU_DBG_MMU	 BIT(2)
70 #define IVPU_DBG_FILE	 BIT(3)
71 #define IVPU_DBG_MISC	 BIT(4)
72 #define IVPU_DBG_FW_BOOT BIT(5)
73 #define IVPU_DBG_PM	 BIT(6)
74 #define IVPU_DBG_IPC	 BIT(7)
75 #define IVPU_DBG_BO	 BIT(8)
76 #define IVPU_DBG_JOB	 BIT(9)
77 #define IVPU_DBG_JSM	 BIT(10)
78 #define IVPU_DBG_KREF	 BIT(11)
79 #define IVPU_DBG_RPM	 BIT(12)
80 #define IVPU_DBG_MMU_MAP BIT(13)
81 
82 #define ivpu_err(vdev, fmt, ...) \
83 	drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
84 
85 #define ivpu_err_ratelimited(vdev, fmt, ...) \
86 	drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
87 
88 #define ivpu_warn(vdev, fmt, ...) \
89 	drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
90 
91 #define ivpu_warn_ratelimited(vdev, fmt, ...) \
92 	drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
93 
94 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
95 
96 #define ivpu_dbg(vdev, type, fmt, args...) do {                                \
97 	if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask))                         \
98 		dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args);          \
99 } while (0)
100 
101 #define IVPU_WA(wa_name) (vdev->wa.wa_name)
102 
103 #define IVPU_PRINT_WA(wa_name) do {					\
104 	if (IVPU_WA(wa_name))						\
105 		ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n");	\
106 } while (0)
107 
108 struct ivpu_wa_table {
109 	bool punit_disabled;
110 	bool clear_runtime_mem;
111 	bool interrupt_clear_with_0;
112 	bool disable_clock_relinquish;
113 	bool disable_d0i3_msg;
114 	bool wp0_during_power_up;
115 	bool disable_d0i2;
116 };
117 
118 struct ivpu_hw_info;
119 struct ivpu_mmu_info;
120 struct ivpu_fw_info;
121 struct ivpu_ipc_info;
122 struct ivpu_pm_info;
123 
124 struct ivpu_device {
125 	struct drm_device drm;
126 	void __iomem *regb;
127 	void __iomem *regv;
128 	u32 platform;
129 	u32 irq;
130 
131 	struct ivpu_wa_table wa;
132 	struct ivpu_hw_info *hw;
133 	struct ivpu_mmu_info *mmu;
134 	struct ivpu_fw_info *fw;
135 	struct ivpu_ipc_info *ipc;
136 	struct ivpu_pm_info *pm;
137 
138 	struct ivpu_mmu_context gctx;
139 	struct ivpu_mmu_context rctx;
140 	struct mutex context_list_lock; /* Protects user context addition/removal */
141 	struct xarray context_xa;
142 	struct xa_limit context_xa_limit;
143 
144 	struct xarray db_xa;
145 	struct xa_limit db_limit;
146 	u32 db_next;
147 
148 	struct work_struct irq_ipc_work;
149 	struct work_struct irq_dct_work;
150 	struct work_struct context_abort_work;
151 
152 	struct mutex bo_list_lock; /* Protects bo_list */
153 	struct list_head bo_list;
154 
155 	struct mutex submitted_jobs_lock; /* Protects submitted_jobs */
156 	struct xarray submitted_jobs_xa;
157 	struct ivpu_ipc_consumer job_done_consumer;
158 	atomic_t job_timeout_counter;
159 
160 	atomic64_t unique_id_counter;
161 
162 	ktime_t busy_start_ts;
163 	ktime_t busy_time;
164 
165 	struct {
166 		int boot;
167 		int jsm;
168 		int tdr;
169 		int inference;
170 		int autosuspend;
171 		int d0i3_entry_msg;
172 		int state_dump_msg;
173 	} timeout;
174 };
175 
176 /*
177  * file_priv has its own refcount (ref) that allows user space to close the fd
178  * without blocking even if VPU is still processing some jobs.
179  */
180 struct ivpu_file_priv {
181 	struct kref ref;
182 	struct ivpu_device *vdev;
183 	struct mutex lock; /* Protects cmdq */
184 	struct xarray cmdq_xa;
185 	struct ivpu_mmu_context ctx;
186 	struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */
187 	struct list_head ms_instance_list;
188 	struct ivpu_bo *ms_info_bo;
189 	struct xa_limit job_limit;
190 	u32 job_id_next;
191 	struct xa_limit cmdq_limit;
192 	u32 cmdq_id_next;
193 	bool has_mmu_faults;
194 	bool bound;
195 	bool aborted;
196 };
197 
198 extern int ivpu_dbg_mask;
199 extern u8 ivpu_pll_min_ratio;
200 extern u8 ivpu_pll_max_ratio;
201 extern int ivpu_sched_mode;
202 extern bool ivpu_disable_mmu_cont_pages;
203 extern bool ivpu_force_snoop;
204 
205 #define IVPU_TEST_MODE_FW_TEST            BIT(0)
206 #define IVPU_TEST_MODE_NULL_HW            BIT(1)
207 #define IVPU_TEST_MODE_NULL_SUBMISSION    BIT(2)
208 #define IVPU_TEST_MODE_D0I3_MSG_DISABLE   BIT(4)
209 #define IVPU_TEST_MODE_D0I3_MSG_ENABLE    BIT(5)
210 #define IVPU_TEST_MODE_MIP_DISABLE        BIT(6)
211 #define IVPU_TEST_MODE_DISABLE_TIMEOUTS   BIT(8)
212 #define IVPU_TEST_MODE_TURBO_ENABLE       BIT(9)
213 #define IVPU_TEST_MODE_TURBO_DISABLE      BIT(10)
214 #define IVPU_TEST_MODE_CLK_RELINQ_DISABLE BIT(11)
215 #define IVPU_TEST_MODE_CLK_RELINQ_ENABLE  BIT(12)
216 #define IVPU_TEST_MODE_D0I2_DISABLE       BIT(13)
217 extern int ivpu_test_mode;
218 
219 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
220 void ivpu_file_priv_put(struct ivpu_file_priv **link);
221 
222 int ivpu_boot(struct ivpu_device *vdev);
223 int ivpu_shutdown(struct ivpu_device *vdev);
224 void ivpu_prepare_for_reset(struct ivpu_device *vdev);
225 bool ivpu_is_capable(struct ivpu_device *vdev, u32 capability);
226 
227 static inline u8 ivpu_revision(struct ivpu_device *vdev)
228 {
229 	return to_pci_dev(vdev->drm.dev)->revision;
230 }
231 
232 static inline u16 ivpu_device_id(struct ivpu_device *vdev)
233 {
234 	return to_pci_dev(vdev->drm.dev)->device;
235 }
236 
237 static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev)
238 {
239 	switch (ivpu_device_id(vdev)) {
240 	case PCI_DEVICE_ID_MTL:
241 	case PCI_DEVICE_ID_ARL:
242 		return IVPU_HW_IP_37XX;
243 	case PCI_DEVICE_ID_LNL:
244 		return IVPU_HW_IP_40XX;
245 	case PCI_DEVICE_ID_PTL_P:
246 	case PCI_DEVICE_ID_WCL:
247 		return IVPU_HW_IP_50XX;
248 	default:
249 		dump_stack();
250 		ivpu_err(vdev, "Unknown NPU IP generation\n");
251 		return 0;
252 	}
253 }
254 
255 static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev)
256 {
257 	switch (ivpu_device_id(vdev)) {
258 	case PCI_DEVICE_ID_MTL:
259 	case PCI_DEVICE_ID_ARL:
260 		return IVPU_HW_BTRS_MTL;
261 	case PCI_DEVICE_ID_LNL:
262 	case PCI_DEVICE_ID_PTL_P:
263 	case PCI_DEVICE_ID_WCL:
264 		return IVPU_HW_BTRS_LNL;
265 	default:
266 		dump_stack();
267 		ivpu_err(vdev, "Unknown buttress generation\n");
268 		return 0;
269 	}
270 }
271 
272 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
273 {
274 	return container_of(dev, struct ivpu_device, drm);
275 }
276 
277 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
278 {
279 	struct xa_limit ctx_limit = vdev->context_xa_limit;
280 
281 	return (ctx_limit.max - ctx_limit.min + 1);
282 }
283 
284 static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
285 {
286 	WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
287 	return vdev->platform;
288 }
289 
290 static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
291 {
292 	return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
293 }
294 
295 static inline bool ivpu_is_simics(struct ivpu_device *vdev)
296 {
297 	return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
298 }
299 
300 static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
301 {
302 	return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA ||
303 	       ivpu_get_platform(vdev) == IVPU_PLATFORM_HSLE;
304 }
305 
306 static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev)
307 {
308 	return ivpu_force_snoop;
309 }
310 
311 #endif /* __IVPU_DRV_H__ */
312