1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2020-2024 Intel Corporation 4 */ 5 6 #ifndef __IVPU_DRV_H__ 7 #define __IVPU_DRV_H__ 8 9 #include <drm/drm_device.h> 10 #include <drm/drm_drv.h> 11 #include <drm/drm_managed.h> 12 #include <drm/drm_mm.h> 13 #include <drm/drm_print.h> 14 15 #include <linux/pci.h> 16 #include <linux/xarray.h> 17 #include <uapi/drm/ivpu_accel.h> 18 19 #include "ivpu_mmu_context.h" 20 #include "ivpu_ipc.h" 21 22 #define DRIVER_NAME "intel_vpu" 23 #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)" 24 25 #define PCI_DEVICE_ID_MTL 0x7d1d 26 #define PCI_DEVICE_ID_ARL 0xad1d 27 #define PCI_DEVICE_ID_LNL 0x643e 28 #define PCI_DEVICE_ID_PTL_P 0xb03e 29 30 #define IVPU_HW_IP_37XX 37 31 #define IVPU_HW_IP_40XX 40 32 #define IVPU_HW_IP_50XX 50 33 #define IVPU_HW_IP_60XX 60 34 35 #define IVPU_HW_IP_REV_LNL_B0 4 36 37 #define IVPU_HW_BTRS_MTL 1 38 #define IVPU_HW_BTRS_LNL 2 39 40 #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0 41 /* SSID 1 is used by the VPU to represent reserved context */ 42 #define IVPU_RESERVED_CONTEXT_MMU_SSID 1 43 #define IVPU_USER_CONTEXT_MIN_SSID 2 44 #define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63) 45 46 #define IVPU_MIN_DB 1 47 #define IVPU_MAX_DB 255 48 49 #define IVPU_JOB_ID_JOB_MASK GENMASK(7, 0) 50 #define IVPU_JOB_ID_CONTEXT_MASK GENMASK(31, 8) 51 52 #define IVPU_NUM_PRIORITIES 4 53 #define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_PRIORITIES) 54 55 #define IVPU_CMDQ_MIN_ID 1 56 #define IVPU_CMDQ_MAX_ID 255 57 58 #define IVPU_PLATFORM_SILICON 0 59 #define IVPU_PLATFORM_SIMICS 2 60 #define IVPU_PLATFORM_FPGA 3 61 #define IVPU_PLATFORM_HSLE 4 62 #define IVPU_PLATFORM_INVALID 8 63 64 #define IVPU_SCHED_MODE_AUTO -1 65 66 #define IVPU_DBG_REG BIT(0) 67 #define IVPU_DBG_IRQ BIT(1) 68 #define IVPU_DBG_MMU BIT(2) 69 #define IVPU_DBG_FILE BIT(3) 70 #define IVPU_DBG_MISC BIT(4) 71 #define IVPU_DBG_FW_BOOT BIT(5) 72 #define IVPU_DBG_PM BIT(6) 73 #define IVPU_DBG_IPC BIT(7) 74 #define IVPU_DBG_BO BIT(8) 75 #define IVPU_DBG_JOB BIT(9) 76 #define IVPU_DBG_JSM BIT(10) 77 #define IVPU_DBG_KREF BIT(11) 78 #define IVPU_DBG_RPM BIT(12) 79 #define IVPU_DBG_MMU_MAP BIT(13) 80 81 #define ivpu_err(vdev, fmt, ...) \ 82 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 83 84 #define ivpu_err_ratelimited(vdev, fmt, ...) \ 85 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 86 87 #define ivpu_warn(vdev, fmt, ...) \ 88 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 89 90 #define ivpu_warn_ratelimited(vdev, fmt, ...) \ 91 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 92 93 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__) 94 95 #define ivpu_dbg(vdev, type, fmt, args...) do { \ 96 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \ 97 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \ 98 } while (0) 99 100 #define IVPU_WA(wa_name) (vdev->wa.wa_name) 101 102 #define IVPU_PRINT_WA(wa_name) do { \ 103 if (IVPU_WA(wa_name)) \ 104 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \ 105 } while (0) 106 107 struct ivpu_wa_table { 108 bool punit_disabled; 109 bool clear_runtime_mem; 110 bool interrupt_clear_with_0; 111 bool disable_clock_relinquish; 112 bool disable_d0i3_msg; 113 bool wp0_during_power_up; 114 bool disable_d0i2; 115 }; 116 117 struct ivpu_hw_info; 118 struct ivpu_mmu_info; 119 struct ivpu_fw_info; 120 struct ivpu_ipc_info; 121 struct ivpu_pm_info; 122 123 struct ivpu_device { 124 struct drm_device drm; 125 void __iomem *regb; 126 void __iomem *regv; 127 u32 platform; 128 u32 irq; 129 130 struct ivpu_wa_table wa; 131 struct ivpu_hw_info *hw; 132 struct ivpu_mmu_info *mmu; 133 struct ivpu_fw_info *fw; 134 struct ivpu_ipc_info *ipc; 135 struct ivpu_pm_info *pm; 136 137 struct ivpu_mmu_context gctx; 138 struct ivpu_mmu_context rctx; 139 struct mutex context_list_lock; /* Protects user context addition/removal */ 140 struct xarray context_xa; 141 struct xa_limit context_xa_limit; 142 143 struct xarray db_xa; 144 struct xa_limit db_limit; 145 u32 db_next; 146 147 struct work_struct irq_ipc_work; 148 struct work_struct irq_dct_work; 149 struct work_struct context_abort_work; 150 151 struct mutex bo_list_lock; /* Protects bo_list */ 152 struct list_head bo_list; 153 154 struct mutex submitted_jobs_lock; /* Protects submitted_jobs */ 155 struct xarray submitted_jobs_xa; 156 struct ivpu_ipc_consumer job_done_consumer; 157 atomic_t job_timeout_counter; 158 159 atomic64_t unique_id_counter; 160 161 ktime_t busy_start_ts; 162 ktime_t busy_time; 163 164 struct { 165 int boot; 166 int jsm; 167 int tdr; 168 int inference; 169 int autosuspend; 170 int d0i3_entry_msg; 171 int state_dump_msg; 172 } timeout; 173 }; 174 175 /* 176 * file_priv has its own refcount (ref) that allows user space to close the fd 177 * without blocking even if VPU is still processing some jobs. 178 */ 179 struct ivpu_file_priv { 180 struct kref ref; 181 struct ivpu_device *vdev; 182 struct mutex lock; /* Protects cmdq */ 183 struct xarray cmdq_xa; 184 struct ivpu_mmu_context ctx; 185 struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */ 186 struct list_head ms_instance_list; 187 struct ivpu_bo *ms_info_bo; 188 struct xa_limit job_limit; 189 u32 job_id_next; 190 struct xa_limit cmdq_limit; 191 u32 cmdq_id_next; 192 bool has_mmu_faults; 193 bool bound; 194 bool aborted; 195 }; 196 197 extern int ivpu_dbg_mask; 198 extern u8 ivpu_pll_min_ratio; 199 extern u8 ivpu_pll_max_ratio; 200 extern int ivpu_sched_mode; 201 extern bool ivpu_disable_mmu_cont_pages; 202 extern bool ivpu_force_snoop; 203 204 #define IVPU_TEST_MODE_FW_TEST BIT(0) 205 #define IVPU_TEST_MODE_NULL_HW BIT(1) 206 #define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2) 207 #define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4) 208 #define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5) 209 #define IVPU_TEST_MODE_MIP_DISABLE BIT(6) 210 #define IVPU_TEST_MODE_DISABLE_TIMEOUTS BIT(8) 211 #define IVPU_TEST_MODE_TURBO BIT(9) 212 #define IVPU_TEST_MODE_CLK_RELINQ_DISABLE BIT(10) 213 #define IVPU_TEST_MODE_CLK_RELINQ_ENABLE BIT(11) 214 #define IVPU_TEST_MODE_D0I2_DISABLE BIT(12) 215 extern int ivpu_test_mode; 216 217 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv); 218 void ivpu_file_priv_put(struct ivpu_file_priv **link); 219 220 int ivpu_boot(struct ivpu_device *vdev); 221 int ivpu_shutdown(struct ivpu_device *vdev); 222 void ivpu_prepare_for_reset(struct ivpu_device *vdev); 223 bool ivpu_is_capable(struct ivpu_device *vdev, u32 capability); 224 225 static inline u8 ivpu_revision(struct ivpu_device *vdev) 226 { 227 return to_pci_dev(vdev->drm.dev)->revision; 228 } 229 230 static inline u16 ivpu_device_id(struct ivpu_device *vdev) 231 { 232 return to_pci_dev(vdev->drm.dev)->device; 233 } 234 235 static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev) 236 { 237 switch (ivpu_device_id(vdev)) { 238 case PCI_DEVICE_ID_MTL: 239 case PCI_DEVICE_ID_ARL: 240 return IVPU_HW_IP_37XX; 241 case PCI_DEVICE_ID_LNL: 242 return IVPU_HW_IP_40XX; 243 case PCI_DEVICE_ID_PTL_P: 244 return IVPU_HW_IP_50XX; 245 default: 246 dump_stack(); 247 ivpu_err(vdev, "Unknown NPU IP generation\n"); 248 return 0; 249 } 250 } 251 252 static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev) 253 { 254 switch (ivpu_device_id(vdev)) { 255 case PCI_DEVICE_ID_MTL: 256 case PCI_DEVICE_ID_ARL: 257 return IVPU_HW_BTRS_MTL; 258 case PCI_DEVICE_ID_LNL: 259 case PCI_DEVICE_ID_PTL_P: 260 return IVPU_HW_BTRS_LNL; 261 default: 262 dump_stack(); 263 ivpu_err(vdev, "Unknown buttress generation\n"); 264 return 0; 265 } 266 } 267 268 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev) 269 { 270 return container_of(dev, struct ivpu_device, drm); 271 } 272 273 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev) 274 { 275 struct xa_limit ctx_limit = vdev->context_xa_limit; 276 277 return (ctx_limit.max - ctx_limit.min + 1); 278 } 279 280 static inline u32 ivpu_get_platform(struct ivpu_device *vdev) 281 { 282 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID); 283 return vdev->platform; 284 } 285 286 static inline bool ivpu_is_silicon(struct ivpu_device *vdev) 287 { 288 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON; 289 } 290 291 static inline bool ivpu_is_simics(struct ivpu_device *vdev) 292 { 293 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS; 294 } 295 296 static inline bool ivpu_is_fpga(struct ivpu_device *vdev) 297 { 298 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA || 299 ivpu_get_platform(vdev) == IVPU_PLATFORM_HSLE; 300 } 301 302 static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev) 303 { 304 return ivpu_force_snoop; 305 } 306 307 #endif /* __IVPU_DRV_H__ */ 308