xref: /linux/drivers/accel/habanalabs/include/hw_ip/mmu/mmu_general.h (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0
2e65e175bSOded Gabbay  *
3e65e175bSOded Gabbay  * Copyright 2016-2020 HabanaLabs, Ltd.
4e65e175bSOded Gabbay  * All Rights Reserved.
5e65e175bSOded Gabbay  *
6e65e175bSOded Gabbay  */
7e65e175bSOded Gabbay 
8e65e175bSOded Gabbay #ifndef INCLUDE_MMU_GENERAL_H_
9e65e175bSOded Gabbay #define INCLUDE_MMU_GENERAL_H_
10e65e175bSOded Gabbay 
11e65e175bSOded Gabbay #define PAGE_SHIFT_4KB			12
12e65e175bSOded Gabbay #define PAGE_SHIFT_64KB			16
13e65e175bSOded Gabbay #define PAGE_SHIFT_2MB			21
14e65e175bSOded Gabbay #define PAGE_SHIFT_16MB			24
15e65e175bSOded Gabbay #define PAGE_SHIFT_64MB			26
16e65e175bSOded Gabbay #define PAGE_SHIFT_1GB			30
17e65e175bSOded Gabbay #define PAGE_SIZE_4KB			_BITUL(PAGE_SHIFT_4KB)
18e65e175bSOded Gabbay #define PAGE_SIZE_64KB			_BITUL(PAGE_SHIFT_64KB)
19e65e175bSOded Gabbay #define PAGE_SIZE_2MB			_BITUL(PAGE_SHIFT_2MB)
20e65e175bSOded Gabbay #define PAGE_SIZE_16MB			_BITUL(PAGE_SHIFT_16MB)
21e65e175bSOded Gabbay #define PAGE_SIZE_64MB			_BITUL(PAGE_SHIFT_64MB)
22e65e175bSOded Gabbay #define PAGE_SIZE_1GB			_BITUL(PAGE_SHIFT_1GB)
23e65e175bSOded Gabbay 
24e65e175bSOded Gabbay #define PAGE_PRESENT_MASK		0x0000000000001ull
25e65e175bSOded Gabbay #define SWAP_OUT_MASK			0x0000000000004ull
26e65e175bSOded Gabbay #define LAST_MASK			0x0000000000800ull
27e65e175bSOded Gabbay #define FLAGS_MASK			0x0000000000FFFull
28e65e175bSOded Gabbay 
29*f728c17fSFarah Kassabri #define MMU_ARCH_3_HOPS			3
30*f728c17fSFarah Kassabri #define MMU_ARCH_4_HOPS			4
31e65e175bSOded Gabbay #define MMU_ARCH_5_HOPS			5
32e65e175bSOded Gabbay #define MMU_ARCH_6_HOPS			6
33e65e175bSOded Gabbay 
34e65e175bSOded Gabbay #define HOP_PHYS_ADDR_MASK		(~FLAGS_MASK)
35e65e175bSOded Gabbay 
36e65e175bSOded Gabbay #define HL_PTE_SIZE			sizeof(u64)
37e65e175bSOded Gabbay 
38e65e175bSOded Gabbay /* definitions for HOP with 512 PTE entries */
39e65e175bSOded Gabbay #define HOP_PTE_ENTRIES_512		512
40e65e175bSOded Gabbay #define HOP_TABLE_SIZE_512_PTE		(HOP_PTE_ENTRIES_512 * HL_PTE_SIZE)
41e65e175bSOded Gabbay #define HOP0_512_PTE_TABLES_TOTAL_SIZE	(HOP_TABLE_SIZE_512_PTE * MAX_ASID)
42e65e175bSOded Gabbay 
43e65e175bSOded Gabbay #define MMU_HOP0_PA43_12_SHIFT		12
44e65e175bSOded Gabbay #define MMU_HOP0_PA49_44_SHIFT		(12 + 32)
45e65e175bSOded Gabbay #define MMU_HOP0_PA63_44_SHIFT		(12 + 32)
46e65e175bSOded Gabbay 
47e65e175bSOded Gabbay #define MMU_CONFIG_TIMEOUT_USEC		2000 /* 2 ms */
48e65e175bSOded Gabbay 
49e65e175bSOded Gabbay enum mmu_hop_num {
50e65e175bSOded Gabbay 	MMU_HOP0,
51e65e175bSOded Gabbay 	MMU_HOP1,
52e65e175bSOded Gabbay 	MMU_HOP2,
53e65e175bSOded Gabbay 	MMU_HOP3,
54e65e175bSOded Gabbay 	MMU_HOP4,
55e65e175bSOded Gabbay 	MMU_HOP5,
56e65e175bSOded Gabbay 	MMU_HOP_MAX,
57e65e175bSOded Gabbay };
58e65e175bSOded Gabbay 
59e65e175bSOded Gabbay #endif /* INCLUDE_MMU_GENERAL_H_ */
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