1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef GAUDI2_REG_MAP_H_ 9 #define GAUDI2_REG_MAP_H_ 10 11 /* 12 * PSOC scratch-pad registers 13 */ 14 #define mmHW_STATE mmCPU_IF_KMD_HW_DIRTY_STATUS 15 #define mmPID_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 16 #define mmARM_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 17 #define mmGIC_TPC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 18 #define mmGIC_MME_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 19 #define mmGIC_DMA_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 20 #define mmGIC_ROT_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 21 #define mmGIC_NIC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 22 #define mmGIC_DMA_CR_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 23 #define mmGIC_HOST_PI_UPD_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 24 #define mmGIC_HOST_HALT_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 25 #define mmGIC_HOST_INTS_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 26 #define mmGIC_HOST_SOFT_RST_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 27 #define mmCPU_RST_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 28 /* 29 * Single scratchpad register used for all ARCs to notify dccm queue full event to FW. 30 * So a new event would overwrite any unhandled previous event. In other words, incase 31 * of multiple events before previous ones are handled, last one would be considered. 32 */ 33 #define mmENGINE_ARC_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 34 #define mmPID_CFG_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 35 #define mmGIC_RAZWI_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 36 #define mmCPU_BOOT_DEV_STS0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 37 #define mmCPU_BOOT_DEV_STS1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 38 #define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 39 #define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 40 #define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 41 #define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 42 #define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 43 #define mmPPBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 44 #define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 45 #define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 46 #define mmRST_SRC mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0 47 #define mmCOLD_RST_DATA mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 48 #define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 49 #define mmPID_CMD_REQ_REG mmPSOC_PID_PID_CMD_0 50 #define mmPID_CMD_REQ_REG_HI mmPSOC_PID_PID_CMD_1 51 #define mmPID_CMD_RSP_REG mmPSOC_PID_PID_CMD_2 52 #define mmPID_CMD_RSP_REG_HI mmPSOC_PID_PID_CMD_3 53 #define mmPID_CMD_TELEMETRY_REG_0 mmPSOC_PID_PID_CMD_4 54 #define mmPID_CMD_TELEMETRY_REG_0_HI mmPSOC_PID_PID_CMD_5 55 #define mmPID_CMD_TELEMETRY_REG_1 mmPSOC_PID_PID_CMD_6 56 #define mmPID_CMD_TELEMETRY_REG_1_HI mmPSOC_PID_PID_CMD_7 57 #define mmWD_GPIO_OUTSET_REG mmPSOC_GPIO3_OUTENSET 58 #define mmWD_GPIO_DATAOUT_REG mmPSOC_GPIO3_DATAOUT 59 #define mmSTM_PROFILER_SPE_REG mmPSOC_STM_STMSPER 60 61 #endif /* GAUDI2_REG_MAP_H_ */ 62