xref: /linux/drivers/accel/habanalabs/include/gaudi2/gaudi2_packets.h (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0)
1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 #ifndef GAUDI2_PACKETS_H
9 #define GAUDI2_PACKETS_H
10 
11 #include <linux/types.h>
12 
13 #define PACKET_HEADER_PACKET_ID_SHIFT		56
14 #define PACKET_HEADER_PACKET_ID_MASK		0x1F00000000000000ull
15 
16 enum packet_id {
17 	PACKET_WREG_32 = 0x1,
18 	PACKET_WREG_BULK = 0x2,
19 	PACKET_MSG_LONG = 0x3,
20 	PACKET_MSG_SHORT = 0x4,
21 	PACKET_CP_DMA = 0x5,
22 	PACKET_REPEAT = 0x6,
23 	PACKET_MSG_PROT = 0x7,
24 	PACKET_FENCE = 0x8,
25 	PACKET_LIN_DMA = 0x9,
26 	PACKET_NOP = 0xA,
27 	PACKET_STOP = 0xB,
28 	PACKET_ARB_POINT = 0xC,
29 	PACKET_WAIT = 0xD,
30 	PACKET_CB_LIST = 0xE,
31 	PACKET_LOAD_AND_EXE = 0xF,
32 	PACKET_WRITE_ARC_STREAM = 0x10,
33 	PACKET_LAST_READ_FROM_ARC = 0x11,
34 	PACKET_WREG_64_SHORT = 0x12,
35 	PACKET_WREG_64_LONG = 0x13,
36 	MAX_PACKET_ID = (PACKET_HEADER_PACKET_ID_MASK >>
37 				PACKET_HEADER_PACKET_ID_SHIFT) + 1
38 };
39 
40 #define GAUDI2_PKT_CTL_OPCODE_SHIFT	24
41 #define GAUDI2_PKT_CTL_OPCODE_MASK	0x1F000000
42 
43 #define GAUDI2_PKT_CTL_EB_SHIFT		29
44 #define GAUDI2_PKT_CTL_EB_MASK		0x20000000
45 
46 #define GAUDI2_PKT_CTL_RB_SHIFT		30
47 #define GAUDI2_PKT_CTL_RB_MASK		0x40000000
48 
49 #define GAUDI2_PKT_CTL_MB_SHIFT		31
50 #define GAUDI2_PKT_CTL_MB_MASK		0x80000000
51 
52 /* All packets have, at least, an 8-byte header, which contains
53  * the packet type. The kernel driver uses the packet header for packet
54  * validation and to perform any necessary required preparation before
55  * sending them off to the hardware.
56  */
57 struct gaudi2_packet {
58 	__le64 header;
59 	/* The rest of the packet data follows. Use the corresponding
60 	 * packet_XXX struct to deference the data, based on packet type
61 	 */
62 	u8 contents[];
63 };
64 
65 struct packet_nop {
66 	__le32 reserved;
67 	__le32 ctl;
68 };
69 
70 struct packet_stop {
71 	__le32 reserved;
72 	__le32 ctl;
73 };
74 
75 struct packet_wreg32 {
76 	__le32 value;
77 	__le32 ctl;
78 };
79 
80 struct packet_wreg_bulk {
81 	__le32 size64;
82 	__le32 ctl;
83 	__le64 values[]; /* data starts here */
84 };
85 
86 struct packet_msg_long {
87 	__le32 value;
88 	__le32 ctl;
89 	__le64 addr;
90 };
91 
92 #define GAUDI2_PKT_SHORT_VAL_SOB_SYNC_VAL_SHIFT	0
93 #define GAUDI2_PKT_SHORT_VAL_SOB_SYNC_VAL_MASK	0x00007FFF
94 
95 #define GAUDI2_PKT_SHORT_VAL_SOB_MOD_SHIFT	31
96 #define GAUDI2_PKT_SHORT_VAL_SOB_MOD_MASK	0x80000000
97 
98 #define GAUDI2_PKT_SHORT_VAL_MON_SYNC_GID_SHIFT	0
99 #define GAUDI2_PKT_SHORT_VAL_MON_SYNC_GID_MASK	0x000000FF
100 
101 #define GAUDI2_PKT_SHORT_VAL_MON_MASK_SHIFT	8
102 #define GAUDI2_PKT_SHORT_VAL_MON_MASK_MASK	0x0000FF00
103 
104 #define GAUDI2_PKT_SHORT_VAL_MON_MODE_SHIFT	16
105 #define GAUDI2_PKT_SHORT_VAL_MON_MODE_MASK	0x00010000
106 
107 #define GAUDI2_PKT_SHORT_VAL_MON_SYNC_VAL_SHIFT	17
108 #define GAUDI2_PKT_SHORT_VAL_MON_SYNC_VAL_MASK	0xFFFE0000
109 
110 #define GAUDI2_PKT_SHORT_CTL_ADDR_SHIFT		0
111 #define GAUDI2_PKT_SHORT_CTL_ADDR_MASK		0x0000FFFF
112 
113 #define GAUDI2_PKT_SHORT_CTL_BASE_SHIFT		22
114 #define GAUDI2_PKT_SHORT_CTL_BASE_MASK		0x00C00000
115 
116 struct packet_msg_short {
117 	__le32 value;
118 	__le32 ctl;
119 };
120 
121 struct packet_msg_prot {
122 	__le32 value;
123 	__le32 ctl;
124 	__le64 addr;
125 };
126 
127 #define GAUDI2_PKT_FENCE_CFG_DEC_VAL_SHIFT	0
128 #define GAUDI2_PKT_FENCE_CFG_DEC_VAL_MASK	0x0000000F
129 
130 #define GAUDI2_PKT_FENCE_CFG_TARGET_VAL_SHIFT	16
131 #define GAUDI2_PKT_FENCE_CFG_TARGET_VAL_MASK	0x00FF0000
132 
133 #define GAUDI2_PKT_FENCE_CFG_ID_SHIFT		30
134 #define GAUDI2_PKT_FENCE_CFG_ID_MASK		0xC0000000
135 
136 #define GAUDI2_PKT_FENCE_CTL_PRED_SHIFT		0
137 #define GAUDI2_PKT_FENCE_CTL_PRED_MASK		0x0000001F
138 
139 struct packet_fence {
140 	__le32 cfg;
141 	__le32 ctl;
142 };
143 
144 #define GAUDI2_PKT_LIN_DMA_CTL_WRCOMP_SHIFT	0
145 #define GAUDI2_PKT_LIN_DMA_CTL_WRCOMP_MASK	0x00000001
146 
147 #define GAUDI2_PKT_LIN_DMA_CTL_ENDIAN_SHIFT	1
148 #define GAUDI2_PKT_LIN_DMA_CTL_ENDIAN_MASK	0x00000006
149 
150 #define GAUDI2_PKT_LIN_DMA_CTL_MEMSET_SHIFT	4
151 #define GAUDI2_PKT_LIN_DMA_CTL_MEMSET_MASK	0x00000010
152 
153 #define GAUDI2_PKT_LIN_DMA_CTL_CONTEXT_ID_SHIFT	8
154 #define GAUDI2_PKT_LIN_DMA_CTL_CONTEXT_ID_MASK	0x00FFFF00
155 
156 struct packet_lin_dma {
157 	__le32 tsize;
158 	__le32 ctl;
159 	__le64 src_addr;
160 	__le64 dst_addr;
161 };
162 
163 struct packet_arb_point {
164 	__le32 cfg;
165 	__le32 ctl;
166 };
167 
168 struct packet_repeat {
169 	__le32 cfg;
170 	__le32 ctl;
171 };
172 
173 struct packet_wait {
174 	__le32 cfg;
175 	__le32 ctl;
176 };
177 
178 struct packet_cb_list {
179 	__le32 reserved;
180 	__le32 ctl;
181 	__le64 index_addr;
182 	__le64 table_addr;
183 };
184 
185 struct packet_load_and_exe {
186 	__le32 cfg;
187 	__le32 ctl;
188 	__le64 src_addr;
189 };
190 
191 struct packet_cp_dma {
192 	__le32 tsize;
193 	__le32 ctl;
194 	__le64 src_addr;
195 };
196 
197 #endif /* GAUDI2_PACKETS_H */
198