1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2019-2021 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef GAUDI2_FW_IF_H 9 #define GAUDI2_FW_IF_H 10 11 #define GAUDI2_EVENT_QUEUE_MSIX_IDX 0 12 13 #define UBOOT_FW_OFFSET 0x100000 /* 1MB in SRAM */ 14 #define LINUX_FW_OFFSET 0x800000 /* 8BM in DDR */ 15 16 #define GAUDI2_PLL_FREQ_LOW 200000000 /* 200 MHz */ 17 18 #define GAUDI2_SP_SRAM_BASE_ADDR 0x27FE0000 19 #define GAUDI2_MAILBOX_BASE_ADDR 0x27FE1800 20 21 #define GAUDI2_NUM_MME 4 22 23 #define NUM_OF_GPIOS_PER_PORT 16 24 #define GAUDI2_WD_GPIO (62 % NUM_OF_GPIOS_PER_PORT) 25 26 #define GAUDI2_ARCPID_TX_MB_SIZE 0x1000 27 #define GAUDI2_ARCPID_RX_MB_SIZE 0x400 28 #define GAUDI2_ARM_TX_MB_SIZE 0x400 29 #define GAUDI2_ARM_RX_MB_SIZE 0x1800 30 31 #define GAUDI2_DCCM_BASE_ADDR 0x27020000 32 33 #define GAUDI2_ARM_TX_MB_ADDR GAUDI2_MAILBOX_BASE_ADDR 34 35 #define GAUDI2_ARM_RX_MB_ADDR (GAUDI2_ARM_TX_MB_ADDR + \ 36 GAUDI2_ARM_TX_MB_SIZE) 37 38 #define GAUDI2_ARCPID_TX_MB_ADDR (GAUDI2_ARM_RX_MB_ADDR + GAUDI2_ARM_RX_MB_SIZE) 39 40 #define GAUDI2_ARCPID_RX_MB_ADDR (GAUDI2_ARCPID_TX_MB_ADDR + GAUDI2_ARCPID_TX_MB_SIZE) 41 42 #define GAUDI2_ARM_TX_MB_OFFSET (GAUDI2_ARM_TX_MB_ADDR - \ 43 GAUDI2_SP_SRAM_BASE_ADDR) 44 45 #define GAUDI2_ARM_RX_MB_OFFSET (GAUDI2_ARM_RX_MB_ADDR - \ 46 GAUDI2_SP_SRAM_BASE_ADDR) 47 48 enum gaudi2_fw_status { 49 GAUDI2_PID_STATUS_UP = 0x1, /* PID on ARC0 is up */ 50 GAUDI2_ARM_STATUS_UP = 0x2, /* ARM Linux Boot complete */ 51 GAUDI2_MGMT_STATUS_UP = 0x3, /* ARC1 Mgmt is up */ 52 GAUDI2_STATUS_LAST = 0xFF 53 }; 54 55 struct gaudi2_cold_rst_data { 56 union { 57 struct { 58 u32 recovery_flag: 1; 59 u32 validation_flag: 1; 60 u32 efuse_read_flag: 1; 61 u32 spsram_init_done : 1; 62 u32 fake_security_enable : 1; 63 u32 fake_sig_validation_en : 1; 64 u32 bist_skip_enable : 1; 65 u32 reserved1 : 1; 66 u32 fake_bis_compliant : 1; 67 u32 wd_rst_cause_arm : 1; 68 u32 wd_rst_cause_arcpid : 1; 69 u32 reserved : 21; 70 }; 71 __le32 data; 72 }; 73 }; 74 75 enum gaudi2_rst_src { 76 HL_COLD_RST = 1, 77 HL_MANUAL_RST = 2, 78 HL_PRSTN_RST = 4, 79 HL_SOFT_RST = 8, 80 HL_WD_RST = 16, 81 HL_FW_ALL_RST = 32, 82 HL_SW_ALL_RST = 64, 83 HL_FLR_RST = 128, 84 HL_ECC_DERR_RST = 256 85 }; 86 87 struct gaudi2_redundancy_ctx { 88 __le32 redundant_hbm; 89 __le32 redundant_edma; 90 __le32 redundant_tpc; 91 __le32 redundant_vdec; 92 __le64 hbm_mask; 93 __le64 edma_mask; 94 __le64 tpc_mask; 95 __le64 vdec_mask; 96 __le64 mme_mask; 97 __le64 nic_mask; 98 __le64 rtr_mask; 99 __le64 hmmu_hif_iso; 100 __le64 xbar_edge_iso; 101 __le64 hmmu_hif_mask; 102 __le64 xbar_edge_mask; 103 __u8 mme_pe_iso[GAUDI2_NUM_MME]; 104 __le32 full_hbm_mode; /* true on full (non binning hbm)*/ 105 } __packed; 106 107 #endif /* GAUDI2_FW_IF_H */ 108