1 // SPDX-License-Identifier: GPL-2.0 2 3 /* 4 * Copyright 2016-2022 HabanaLabs, Ltd. 5 * All Rights Reserved. 6 */ 7 8 #include "goyaP.h" 9 #include "../include/hw_ip/mmu/mmu_general.h" 10 #include "../include/hw_ip/mmu/mmu_v1_0.h" 11 #include "../include/goya/asic_reg/goya_masks.h" 12 #include "../include/goya/goya_reg_map.h" 13 14 #include <linux/pci.h> 15 #include <linux/hwmon.h> 16 #include <linux/iommu.h> 17 #include <linux/seq_file.h> 18 19 /* 20 * GOYA security scheme: 21 * 22 * 1. Host is protected by: 23 * - Range registers (When MMU is enabled, DMA RR does NOT protect host) 24 * - MMU 25 * 26 * 2. DRAM is protected by: 27 * - Range registers (protect the first 512MB) 28 * - MMU (isolation between users) 29 * 30 * 3. Configuration is protected by: 31 * - Range registers 32 * - Protection bits 33 * 34 * When MMU is disabled: 35 * 36 * QMAN DMA: PQ, CQ, CP, DMA are secured. 37 * PQ, CB and the data are on the host. 38 * 39 * QMAN TPC/MME: 40 * PQ, CQ and CP are not secured. 41 * PQ, CB and the data are on the SRAM/DRAM. 42 * 43 * Since QMAN DMA is secured, the driver is parsing the DMA CB: 44 * - checks DMA pointer 45 * - WREG, MSG_PROT are not allowed. 46 * - MSG_LONG/SHORT are allowed. 47 * 48 * A read/write transaction by the QMAN to a protected area will succeed if 49 * and only if the QMAN's CP is secured and MSG_PROT is used 50 * 51 * 52 * When MMU is enabled: 53 * 54 * QMAN DMA: PQ, CQ and CP are secured. 55 * MMU is set to bypass on the Secure props register of the QMAN. 56 * The reasons we don't enable MMU for PQ, CQ and CP are: 57 * - PQ entry is in kernel address space and the driver doesn't map it. 58 * - CP writes to MSIX register and to kernel address space (completion 59 * queue). 60 * 61 * DMA is not secured but because CP is secured, the driver still needs to parse 62 * the CB, but doesn't need to check the DMA addresses. 63 * 64 * For QMAN DMA 0, DMA is also secured because only the driver uses this DMA and 65 * the driver doesn't map memory in MMU. 66 * 67 * QMAN TPC/MME: PQ, CQ and CP aren't secured (no change from MMU disabled mode) 68 * 69 * DMA RR does NOT protect host because DMA is not secured 70 * 71 */ 72 73 #define GOYA_BOOT_FIT_FILE "habanalabs/goya/goya-boot-fit.itb" 74 #define GOYA_LINUX_FW_FILE "habanalabs/goya/goya-fit.itb" 75 76 #define GOYA_MMU_REGS_NUM 63 77 78 #define GOYA_DMA_POOL_BLK_SIZE 0x100 /* 256 bytes */ 79 80 #define GOYA_RESET_TIMEOUT_MSEC 500 /* 500ms */ 81 #define GOYA_PLDM_RESET_TIMEOUT_MSEC 20000 /* 20s */ 82 #define GOYA_RESET_WAIT_MSEC 1 /* 1ms */ 83 #define GOYA_CPU_RESET_WAIT_MSEC 100 /* 100ms */ 84 #define GOYA_PLDM_RESET_WAIT_MSEC 1000 /* 1s */ 85 #define GOYA_TEST_QUEUE_WAIT_USEC 100000 /* 100ms */ 86 #define GOYA_PLDM_MMU_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 100) 87 #define GOYA_PLDM_QMAN0_TIMEOUT_USEC (HL_DEVICE_TIMEOUT_USEC * 30) 88 #define GOYA_BOOT_FIT_REQ_TIMEOUT_USEC 1000000 /* 1s */ 89 #define GOYA_MSG_TO_CPU_TIMEOUT_USEC 4000000 /* 4s */ 90 #define GOYA_WAIT_FOR_BL_TIMEOUT_USEC 15000000 /* 15s */ 91 92 #define GOYA_QMAN0_FENCE_VAL 0xD169B243 93 94 #define GOYA_MAX_STRING_LEN 20 95 96 #define GOYA_CB_POOL_CB_CNT 512 97 #define GOYA_CB_POOL_CB_SIZE 0x20000 /* 128KB */ 98 99 #define IS_QM_IDLE(engine, qm_glbl_sts0) \ 100 (((qm_glbl_sts0) & engine##_QM_IDLE_MASK) == engine##_QM_IDLE_MASK) 101 #define IS_DMA_QM_IDLE(qm_glbl_sts0) IS_QM_IDLE(DMA, qm_glbl_sts0) 102 #define IS_TPC_QM_IDLE(qm_glbl_sts0) IS_QM_IDLE(TPC, qm_glbl_sts0) 103 #define IS_MME_QM_IDLE(qm_glbl_sts0) IS_QM_IDLE(MME, qm_glbl_sts0) 104 105 #define IS_CMDQ_IDLE(engine, cmdq_glbl_sts0) \ 106 (((cmdq_glbl_sts0) & engine##_CMDQ_IDLE_MASK) == \ 107 engine##_CMDQ_IDLE_MASK) 108 #define IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) \ 109 IS_CMDQ_IDLE(TPC, cmdq_glbl_sts0) 110 #define IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) \ 111 IS_CMDQ_IDLE(MME, cmdq_glbl_sts0) 112 113 #define IS_DMA_IDLE(dma_core_sts0) \ 114 !((dma_core_sts0) & DMA_CH_0_STS0_DMA_BUSY_MASK) 115 116 #define IS_TPC_IDLE(tpc_cfg_sts) \ 117 (((tpc_cfg_sts) & TPC_CFG_IDLE_MASK) == TPC_CFG_IDLE_MASK) 118 119 #define IS_MME_IDLE(mme_arch_sts) \ 120 (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK) 121 122 static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = { 123 "goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3", 124 "goya cq 4", "goya cpu eq" 125 }; 126 127 static u16 goya_packet_sizes[MAX_PACKET_ID] = { 128 [PACKET_WREG_32] = sizeof(struct packet_wreg32), 129 [PACKET_WREG_BULK] = sizeof(struct packet_wreg_bulk), 130 [PACKET_MSG_LONG] = sizeof(struct packet_msg_long), 131 [PACKET_MSG_SHORT] = sizeof(struct packet_msg_short), 132 [PACKET_CP_DMA] = sizeof(struct packet_cp_dma), 133 [PACKET_MSG_PROT] = sizeof(struct packet_msg_prot), 134 [PACKET_FENCE] = sizeof(struct packet_fence), 135 [PACKET_LIN_DMA] = sizeof(struct packet_lin_dma), 136 [PACKET_NOP] = sizeof(struct packet_nop), 137 [PACKET_STOP] = sizeof(struct packet_stop) 138 }; 139 140 static inline bool validate_packet_id(enum packet_id id) 141 { 142 switch (id) { 143 case PACKET_WREG_32: 144 case PACKET_WREG_BULK: 145 case PACKET_MSG_LONG: 146 case PACKET_MSG_SHORT: 147 case PACKET_CP_DMA: 148 case PACKET_MSG_PROT: 149 case PACKET_FENCE: 150 case PACKET_LIN_DMA: 151 case PACKET_NOP: 152 case PACKET_STOP: 153 return true; 154 default: 155 return false; 156 } 157 } 158 159 static u64 goya_mmu_regs[GOYA_MMU_REGS_NUM] = { 160 mmDMA_QM_0_GLBL_NON_SECURE_PROPS, 161 mmDMA_QM_1_GLBL_NON_SECURE_PROPS, 162 mmDMA_QM_2_GLBL_NON_SECURE_PROPS, 163 mmDMA_QM_3_GLBL_NON_SECURE_PROPS, 164 mmDMA_QM_4_GLBL_NON_SECURE_PROPS, 165 mmTPC0_QM_GLBL_SECURE_PROPS, 166 mmTPC0_QM_GLBL_NON_SECURE_PROPS, 167 mmTPC0_CMDQ_GLBL_SECURE_PROPS, 168 mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS, 169 mmTPC0_CFG_ARUSER, 170 mmTPC0_CFG_AWUSER, 171 mmTPC1_QM_GLBL_SECURE_PROPS, 172 mmTPC1_QM_GLBL_NON_SECURE_PROPS, 173 mmTPC1_CMDQ_GLBL_SECURE_PROPS, 174 mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS, 175 mmTPC1_CFG_ARUSER, 176 mmTPC1_CFG_AWUSER, 177 mmTPC2_QM_GLBL_SECURE_PROPS, 178 mmTPC2_QM_GLBL_NON_SECURE_PROPS, 179 mmTPC2_CMDQ_GLBL_SECURE_PROPS, 180 mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS, 181 mmTPC2_CFG_ARUSER, 182 mmTPC2_CFG_AWUSER, 183 mmTPC3_QM_GLBL_SECURE_PROPS, 184 mmTPC3_QM_GLBL_NON_SECURE_PROPS, 185 mmTPC3_CMDQ_GLBL_SECURE_PROPS, 186 mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS, 187 mmTPC3_CFG_ARUSER, 188 mmTPC3_CFG_AWUSER, 189 mmTPC4_QM_GLBL_SECURE_PROPS, 190 mmTPC4_QM_GLBL_NON_SECURE_PROPS, 191 mmTPC4_CMDQ_GLBL_SECURE_PROPS, 192 mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS, 193 mmTPC4_CFG_ARUSER, 194 mmTPC4_CFG_AWUSER, 195 mmTPC5_QM_GLBL_SECURE_PROPS, 196 mmTPC5_QM_GLBL_NON_SECURE_PROPS, 197 mmTPC5_CMDQ_GLBL_SECURE_PROPS, 198 mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS, 199 mmTPC5_CFG_ARUSER, 200 mmTPC5_CFG_AWUSER, 201 mmTPC6_QM_GLBL_SECURE_PROPS, 202 mmTPC6_QM_GLBL_NON_SECURE_PROPS, 203 mmTPC6_CMDQ_GLBL_SECURE_PROPS, 204 mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS, 205 mmTPC6_CFG_ARUSER, 206 mmTPC6_CFG_AWUSER, 207 mmTPC7_QM_GLBL_SECURE_PROPS, 208 mmTPC7_QM_GLBL_NON_SECURE_PROPS, 209 mmTPC7_CMDQ_GLBL_SECURE_PROPS, 210 mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS, 211 mmTPC7_CFG_ARUSER, 212 mmTPC7_CFG_AWUSER, 213 mmMME_QM_GLBL_SECURE_PROPS, 214 mmMME_QM_GLBL_NON_SECURE_PROPS, 215 mmMME_CMDQ_GLBL_SECURE_PROPS, 216 mmMME_CMDQ_GLBL_NON_SECURE_PROPS, 217 mmMME_SBA_CONTROL_DATA, 218 mmMME_SBB_CONTROL_DATA, 219 mmMME_SBC_CONTROL_DATA, 220 mmMME_WBC_CONTROL_DATA, 221 mmPCIE_WRAP_PSOC_ARUSER, 222 mmPCIE_WRAP_PSOC_AWUSER 223 }; 224 225 static u32 goya_all_events[] = { 226 GOYA_ASYNC_EVENT_ID_PCIE_IF, 227 GOYA_ASYNC_EVENT_ID_TPC0_ECC, 228 GOYA_ASYNC_EVENT_ID_TPC1_ECC, 229 GOYA_ASYNC_EVENT_ID_TPC2_ECC, 230 GOYA_ASYNC_EVENT_ID_TPC3_ECC, 231 GOYA_ASYNC_EVENT_ID_TPC4_ECC, 232 GOYA_ASYNC_EVENT_ID_TPC5_ECC, 233 GOYA_ASYNC_EVENT_ID_TPC6_ECC, 234 GOYA_ASYNC_EVENT_ID_TPC7_ECC, 235 GOYA_ASYNC_EVENT_ID_MME_ECC, 236 GOYA_ASYNC_EVENT_ID_MME_ECC_EXT, 237 GOYA_ASYNC_EVENT_ID_MMU_ECC, 238 GOYA_ASYNC_EVENT_ID_DMA_MACRO, 239 GOYA_ASYNC_EVENT_ID_DMA_ECC, 240 GOYA_ASYNC_EVENT_ID_CPU_IF_ECC, 241 GOYA_ASYNC_EVENT_ID_PSOC_MEM, 242 GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT, 243 GOYA_ASYNC_EVENT_ID_SRAM0, 244 GOYA_ASYNC_EVENT_ID_SRAM1, 245 GOYA_ASYNC_EVENT_ID_SRAM2, 246 GOYA_ASYNC_EVENT_ID_SRAM3, 247 GOYA_ASYNC_EVENT_ID_SRAM4, 248 GOYA_ASYNC_EVENT_ID_SRAM5, 249 GOYA_ASYNC_EVENT_ID_SRAM6, 250 GOYA_ASYNC_EVENT_ID_SRAM7, 251 GOYA_ASYNC_EVENT_ID_SRAM8, 252 GOYA_ASYNC_EVENT_ID_SRAM9, 253 GOYA_ASYNC_EVENT_ID_SRAM10, 254 GOYA_ASYNC_EVENT_ID_SRAM11, 255 GOYA_ASYNC_EVENT_ID_SRAM12, 256 GOYA_ASYNC_EVENT_ID_SRAM13, 257 GOYA_ASYNC_EVENT_ID_SRAM14, 258 GOYA_ASYNC_EVENT_ID_SRAM15, 259 GOYA_ASYNC_EVENT_ID_SRAM16, 260 GOYA_ASYNC_EVENT_ID_SRAM17, 261 GOYA_ASYNC_EVENT_ID_SRAM18, 262 GOYA_ASYNC_EVENT_ID_SRAM19, 263 GOYA_ASYNC_EVENT_ID_SRAM20, 264 GOYA_ASYNC_EVENT_ID_SRAM21, 265 GOYA_ASYNC_EVENT_ID_SRAM22, 266 GOYA_ASYNC_EVENT_ID_SRAM23, 267 GOYA_ASYNC_EVENT_ID_SRAM24, 268 GOYA_ASYNC_EVENT_ID_SRAM25, 269 GOYA_ASYNC_EVENT_ID_SRAM26, 270 GOYA_ASYNC_EVENT_ID_SRAM27, 271 GOYA_ASYNC_EVENT_ID_SRAM28, 272 GOYA_ASYNC_EVENT_ID_SRAM29, 273 GOYA_ASYNC_EVENT_ID_GIC500, 274 GOYA_ASYNC_EVENT_ID_PLL0, 275 GOYA_ASYNC_EVENT_ID_PLL1, 276 GOYA_ASYNC_EVENT_ID_PLL3, 277 GOYA_ASYNC_EVENT_ID_PLL4, 278 GOYA_ASYNC_EVENT_ID_PLL5, 279 GOYA_ASYNC_EVENT_ID_PLL6, 280 GOYA_ASYNC_EVENT_ID_AXI_ECC, 281 GOYA_ASYNC_EVENT_ID_L2_RAM_ECC, 282 GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET, 283 GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT, 284 GOYA_ASYNC_EVENT_ID_PCIE_DEC, 285 GOYA_ASYNC_EVENT_ID_TPC0_DEC, 286 GOYA_ASYNC_EVENT_ID_TPC1_DEC, 287 GOYA_ASYNC_EVENT_ID_TPC2_DEC, 288 GOYA_ASYNC_EVENT_ID_TPC3_DEC, 289 GOYA_ASYNC_EVENT_ID_TPC4_DEC, 290 GOYA_ASYNC_EVENT_ID_TPC5_DEC, 291 GOYA_ASYNC_EVENT_ID_TPC6_DEC, 292 GOYA_ASYNC_EVENT_ID_TPC7_DEC, 293 GOYA_ASYNC_EVENT_ID_MME_WACS, 294 GOYA_ASYNC_EVENT_ID_MME_WACSD, 295 GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER, 296 GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC, 297 GOYA_ASYNC_EVENT_ID_PSOC, 298 GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR, 299 GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR, 300 GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR, 301 GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR, 302 GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR, 303 GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR, 304 GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR, 305 GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR, 306 GOYA_ASYNC_EVENT_ID_TPC0_CMDQ, 307 GOYA_ASYNC_EVENT_ID_TPC1_CMDQ, 308 GOYA_ASYNC_EVENT_ID_TPC2_CMDQ, 309 GOYA_ASYNC_EVENT_ID_TPC3_CMDQ, 310 GOYA_ASYNC_EVENT_ID_TPC4_CMDQ, 311 GOYA_ASYNC_EVENT_ID_TPC5_CMDQ, 312 GOYA_ASYNC_EVENT_ID_TPC6_CMDQ, 313 GOYA_ASYNC_EVENT_ID_TPC7_CMDQ, 314 GOYA_ASYNC_EVENT_ID_TPC0_QM, 315 GOYA_ASYNC_EVENT_ID_TPC1_QM, 316 GOYA_ASYNC_EVENT_ID_TPC2_QM, 317 GOYA_ASYNC_EVENT_ID_TPC3_QM, 318 GOYA_ASYNC_EVENT_ID_TPC4_QM, 319 GOYA_ASYNC_EVENT_ID_TPC5_QM, 320 GOYA_ASYNC_EVENT_ID_TPC6_QM, 321 GOYA_ASYNC_EVENT_ID_TPC7_QM, 322 GOYA_ASYNC_EVENT_ID_MME_QM, 323 GOYA_ASYNC_EVENT_ID_MME_CMDQ, 324 GOYA_ASYNC_EVENT_ID_DMA0_QM, 325 GOYA_ASYNC_EVENT_ID_DMA1_QM, 326 GOYA_ASYNC_EVENT_ID_DMA2_QM, 327 GOYA_ASYNC_EVENT_ID_DMA3_QM, 328 GOYA_ASYNC_EVENT_ID_DMA4_QM, 329 GOYA_ASYNC_EVENT_ID_DMA0_CH, 330 GOYA_ASYNC_EVENT_ID_DMA1_CH, 331 GOYA_ASYNC_EVENT_ID_DMA2_CH, 332 GOYA_ASYNC_EVENT_ID_DMA3_CH, 333 GOYA_ASYNC_EVENT_ID_DMA4_CH, 334 GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU, 335 GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU, 336 GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU, 337 GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU, 338 GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU, 339 GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU, 340 GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU, 341 GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU, 342 GOYA_ASYNC_EVENT_ID_DMA_BM_CH0, 343 GOYA_ASYNC_EVENT_ID_DMA_BM_CH1, 344 GOYA_ASYNC_EVENT_ID_DMA_BM_CH2, 345 GOYA_ASYNC_EVENT_ID_DMA_BM_CH3, 346 GOYA_ASYNC_EVENT_ID_DMA_BM_CH4, 347 GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S, 348 GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E, 349 GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S, 350 GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E 351 }; 352 353 static s64 goya_state_dump_specs_props[SP_MAX] = {0}; 354 355 static int goya_mmu_clear_pgt_range(struct hl_device *hdev); 356 static int goya_mmu_set_dram_default_page(struct hl_device *hdev); 357 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev); 358 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid); 359 360 int goya_set_fixed_properties(struct hl_device *hdev) 361 { 362 struct asic_fixed_properties *prop = &hdev->asic_prop; 363 int i; 364 365 prop->max_queues = GOYA_QUEUE_ID_SIZE; 366 prop->hw_queues_props = kcalloc(prop->max_queues, 367 sizeof(struct hw_queue_properties), 368 GFP_KERNEL); 369 370 if (!prop->hw_queues_props) 371 return -ENOMEM; 372 373 for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) { 374 prop->hw_queues_props[i].type = QUEUE_TYPE_EXT; 375 prop->hw_queues_props[i].driver_only = 0; 376 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL; 377 } 378 379 for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES ; i++) { 380 prop->hw_queues_props[i].type = QUEUE_TYPE_CPU; 381 prop->hw_queues_props[i].driver_only = 1; 382 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL; 383 } 384 385 for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES + 386 NUMBER_OF_INT_HW_QUEUES; i++) { 387 prop->hw_queues_props[i].type = QUEUE_TYPE_INT; 388 prop->hw_queues_props[i].driver_only = 0; 389 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_USER; 390 } 391 392 prop->cfg_base_address = CFG_BASE; 393 prop->device_dma_offset_for_host_access = HOST_PHYS_BASE; 394 prop->host_base_address = HOST_PHYS_BASE; 395 prop->host_end_address = prop->host_base_address + HOST_PHYS_SIZE; 396 prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES; 397 prop->completion_mode = HL_COMPLETION_MODE_JOB; 398 prop->dram_base_address = DRAM_PHYS_BASE; 399 prop->dram_size = DRAM_PHYS_DEFAULT_SIZE; 400 prop->dram_end_address = prop->dram_base_address + prop->dram_size; 401 prop->dram_user_base_address = DRAM_BASE_ADDR_USER; 402 403 prop->sram_base_address = SRAM_BASE_ADDR; 404 prop->sram_size = SRAM_SIZE; 405 prop->sram_end_address = prop->sram_base_address + prop->sram_size; 406 prop->sram_user_base_address = prop->sram_base_address + 407 SRAM_USER_BASE_OFFSET; 408 409 prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR; 410 prop->mmu_dram_default_page_addr = MMU_DRAM_DEFAULT_PAGE_ADDR; 411 if (hdev->pldm) 412 prop->mmu_pgt_size = 0x800000; /* 8MB */ 413 else 414 prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE; 415 prop->mmu_pte_size = HL_PTE_SIZE; 416 prop->mmu_hop_table_size = HOP_TABLE_SIZE_512_PTE; 417 prop->mmu_hop0_tables_total_size = HOP0_512_PTE_TABLES_TOTAL_SIZE; 418 prop->dram_page_size = PAGE_SIZE_2MB; 419 prop->device_mem_alloc_default_page_size = prop->dram_page_size; 420 prop->dram_supports_virtual_memory = true; 421 422 prop->dmmu.hop_shifts[MMU_HOP0] = MMU_V1_0_HOP0_SHIFT; 423 prop->dmmu.hop_shifts[MMU_HOP1] = MMU_V1_0_HOP1_SHIFT; 424 prop->dmmu.hop_shifts[MMU_HOP2] = MMU_V1_0_HOP2_SHIFT; 425 prop->dmmu.hop_shifts[MMU_HOP3] = MMU_V1_0_HOP3_SHIFT; 426 prop->dmmu.hop_shifts[MMU_HOP4] = MMU_V1_0_HOP4_SHIFT; 427 prop->dmmu.hop_masks[MMU_HOP0] = MMU_V1_0_HOP0_MASK; 428 prop->dmmu.hop_masks[MMU_HOP1] = MMU_V1_0_HOP1_MASK; 429 prop->dmmu.hop_masks[MMU_HOP2] = MMU_V1_0_HOP2_MASK; 430 prop->dmmu.hop_masks[MMU_HOP3] = MMU_V1_0_HOP3_MASK; 431 prop->dmmu.hop_masks[MMU_HOP4] = MMU_V1_0_HOP4_MASK; 432 prop->dmmu.start_addr = VA_DDR_SPACE_START; 433 prop->dmmu.end_addr = VA_DDR_SPACE_END; 434 prop->dmmu.page_size = PAGE_SIZE_2MB; 435 prop->dmmu.num_hops = MMU_ARCH_5_HOPS; 436 prop->dmmu.last_mask = LAST_MASK; 437 /* TODO: will be duplicated until implementing per-MMU props */ 438 prop->dmmu.hop_table_size = prop->mmu_hop_table_size; 439 prop->dmmu.hop0_tables_total_size = prop->mmu_hop0_tables_total_size; 440 441 /* shifts and masks are the same in PMMU and DMMU */ 442 memcpy(&prop->pmmu, &prop->dmmu, sizeof(prop->dmmu)); 443 prop->pmmu.start_addr = VA_HOST_SPACE_START; 444 prop->pmmu.end_addr = VA_HOST_SPACE_END; 445 prop->pmmu.page_size = PAGE_SIZE_4KB; 446 prop->pmmu.num_hops = MMU_ARCH_5_HOPS; 447 prop->pmmu.last_mask = LAST_MASK; 448 /* TODO: will be duplicated until implementing per-MMU props */ 449 prop->pmmu.hop_table_size = prop->mmu_hop_table_size; 450 prop->pmmu.hop0_tables_total_size = prop->mmu_hop0_tables_total_size; 451 452 /* PMMU and HPMMU are the same except of page size */ 453 memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu)); 454 prop->pmmu_huge.page_size = PAGE_SIZE_2MB; 455 456 prop->dram_size_for_default_page_mapping = VA_DDR_SPACE_END; 457 prop->cfg_size = CFG_SIZE; 458 prop->max_asid = MAX_ASID; 459 prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE; 460 prop->high_pll = PLL_HIGH_DEFAULT; 461 prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT; 462 prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE; 463 prop->max_power_default = MAX_POWER_DEFAULT; 464 prop->dc_power_default = DC_POWER_DEFAULT; 465 prop->tpc_enabled_mask = TPC_ENABLED_MASK; 466 prop->pcie_dbi_base_address = mmPCIE_DBI_BASE; 467 prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI; 468 469 strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME, 470 CARD_NAME_MAX_LEN); 471 472 prop->max_pending_cs = GOYA_MAX_PENDING_CS; 473 474 prop->first_available_user_interrupt = USHRT_MAX; 475 prop->tpc_interrupt_id = USHRT_MAX; 476 477 for (i = 0 ; i < HL_MAX_DCORES ; i++) 478 prop->first_available_cq[i] = USHRT_MAX; 479 480 prop->fw_cpu_boot_dev_sts0_valid = false; 481 prop->fw_cpu_boot_dev_sts1_valid = false; 482 prop->hard_reset_done_by_fw = false; 483 prop->gic_interrupts_enable = true; 484 485 prop->server_type = HL_SERVER_TYPE_UNKNOWN; 486 487 prop->clk_pll_index = HL_GOYA_MME_PLL; 488 489 prop->use_get_power_for_reset_history = true; 490 491 prop->configurable_stop_on_err = true; 492 493 prop->set_max_power_on_device_init = true; 494 495 prop->dma_mask = 48; 496 497 return 0; 498 } 499 500 /* 501 * goya_pci_bars_map - Map PCI BARS of Goya device 502 * 503 * @hdev: pointer to hl_device structure 504 * 505 * Request PCI regions and map them to kernel virtual addresses. 506 * Returns 0 on success 507 * 508 */ 509 static int goya_pci_bars_map(struct hl_device *hdev) 510 { 511 static const char * const name[] = {"SRAM_CFG", "MSIX", "DDR"}; 512 bool is_wc[3] = {false, false, true}; 513 int rc; 514 515 rc = hl_pci_bars_map(hdev, name, is_wc); 516 if (rc) 517 return rc; 518 519 hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] + 520 (CFG_BASE - SRAM_BASE_ADDR); 521 522 return 0; 523 } 524 525 static u64 goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr) 526 { 527 struct goya_device *goya = hdev->asic_specific; 528 struct hl_inbound_pci_region pci_region; 529 u64 old_addr = addr; 530 int rc; 531 532 if ((goya) && (goya->ddr_bar_cur_addr == addr)) 533 return old_addr; 534 535 /* Inbound Region 1 - Bar 4 - Point to DDR */ 536 pci_region.mode = PCI_BAR_MATCH_MODE; 537 pci_region.bar = DDR_BAR_ID; 538 pci_region.addr = addr; 539 rc = hl_pci_set_inbound_region(hdev, 1, &pci_region); 540 if (rc) 541 return U64_MAX; 542 543 if (goya) { 544 old_addr = goya->ddr_bar_cur_addr; 545 goya->ddr_bar_cur_addr = addr; 546 } 547 548 return old_addr; 549 } 550 551 /* 552 * goya_init_iatu - Initialize the iATU unit inside the PCI controller 553 * 554 * @hdev: pointer to hl_device structure 555 * 556 * This is needed in case the firmware doesn't initialize the iATU 557 * 558 */ 559 static int goya_init_iatu(struct hl_device *hdev) 560 { 561 struct hl_inbound_pci_region inbound_region; 562 struct hl_outbound_pci_region outbound_region; 563 int rc; 564 565 if (hdev->asic_prop.iatu_done_by_fw) 566 return 0; 567 568 /* Inbound Region 0 - Bar 0 - Point to SRAM and CFG */ 569 inbound_region.mode = PCI_BAR_MATCH_MODE; 570 inbound_region.bar = SRAM_CFG_BAR_ID; 571 inbound_region.addr = SRAM_BASE_ADDR; 572 rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region); 573 if (rc) 574 goto done; 575 576 /* Inbound Region 1 - Bar 4 - Point to DDR */ 577 inbound_region.mode = PCI_BAR_MATCH_MODE; 578 inbound_region.bar = DDR_BAR_ID; 579 inbound_region.addr = DRAM_PHYS_BASE; 580 rc = hl_pci_set_inbound_region(hdev, 1, &inbound_region); 581 if (rc) 582 goto done; 583 584 /* Outbound Region 0 - Point to Host */ 585 outbound_region.addr = HOST_PHYS_BASE; 586 outbound_region.size = HOST_PHYS_SIZE; 587 rc = hl_pci_set_outbound_region(hdev, &outbound_region); 588 589 done: 590 return rc; 591 } 592 593 static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev) 594 { 595 return RREG32(mmHW_STATE); 596 } 597 598 /* 599 * goya_early_init - GOYA early initialization code 600 * 601 * @hdev: pointer to hl_device structure 602 * 603 * Verify PCI bars 604 * Set DMA masks 605 * PCI controller initialization 606 * Map PCI bars 607 * 608 */ 609 static int goya_early_init(struct hl_device *hdev) 610 { 611 struct asic_fixed_properties *prop = &hdev->asic_prop; 612 struct pci_dev *pdev = hdev->pdev; 613 resource_size_t pci_bar_size; 614 u32 fw_boot_status, val; 615 int rc; 616 617 rc = goya_set_fixed_properties(hdev); 618 if (rc) { 619 dev_err(hdev->dev, "Failed to get fixed properties\n"); 620 return rc; 621 } 622 623 /* Check BAR sizes */ 624 pci_bar_size = pci_resource_len(pdev, SRAM_CFG_BAR_ID); 625 626 if (pci_bar_size != CFG_BAR_SIZE) { 627 dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n", 628 SRAM_CFG_BAR_ID, &pci_bar_size, CFG_BAR_SIZE); 629 rc = -ENODEV; 630 goto free_queue_props; 631 } 632 633 pci_bar_size = pci_resource_len(pdev, MSIX_BAR_ID); 634 635 if (pci_bar_size != MSIX_BAR_SIZE) { 636 dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n", 637 MSIX_BAR_ID, &pci_bar_size, MSIX_BAR_SIZE); 638 rc = -ENODEV; 639 goto free_queue_props; 640 } 641 642 prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID); 643 hdev->dram_pci_bar_start = pci_resource_start(pdev, DDR_BAR_ID); 644 645 /* If FW security is enabled at this point it means no access to ELBI */ 646 if (hdev->asic_prop.fw_security_enabled) { 647 hdev->asic_prop.iatu_done_by_fw = true; 648 goto pci_init; 649 } 650 651 rc = hl_pci_elbi_read(hdev, CFG_BASE + mmCPU_BOOT_DEV_STS0, 652 &fw_boot_status); 653 if (rc) 654 goto free_queue_props; 655 656 /* Check whether FW is configuring iATU */ 657 if ((fw_boot_status & CPU_BOOT_DEV_STS0_ENABLED) && 658 (fw_boot_status & CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN)) 659 hdev->asic_prop.iatu_done_by_fw = true; 660 661 pci_init: 662 rc = hl_pci_init(hdev); 663 if (rc) 664 goto free_queue_props; 665 666 /* Before continuing in the initialization, we need to read the preboot 667 * version to determine whether we run with a security-enabled firmware 668 */ 669 rc = hl_fw_read_preboot_status(hdev); 670 if (rc) { 671 if (hdev->reset_on_preboot_fail) 672 /* we are already on failure flow, so don't check if hw_fini fails. */ 673 hdev->asic_funcs->hw_fini(hdev, true, false); 674 goto pci_fini; 675 } 676 677 if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) { 678 dev_dbg(hdev->dev, "H/W state is dirty, must reset before initializing\n"); 679 rc = hdev->asic_funcs->hw_fini(hdev, true, false); 680 if (rc) { 681 dev_err(hdev->dev, "failed to reset HW in dirty state (%d)\n", rc); 682 goto pci_fini; 683 } 684 } 685 686 if (!hdev->pldm) { 687 val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS); 688 if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK) 689 dev_warn(hdev->dev, 690 "PCI strap is not configured correctly, PCI bus errors may occur\n"); 691 } 692 693 return 0; 694 695 pci_fini: 696 hl_pci_fini(hdev); 697 free_queue_props: 698 kfree(hdev->asic_prop.hw_queues_props); 699 return rc; 700 } 701 702 /* 703 * goya_early_fini - GOYA early finalization code 704 * 705 * @hdev: pointer to hl_device structure 706 * 707 * Unmap PCI bars 708 * 709 */ 710 static int goya_early_fini(struct hl_device *hdev) 711 { 712 kfree(hdev->asic_prop.hw_queues_props); 713 hl_pci_fini(hdev); 714 715 return 0; 716 } 717 718 static void goya_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid) 719 { 720 /* mask to zero the MMBP and ASID bits */ 721 WREG32_AND(reg, ~0x7FF); 722 WREG32_OR(reg, asid); 723 } 724 725 static void goya_qman0_set_security(struct hl_device *hdev, bool secure) 726 { 727 struct goya_device *goya = hdev->asic_specific; 728 729 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) 730 return; 731 732 if (secure) 733 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED); 734 else 735 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED); 736 737 RREG32(mmDMA_QM_0_GLBL_PROT); 738 } 739 740 /* 741 * goya_fetch_psoc_frequency - Fetch PSOC frequency values 742 * 743 * @hdev: pointer to hl_device structure 744 * 745 */ 746 static void goya_fetch_psoc_frequency(struct hl_device *hdev) 747 { 748 struct asic_fixed_properties *prop = &hdev->asic_prop; 749 u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel; 750 u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq; 751 int rc; 752 753 if (hdev->asic_prop.fw_security_enabled) { 754 struct goya_device *goya = hdev->asic_specific; 755 756 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) 757 return; 758 759 rc = hl_fw_cpucp_pll_info_get(hdev, HL_GOYA_PCI_PLL, 760 pll_freq_arr); 761 762 if (rc) 763 return; 764 765 freq = pll_freq_arr[1]; 766 } else { 767 div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1); 768 div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1); 769 nr = RREG32(mmPSOC_PCI_PLL_NR); 770 nf = RREG32(mmPSOC_PCI_PLL_NF); 771 od = RREG32(mmPSOC_PCI_PLL_OD); 772 773 if (div_sel == DIV_SEL_REF_CLK || 774 div_sel == DIV_SEL_DIVIDED_REF) { 775 if (div_sel == DIV_SEL_REF_CLK) 776 freq = PLL_REF_CLK; 777 else 778 freq = PLL_REF_CLK / (div_fctr + 1); 779 } else if (div_sel == DIV_SEL_PLL_CLK || 780 div_sel == DIV_SEL_DIVIDED_PLL) { 781 pll_clk = PLL_REF_CLK * (nf + 1) / 782 ((nr + 1) * (od + 1)); 783 if (div_sel == DIV_SEL_PLL_CLK) 784 freq = pll_clk; 785 else 786 freq = pll_clk / (div_fctr + 1); 787 } else { 788 dev_warn(hdev->dev, 789 "Received invalid div select value: %d", 790 div_sel); 791 freq = 0; 792 } 793 } 794 795 prop->psoc_timestamp_frequency = freq; 796 prop->psoc_pci_pll_nr = nr; 797 prop->psoc_pci_pll_nf = nf; 798 prop->psoc_pci_pll_od = od; 799 prop->psoc_pci_pll_div_factor = div_fctr; 800 } 801 802 /* 803 * goya_set_frequency - set the frequency of the device 804 * 805 * @hdev: pointer to habanalabs device structure 806 * @freq: the new frequency value 807 * 808 * Change the frequency if needed. This function has no protection against 809 * concurrency, therefore it is assumed that the calling function has protected 810 * itself against the case of calling this function from multiple threads with 811 * different values 812 * 813 * Returns 0 if no change was done, otherwise returns 1 814 */ 815 int goya_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq) 816 { 817 struct goya_device *goya = hdev->asic_specific; 818 819 if ((goya->pm_mng_profile == PM_MANUAL) || 820 (goya->curr_pll_profile == freq)) 821 return 0; 822 823 dev_dbg(hdev->dev, "Changing device frequency to %s\n", 824 freq == PLL_HIGH ? "high" : "low"); 825 826 goya_set_pll_profile(hdev, freq); 827 828 goya->curr_pll_profile = freq; 829 830 return 1; 831 } 832 833 static void goya_set_freq_to_low_job(struct work_struct *work) 834 { 835 struct goya_work_freq *goya_work = container_of(work, 836 struct goya_work_freq, 837 work_freq.work); 838 struct hl_device *hdev = goya_work->hdev; 839 840 mutex_lock(&hdev->fpriv_list_lock); 841 842 if (!hdev->is_compute_ctx_active) 843 goya_set_frequency(hdev, PLL_LOW); 844 845 mutex_unlock(&hdev->fpriv_list_lock); 846 847 schedule_delayed_work(&goya_work->work_freq, 848 usecs_to_jiffies(HL_PLL_LOW_JOB_FREQ_USEC)); 849 } 850 851 int goya_late_init(struct hl_device *hdev) 852 { 853 struct asic_fixed_properties *prop = &hdev->asic_prop; 854 struct goya_device *goya = hdev->asic_specific; 855 int rc; 856 857 goya_fetch_psoc_frequency(hdev); 858 859 rc = goya_mmu_clear_pgt_range(hdev); 860 if (rc) { 861 dev_err(hdev->dev, 862 "Failed to clear MMU page tables range %d\n", rc); 863 return rc; 864 } 865 866 rc = goya_mmu_set_dram_default_page(hdev); 867 if (rc) { 868 dev_err(hdev->dev, "Failed to set DRAM default page %d\n", rc); 869 return rc; 870 } 871 872 rc = goya_mmu_add_mappings_for_device_cpu(hdev); 873 if (rc) 874 return rc; 875 876 rc = goya_init_cpu_queues(hdev); 877 if (rc) 878 return rc; 879 880 rc = goya_test_cpu_queue(hdev); 881 if (rc) 882 return rc; 883 884 rc = goya_cpucp_info_get(hdev); 885 if (rc) { 886 dev_err(hdev->dev, "Failed to get cpucp info %d\n", rc); 887 return rc; 888 } 889 890 /* Now that we have the DRAM size in ASIC prop, we need to check 891 * its size and configure the DMA_IF DDR wrap protection (which is in 892 * the MMU block) accordingly. The value is the log2 of the DRAM size 893 */ 894 WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size)); 895 896 rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS, 0x0); 897 if (rc) { 898 dev_err(hdev->dev, 899 "Failed to enable PCI access from CPU %d\n", rc); 900 return rc; 901 } 902 903 /* force setting to low frequency */ 904 goya->curr_pll_profile = PLL_LOW; 905 906 goya->pm_mng_profile = PM_AUTO; 907 908 goya_set_pll_profile(hdev, PLL_LOW); 909 910 schedule_delayed_work(&goya->goya_work->work_freq, 911 usecs_to_jiffies(HL_PLL_LOW_JOB_FREQ_USEC)); 912 913 return 0; 914 } 915 916 /* 917 * goya_late_fini - GOYA late tear-down code 918 * 919 * @hdev: pointer to hl_device structure 920 * 921 * Free sensors allocated structures 922 */ 923 void goya_late_fini(struct hl_device *hdev) 924 { 925 struct goya_device *goya = hdev->asic_specific; 926 927 cancel_delayed_work_sync(&goya->goya_work->work_freq); 928 929 hl_hwmon_release_resources(hdev); 930 } 931 932 static void goya_set_pci_memory_regions(struct hl_device *hdev) 933 { 934 struct asic_fixed_properties *prop = &hdev->asic_prop; 935 struct pci_mem_region *region; 936 937 /* CFG */ 938 region = &hdev->pci_mem_region[PCI_REGION_CFG]; 939 region->region_base = CFG_BASE; 940 region->region_size = CFG_SIZE; 941 region->offset_in_bar = CFG_BASE - SRAM_BASE_ADDR; 942 region->bar_size = CFG_BAR_SIZE; 943 region->bar_id = SRAM_CFG_BAR_ID; 944 region->used = 1; 945 946 /* SRAM */ 947 region = &hdev->pci_mem_region[PCI_REGION_SRAM]; 948 region->region_base = SRAM_BASE_ADDR; 949 region->region_size = SRAM_SIZE; 950 region->offset_in_bar = 0; 951 region->bar_size = CFG_BAR_SIZE; 952 region->bar_id = SRAM_CFG_BAR_ID; 953 region->used = 1; 954 955 /* DRAM */ 956 region = &hdev->pci_mem_region[PCI_REGION_DRAM]; 957 region->region_base = DRAM_PHYS_BASE; 958 region->region_size = hdev->asic_prop.dram_size; 959 region->offset_in_bar = 0; 960 region->bar_size = prop->dram_pci_bar_size; 961 region->bar_id = DDR_BAR_ID; 962 region->used = 1; 963 } 964 965 /* 966 * goya_sw_init - Goya software initialization code 967 * 968 * @hdev: pointer to hl_device structure 969 * 970 */ 971 static int goya_sw_init(struct hl_device *hdev) 972 { 973 struct goya_device *goya; 974 int rc; 975 976 /* Allocate device structure */ 977 goya = kzalloc(sizeof(*goya), GFP_KERNEL); 978 if (!goya) 979 return -ENOMEM; 980 981 /* according to goya_init_iatu */ 982 goya->ddr_bar_cur_addr = DRAM_PHYS_BASE; 983 984 goya->mme_clk = GOYA_PLL_FREQ_LOW; 985 goya->tpc_clk = GOYA_PLL_FREQ_LOW; 986 goya->ic_clk = GOYA_PLL_FREQ_LOW; 987 988 hdev->asic_specific = goya; 989 990 /* Create DMA pool for small allocations */ 991 hdev->dma_pool = dma_pool_create(dev_name(hdev->dev), 992 &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0); 993 if (!hdev->dma_pool) { 994 dev_err(hdev->dev, "failed to create DMA pool\n"); 995 rc = -ENOMEM; 996 goto free_goya_device; 997 } 998 999 hdev->cpu_accessible_dma_mem = hl_asic_dma_alloc_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, 1000 &hdev->cpu_accessible_dma_address, 1001 GFP_KERNEL | __GFP_ZERO); 1002 1003 if (!hdev->cpu_accessible_dma_mem) { 1004 rc = -ENOMEM; 1005 goto free_dma_pool; 1006 } 1007 1008 dev_dbg(hdev->dev, "cpu accessible memory at bus address %pad\n", 1009 &hdev->cpu_accessible_dma_address); 1010 1011 hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1); 1012 if (!hdev->cpu_accessible_dma_pool) { 1013 dev_err(hdev->dev, 1014 "Failed to create CPU accessible DMA pool\n"); 1015 rc = -ENOMEM; 1016 goto free_cpu_dma_mem; 1017 } 1018 1019 rc = gen_pool_add(hdev->cpu_accessible_dma_pool, 1020 (uintptr_t) hdev->cpu_accessible_dma_mem, 1021 HL_CPU_ACCESSIBLE_MEM_SIZE, -1); 1022 if (rc) { 1023 dev_err(hdev->dev, 1024 "Failed to add memory to CPU accessible DMA pool\n"); 1025 rc = -EFAULT; 1026 goto free_cpu_accessible_dma_pool; 1027 } 1028 1029 spin_lock_init(&goya->hw_queues_lock); 1030 hdev->supports_coresight = true; 1031 hdev->asic_prop.supports_compute_reset = true; 1032 hdev->asic_prop.allow_inference_soft_reset = true; 1033 hdev->supports_wait_for_multi_cs = false; 1034 hdev->supports_ctx_switch = true; 1035 1036 hdev->asic_funcs->set_pci_memory_regions(hdev); 1037 1038 goya->goya_work = kmalloc(sizeof(struct goya_work_freq), GFP_KERNEL); 1039 if (!goya->goya_work) { 1040 rc = -ENOMEM; 1041 goto free_cpu_accessible_dma_pool; 1042 } 1043 1044 goya->goya_work->hdev = hdev; 1045 INIT_DELAYED_WORK(&goya->goya_work->work_freq, goya_set_freq_to_low_job); 1046 1047 return 0; 1048 1049 free_cpu_accessible_dma_pool: 1050 gen_pool_destroy(hdev->cpu_accessible_dma_pool); 1051 free_cpu_dma_mem: 1052 hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem, 1053 hdev->cpu_accessible_dma_address); 1054 free_dma_pool: 1055 dma_pool_destroy(hdev->dma_pool); 1056 free_goya_device: 1057 kfree(goya); 1058 1059 return rc; 1060 } 1061 1062 /* 1063 * goya_sw_fini - Goya software tear-down code 1064 * 1065 * @hdev: pointer to hl_device structure 1066 * 1067 */ 1068 static int goya_sw_fini(struct hl_device *hdev) 1069 { 1070 struct goya_device *goya = hdev->asic_specific; 1071 1072 gen_pool_destroy(hdev->cpu_accessible_dma_pool); 1073 1074 hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem, 1075 hdev->cpu_accessible_dma_address); 1076 1077 dma_pool_destroy(hdev->dma_pool); 1078 1079 kfree(goya->goya_work); 1080 kfree(goya); 1081 1082 return 0; 1083 } 1084 1085 static void goya_init_dma_qman(struct hl_device *hdev, int dma_id, 1086 dma_addr_t bus_address) 1087 { 1088 struct goya_device *goya = hdev->asic_specific; 1089 u32 mtr_base_lo, mtr_base_hi; 1090 u32 so_base_lo, so_base_hi; 1091 u32 gic_base_lo, gic_base_hi; 1092 u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI); 1093 u32 dma_err_cfg = QMAN_DMA_ERR_MSG_EN; 1094 1095 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); 1096 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); 1097 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); 1098 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); 1099 1100 gic_base_lo = 1101 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); 1102 gic_base_hi = 1103 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); 1104 1105 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address)); 1106 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address)); 1107 1108 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH)); 1109 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); 1110 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); 1111 1112 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); 1113 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); 1114 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); 1115 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); 1116 WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo); 1117 WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi); 1118 WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off, 1119 GOYA_ASYNC_EVENT_ID_DMA0_QM + dma_id); 1120 1121 /* PQ has buffer of 2 cache lines, while CQ has 8 lines */ 1122 WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002); 1123 WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008); 1124 1125 if (goya->hw_cap_initialized & HW_CAP_MMU) 1126 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED); 1127 else 1128 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED); 1129 1130 if (hdev->stop_on_err) 1131 dma_err_cfg |= 1 << DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT; 1132 1133 WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, dma_err_cfg); 1134 WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE); 1135 } 1136 1137 static void goya_init_dma_ch(struct hl_device *hdev, int dma_id) 1138 { 1139 u32 gic_base_lo, gic_base_hi; 1140 u64 sob_addr; 1141 u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1); 1142 1143 gic_base_lo = 1144 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); 1145 gic_base_hi = 1146 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); 1147 1148 WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo); 1149 WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi); 1150 WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off, 1151 GOYA_ASYNC_EVENT_ID_DMA0_CH + dma_id); 1152 1153 if (dma_id) 1154 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 + 1155 (dma_id - 1) * 4; 1156 else 1157 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007; 1158 1159 WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr)); 1160 WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001); 1161 } 1162 1163 /* 1164 * goya_init_dma_qmans - Initialize QMAN DMA registers 1165 * 1166 * @hdev: pointer to hl_device structure 1167 * 1168 * Initialize the H/W registers of the QMAN DMA channels 1169 * 1170 */ 1171 void goya_init_dma_qmans(struct hl_device *hdev) 1172 { 1173 struct goya_device *goya = hdev->asic_specific; 1174 struct hl_hw_queue *q; 1175 int i; 1176 1177 if (goya->hw_cap_initialized & HW_CAP_DMA) 1178 return; 1179 1180 q = &hdev->kernel_queues[0]; 1181 1182 for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) { 1183 q->cq_id = q->msi_vec = i; 1184 goya_init_dma_qman(hdev, i, q->bus_address); 1185 goya_init_dma_ch(hdev, i); 1186 } 1187 1188 goya->hw_cap_initialized |= HW_CAP_DMA; 1189 } 1190 1191 /* 1192 * goya_disable_external_queues - Disable external queues 1193 * 1194 * @hdev: pointer to hl_device structure 1195 * 1196 */ 1197 static void goya_disable_external_queues(struct hl_device *hdev) 1198 { 1199 struct goya_device *goya = hdev->asic_specific; 1200 1201 if (!(goya->hw_cap_initialized & HW_CAP_DMA)) 1202 return; 1203 1204 WREG32(mmDMA_QM_0_GLBL_CFG0, 0); 1205 WREG32(mmDMA_QM_1_GLBL_CFG0, 0); 1206 WREG32(mmDMA_QM_2_GLBL_CFG0, 0); 1207 WREG32(mmDMA_QM_3_GLBL_CFG0, 0); 1208 WREG32(mmDMA_QM_4_GLBL_CFG0, 0); 1209 } 1210 1211 static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg, 1212 u32 cp_sts_reg, u32 glbl_sts0_reg) 1213 { 1214 int rc; 1215 u32 status; 1216 1217 /* use the values of TPC0 as they are all the same*/ 1218 1219 WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); 1220 1221 status = RREG32(cp_sts_reg); 1222 if (status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK) { 1223 rc = hl_poll_timeout( 1224 hdev, 1225 cp_sts_reg, 1226 status, 1227 !(status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK), 1228 1000, 1229 QMAN_FENCE_TIMEOUT_USEC); 1230 1231 /* if QMAN is stuck in fence no need to check for stop */ 1232 if (rc) 1233 return 0; 1234 } 1235 1236 rc = hl_poll_timeout( 1237 hdev, 1238 glbl_sts0_reg, 1239 status, 1240 (status & TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK), 1241 1000, 1242 QMAN_STOP_TIMEOUT_USEC); 1243 1244 if (rc) { 1245 dev_err(hdev->dev, 1246 "Timeout while waiting for QMAN to stop\n"); 1247 return -EINVAL; 1248 } 1249 1250 return 0; 1251 } 1252 1253 /* 1254 * goya_stop_external_queues - Stop external queues 1255 * 1256 * @hdev: pointer to hl_device structure 1257 * 1258 * Returns 0 on success 1259 * 1260 */ 1261 static int goya_stop_external_queues(struct hl_device *hdev) 1262 { 1263 int rc, retval = 0; 1264 1265 struct goya_device *goya = hdev->asic_specific; 1266 1267 if (!(goya->hw_cap_initialized & HW_CAP_DMA)) 1268 return retval; 1269 1270 rc = goya_stop_queue(hdev, 1271 mmDMA_QM_0_GLBL_CFG1, 1272 mmDMA_QM_0_CP_STS, 1273 mmDMA_QM_0_GLBL_STS0); 1274 1275 if (rc) { 1276 dev_err(hdev->dev, "failed to stop DMA QMAN 0\n"); 1277 retval = -EIO; 1278 } 1279 1280 rc = goya_stop_queue(hdev, 1281 mmDMA_QM_1_GLBL_CFG1, 1282 mmDMA_QM_1_CP_STS, 1283 mmDMA_QM_1_GLBL_STS0); 1284 1285 if (rc) { 1286 dev_err(hdev->dev, "failed to stop DMA QMAN 1\n"); 1287 retval = -EIO; 1288 } 1289 1290 rc = goya_stop_queue(hdev, 1291 mmDMA_QM_2_GLBL_CFG1, 1292 mmDMA_QM_2_CP_STS, 1293 mmDMA_QM_2_GLBL_STS0); 1294 1295 if (rc) { 1296 dev_err(hdev->dev, "failed to stop DMA QMAN 2\n"); 1297 retval = -EIO; 1298 } 1299 1300 rc = goya_stop_queue(hdev, 1301 mmDMA_QM_3_GLBL_CFG1, 1302 mmDMA_QM_3_CP_STS, 1303 mmDMA_QM_3_GLBL_STS0); 1304 1305 if (rc) { 1306 dev_err(hdev->dev, "failed to stop DMA QMAN 3\n"); 1307 retval = -EIO; 1308 } 1309 1310 rc = goya_stop_queue(hdev, 1311 mmDMA_QM_4_GLBL_CFG1, 1312 mmDMA_QM_4_CP_STS, 1313 mmDMA_QM_4_GLBL_STS0); 1314 1315 if (rc) { 1316 dev_err(hdev->dev, "failed to stop DMA QMAN 4\n"); 1317 retval = -EIO; 1318 } 1319 1320 return retval; 1321 } 1322 1323 /* 1324 * goya_init_cpu_queues - Initialize PQ/CQ/EQ of CPU 1325 * 1326 * @hdev: pointer to hl_device structure 1327 * 1328 * Returns 0 on success 1329 * 1330 */ 1331 int goya_init_cpu_queues(struct hl_device *hdev) 1332 { 1333 struct goya_device *goya = hdev->asic_specific; 1334 struct asic_fixed_properties *prop = &hdev->asic_prop; 1335 struct hl_eq *eq; 1336 u32 status; 1337 struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ]; 1338 int err; 1339 1340 if (!hdev->cpu_queues_enable) 1341 return 0; 1342 1343 if (goya->hw_cap_initialized & HW_CAP_CPU_Q) 1344 return 0; 1345 1346 eq = &hdev->event_queue; 1347 1348 WREG32(mmCPU_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address)); 1349 WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address)); 1350 1351 WREG32(mmCPU_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address)); 1352 WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address)); 1353 1354 WREG32(mmCPU_CQ_BASE_ADDR_LOW, 1355 lower_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR)); 1356 WREG32(mmCPU_CQ_BASE_ADDR_HIGH, 1357 upper_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR)); 1358 1359 WREG32(mmCPU_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES); 1360 WREG32(mmCPU_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES); 1361 WREG32(mmCPU_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE); 1362 1363 /* Used for EQ CI */ 1364 WREG32(mmCPU_EQ_CI, 0); 1365 1366 WREG32(mmCPU_IF_PF_PQ_PI, 0); 1367 1368 WREG32(mmCPU_PQ_INIT_STATUS, PQ_INIT_STATUS_READY_FOR_CP); 1369 1370 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, 1371 GOYA_ASYNC_EVENT_ID_PI_UPDATE); 1372 1373 err = hl_poll_timeout( 1374 hdev, 1375 mmCPU_PQ_INIT_STATUS, 1376 status, 1377 (status == PQ_INIT_STATUS_READY_FOR_HOST), 1378 1000, 1379 GOYA_CPU_TIMEOUT_USEC); 1380 1381 if (err) { 1382 dev_err(hdev->dev, 1383 "Failed to setup communication with device CPU\n"); 1384 return -EIO; 1385 } 1386 1387 /* update FW application security bits */ 1388 if (prop->fw_cpu_boot_dev_sts0_valid) 1389 prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0); 1390 1391 if (prop->fw_cpu_boot_dev_sts1_valid) 1392 prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1); 1393 1394 goya->hw_cap_initialized |= HW_CAP_CPU_Q; 1395 return 0; 1396 } 1397 1398 static void goya_set_pll_refclk(struct hl_device *hdev) 1399 { 1400 WREG32(mmCPU_PLL_DIV_SEL_0, 0x0); 1401 WREG32(mmCPU_PLL_DIV_SEL_1, 0x0); 1402 WREG32(mmCPU_PLL_DIV_SEL_2, 0x0); 1403 WREG32(mmCPU_PLL_DIV_SEL_3, 0x0); 1404 1405 WREG32(mmIC_PLL_DIV_SEL_0, 0x0); 1406 WREG32(mmIC_PLL_DIV_SEL_1, 0x0); 1407 WREG32(mmIC_PLL_DIV_SEL_2, 0x0); 1408 WREG32(mmIC_PLL_DIV_SEL_3, 0x0); 1409 1410 WREG32(mmMC_PLL_DIV_SEL_0, 0x0); 1411 WREG32(mmMC_PLL_DIV_SEL_1, 0x0); 1412 WREG32(mmMC_PLL_DIV_SEL_2, 0x0); 1413 WREG32(mmMC_PLL_DIV_SEL_3, 0x0); 1414 1415 WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0); 1416 WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0); 1417 WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0); 1418 WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0); 1419 1420 WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0); 1421 WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0); 1422 WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0); 1423 WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0); 1424 1425 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0); 1426 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0); 1427 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0); 1428 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0); 1429 1430 WREG32(mmTPC_PLL_DIV_SEL_0, 0x0); 1431 WREG32(mmTPC_PLL_DIV_SEL_1, 0x0); 1432 WREG32(mmTPC_PLL_DIV_SEL_2, 0x0); 1433 WREG32(mmTPC_PLL_DIV_SEL_3, 0x0); 1434 } 1435 1436 static void goya_disable_clk_rlx(struct hl_device *hdev) 1437 { 1438 WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010); 1439 WREG32(mmIC_PLL_CLK_RLX_0, 0x100010); 1440 } 1441 1442 static void _goya_tpc_mbist_workaround(struct hl_device *hdev, u8 tpc_id) 1443 { 1444 u64 tpc_eml_address; 1445 u32 val, tpc_offset, tpc_eml_offset, tpc_slm_offset; 1446 int err, slm_index; 1447 1448 tpc_offset = tpc_id * 0x40000; 1449 tpc_eml_offset = tpc_id * 0x200000; 1450 tpc_eml_address = (mmTPC0_EML_CFG_BASE + tpc_eml_offset - CFG_BASE); 1451 tpc_slm_offset = tpc_eml_address + 0x100000; 1452 1453 /* 1454 * Workaround for Bug H2 #2443 : 1455 * "TPC SB is not initialized on chip reset" 1456 */ 1457 1458 val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset); 1459 if (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK) 1460 dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n", 1461 tpc_id); 1462 1463 WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000); 1464 1465 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF); 1466 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F); 1467 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF); 1468 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF); 1469 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF); 1470 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF); 1471 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF); 1472 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF); 1473 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF); 1474 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF); 1475 1476 WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset, 1477 1 << TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT); 1478 1479 err = hl_poll_timeout( 1480 hdev, 1481 mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset, 1482 val, 1483 (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK), 1484 1000, 1485 HL_DEVICE_TIMEOUT_USEC); 1486 1487 if (err) 1488 dev_err(hdev->dev, 1489 "Timeout while waiting for TPC%d MBIST DONE\n", tpc_id); 1490 1491 WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset, 1492 1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT); 1493 1494 msleep(GOYA_RESET_WAIT_MSEC); 1495 1496 WREG32_AND(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset, 1497 ~(1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT)); 1498 1499 msleep(GOYA_RESET_WAIT_MSEC); 1500 1501 for (slm_index = 0 ; slm_index < 256 ; slm_index++) 1502 WREG32(tpc_slm_offset + (slm_index << 2), 0); 1503 1504 val = RREG32(tpc_slm_offset); 1505 } 1506 1507 static void goya_tpc_mbist_workaround(struct hl_device *hdev) 1508 { 1509 struct goya_device *goya = hdev->asic_specific; 1510 int i; 1511 1512 if (hdev->pldm) 1513 return; 1514 1515 if (goya->hw_cap_initialized & HW_CAP_TPC_MBIST) 1516 return; 1517 1518 /* Workaround for H2 #2443 */ 1519 1520 for (i = 0 ; i < TPC_MAX_NUM ; i++) 1521 _goya_tpc_mbist_workaround(hdev, i); 1522 1523 goya->hw_cap_initialized |= HW_CAP_TPC_MBIST; 1524 } 1525 1526 /* 1527 * goya_init_golden_registers - Initialize golden registers 1528 * 1529 * @hdev: pointer to hl_device structure 1530 * 1531 * Initialize the H/W registers of the device 1532 * 1533 */ 1534 static void goya_init_golden_registers(struct hl_device *hdev) 1535 { 1536 struct goya_device *goya = hdev->asic_specific; 1537 u32 polynom[10], tpc_intr_mask, offset; 1538 int i; 1539 1540 if (goya->hw_cap_initialized & HW_CAP_GOLDEN) 1541 return; 1542 1543 polynom[0] = 0x00020080; 1544 polynom[1] = 0x00401000; 1545 polynom[2] = 0x00200800; 1546 polynom[3] = 0x00002000; 1547 polynom[4] = 0x00080200; 1548 polynom[5] = 0x00040100; 1549 polynom[6] = 0x00100400; 1550 polynom[7] = 0x00004000; 1551 polynom[8] = 0x00010000; 1552 polynom[9] = 0x00008000; 1553 1554 /* Mask all arithmetic interrupts from TPC */ 1555 tpc_intr_mask = 0x7FFF; 1556 1557 for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x20000) { 1558 WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302); 1559 WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302); 1560 WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302); 1561 WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302); 1562 WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302); 1563 1564 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204); 1565 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204); 1566 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204); 1567 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204); 1568 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204); 1569 1570 1571 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206); 1572 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206); 1573 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206); 1574 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207); 1575 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207); 1576 1577 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207); 1578 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207); 1579 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206); 1580 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206); 1581 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206); 1582 1583 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101); 1584 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102); 1585 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103); 1586 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104); 1587 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105); 1588 1589 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105); 1590 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104); 1591 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103); 1592 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102); 1593 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101); 1594 } 1595 1596 WREG32(mmMME_STORE_MAX_CREDIT, 0x21); 1597 WREG32(mmMME_AGU, 0x0f0f0f10); 1598 WREG32(mmMME_SEI_MASK, ~0x0); 1599 1600 WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101); 1601 WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101); 1602 WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101); 1603 WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101); 1604 WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101); 1605 WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701); 1606 WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401); 1607 WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401); 1608 WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301); 1609 WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101); 1610 WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101); 1611 WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105); 1612 WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501); 1613 WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501); 1614 WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301); 1615 WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401); 1616 WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101); 1617 WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101); 1618 WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202); 1619 WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101); 1620 WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201); 1621 WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701); 1622 WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101); 1623 WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101); 1624 WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101); 1625 WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101); 1626 WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701); 1627 WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201); 1628 WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101); 1629 WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102); 1630 WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701); 1631 WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701); 1632 WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707); 1633 WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201); 1634 WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201); 1635 WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201); 1636 WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102); 1637 WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102); 1638 WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102); 1639 WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102); 1640 WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102); 1641 WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107); 1642 WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106); 1643 WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102); 1644 WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102); 1645 WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102); 1646 WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102); 1647 WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102); 1648 WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702); 1649 WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702); 1650 WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602); 1651 WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402); 1652 WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202); 1653 WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102); 1654 WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401); 1655 WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401); 1656 WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401); 1657 WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401); 1658 WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401); 1659 WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401); 1660 WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101); 1661 WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101); 1662 WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101); 1663 WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101); 1664 WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101); 1665 WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107); 1666 WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107); 1667 WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101); 1668 WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101); 1669 WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101); 1670 WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101); 1671 WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101); 1672 WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501); 1673 WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501); 1674 WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301); 1675 WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401); 1676 WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101); 1677 WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101); 1678 WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101); 1679 WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101); 1680 WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101); 1681 WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101); 1682 WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101); 1683 WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101); 1684 1685 WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101); 1686 WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101); 1687 WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101); 1688 WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102); 1689 WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101); 1690 WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202); 1691 WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201); 1692 WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201); 1693 WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202); 1694 WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101); 1695 WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101); 1696 WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101); 1697 1698 WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101); 1699 WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101); 1700 WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201); 1701 WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102); 1702 WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101); 1703 WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202); 1704 WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201); 1705 WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201); 1706 WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202); 1707 WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101); 1708 WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101); 1709 WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101); 1710 1711 WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101); 1712 WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101); 1713 WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301); 1714 WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102); 1715 WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101); 1716 WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301); 1717 WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201); 1718 WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201); 1719 WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402); 1720 WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101); 1721 WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101); 1722 WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401); 1723 1724 WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101); 1725 WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101); 1726 WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401); 1727 WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102); 1728 WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101); 1729 WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702); 1730 WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201); 1731 WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201); 1732 WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602); 1733 WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101); 1734 WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101); 1735 WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301); 1736 1737 WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101); 1738 WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101); 1739 WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501); 1740 WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102); 1741 WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101); 1742 WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602); 1743 WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201); 1744 WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201); 1745 WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702); 1746 WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101); 1747 WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101); 1748 WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501); 1749 1750 WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101); 1751 WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101); 1752 WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601); 1753 WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101); 1754 WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101); 1755 WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702); 1756 WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101); 1757 WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101); 1758 WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702); 1759 WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101); 1760 WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101); 1761 WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501); 1762 1763 for (i = 0, offset = 0 ; i < 10 ; i++, offset += 4) { 1764 WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1765 WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1766 WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1767 WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1768 WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1769 WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1770 1771 WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1772 WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1773 WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1774 WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1775 WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1776 WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1777 WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1778 WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1779 1780 WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1781 WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); 1782 } 1783 1784 for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x40000) { 1785 WREG32(mmMME1_RTR_SCRAMB_EN + offset, 1786 1 << MME1_RTR_SCRAMB_EN_VAL_SHIFT); 1787 WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset, 1788 1 << MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT); 1789 } 1790 1791 for (i = 0, offset = 0 ; i < 8 ; i++, offset += 0x40000) { 1792 /* 1793 * Workaround for Bug H2 #2441 : 1794 * "ST.NOP set trace event illegal opcode" 1795 */ 1796 WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask); 1797 1798 WREG32(mmTPC0_NRTR_SCRAMB_EN + offset, 1799 1 << TPC0_NRTR_SCRAMB_EN_VAL_SHIFT); 1800 WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset, 1801 1 << TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT); 1802 1803 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, offset, 1804 ICACHE_FETCH_LINE_NUM, 2); 1805 } 1806 1807 WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT); 1808 WREG32(mmDMA_NRTR_NON_LIN_SCRAMB, 1809 1 << DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT); 1810 1811 WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT); 1812 WREG32(mmPCI_NRTR_NON_LIN_SCRAMB, 1813 1 << PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT); 1814 1815 /* 1816 * Workaround for H2 #HW-23 bug 1817 * Set DMA max outstanding read requests to 240 on DMA CH 1. 1818 * This limitation is still large enough to not affect Gen4 bandwidth. 1819 * We need to only limit that DMA channel because the user can only read 1820 * from Host using DMA CH 1 1821 */ 1822 WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0); 1823 1824 WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020); 1825 1826 goya->hw_cap_initialized |= HW_CAP_GOLDEN; 1827 } 1828 1829 static void goya_init_mme_qman(struct hl_device *hdev) 1830 { 1831 u32 mtr_base_lo, mtr_base_hi; 1832 u32 so_base_lo, so_base_hi; 1833 u32 gic_base_lo, gic_base_hi; 1834 u64 qman_base_addr; 1835 1836 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); 1837 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); 1838 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); 1839 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); 1840 1841 gic_base_lo = 1842 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); 1843 gic_base_hi = 1844 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); 1845 1846 qman_base_addr = hdev->asic_prop.sram_base_address + 1847 MME_QMAN_BASE_OFFSET; 1848 1849 WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr)); 1850 WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr)); 1851 WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH)); 1852 WREG32(mmMME_QM_PQ_PI, 0); 1853 WREG32(mmMME_QM_PQ_CI, 0); 1854 WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0); 1855 WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4); 1856 WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8); 1857 WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC); 1858 1859 WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo); 1860 WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi); 1861 WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo); 1862 WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi); 1863 1864 /* QMAN CQ has 8 cache lines */ 1865 WREG32(mmMME_QM_CQ_CFG1, 0x00080008); 1866 1867 WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo); 1868 WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi); 1869 1870 WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM); 1871 1872 WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN); 1873 1874 WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT); 1875 1876 WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE); 1877 } 1878 1879 static void goya_init_mme_cmdq(struct hl_device *hdev) 1880 { 1881 u32 mtr_base_lo, mtr_base_hi; 1882 u32 so_base_lo, so_base_hi; 1883 u32 gic_base_lo, gic_base_hi; 1884 1885 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); 1886 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); 1887 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); 1888 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); 1889 1890 gic_base_lo = 1891 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); 1892 gic_base_hi = 1893 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); 1894 1895 WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo); 1896 WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi); 1897 WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo); 1898 WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi); 1899 1900 /* CMDQ CQ has 20 cache lines */ 1901 WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014); 1902 1903 WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo); 1904 WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi); 1905 1906 WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ); 1907 1908 WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN); 1909 1910 WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT); 1911 1912 WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE); 1913 } 1914 1915 void goya_init_mme_qmans(struct hl_device *hdev) 1916 { 1917 struct goya_device *goya = hdev->asic_specific; 1918 u32 so_base_lo, so_base_hi; 1919 1920 if (goya->hw_cap_initialized & HW_CAP_MME) 1921 return; 1922 1923 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); 1924 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); 1925 1926 WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo); 1927 WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi); 1928 1929 goya_init_mme_qman(hdev); 1930 goya_init_mme_cmdq(hdev); 1931 1932 goya->hw_cap_initialized |= HW_CAP_MME; 1933 } 1934 1935 static void goya_init_tpc_qman(struct hl_device *hdev, u32 base_off, int tpc_id) 1936 { 1937 u32 mtr_base_lo, mtr_base_hi; 1938 u32 so_base_lo, so_base_hi; 1939 u32 gic_base_lo, gic_base_hi; 1940 u64 qman_base_addr; 1941 u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI); 1942 1943 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); 1944 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); 1945 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); 1946 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); 1947 1948 gic_base_lo = 1949 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); 1950 gic_base_hi = 1951 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); 1952 1953 qman_base_addr = hdev->asic_prop.sram_base_address + base_off; 1954 1955 WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr)); 1956 WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr)); 1957 WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH)); 1958 WREG32(mmTPC0_QM_PQ_PI + reg_off, 0); 1959 WREG32(mmTPC0_QM_PQ_CI + reg_off, 0); 1960 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0); 1961 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4); 1962 WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8); 1963 WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC); 1964 1965 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); 1966 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); 1967 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); 1968 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); 1969 1970 WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008); 1971 1972 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo); 1973 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi); 1974 1975 WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off, 1976 GOYA_ASYNC_EVENT_ID_TPC0_QM + tpc_id); 1977 1978 WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN); 1979 1980 WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT); 1981 1982 WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE); 1983 } 1984 1985 static void goya_init_tpc_cmdq(struct hl_device *hdev, int tpc_id) 1986 { 1987 u32 mtr_base_lo, mtr_base_hi; 1988 u32 so_base_lo, so_base_hi; 1989 u32 gic_base_lo, gic_base_hi; 1990 u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1); 1991 1992 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); 1993 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); 1994 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); 1995 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); 1996 1997 gic_base_lo = 1998 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); 1999 gic_base_hi = 2000 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); 2001 2002 WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); 2003 WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); 2004 WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); 2005 WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); 2006 2007 WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014); 2008 2009 WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo); 2010 WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi); 2011 2012 WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off, 2013 GOYA_ASYNC_EVENT_ID_TPC0_CMDQ + tpc_id); 2014 2015 WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN); 2016 2017 WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT); 2018 2019 WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE); 2020 } 2021 2022 void goya_init_tpc_qmans(struct hl_device *hdev) 2023 { 2024 struct goya_device *goya = hdev->asic_specific; 2025 u32 so_base_lo, so_base_hi; 2026 u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW - 2027 mmTPC0_CFG_SM_BASE_ADDRESS_LOW; 2028 int i; 2029 2030 if (goya->hw_cap_initialized & HW_CAP_TPC) 2031 return; 2032 2033 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); 2034 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); 2035 2036 for (i = 0 ; i < TPC_MAX_NUM ; i++) { 2037 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off, 2038 so_base_lo); 2039 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off, 2040 so_base_hi); 2041 } 2042 2043 goya_init_tpc_qman(hdev, TPC0_QMAN_BASE_OFFSET, 0); 2044 goya_init_tpc_qman(hdev, TPC1_QMAN_BASE_OFFSET, 1); 2045 goya_init_tpc_qman(hdev, TPC2_QMAN_BASE_OFFSET, 2); 2046 goya_init_tpc_qman(hdev, TPC3_QMAN_BASE_OFFSET, 3); 2047 goya_init_tpc_qman(hdev, TPC4_QMAN_BASE_OFFSET, 4); 2048 goya_init_tpc_qman(hdev, TPC5_QMAN_BASE_OFFSET, 5); 2049 goya_init_tpc_qman(hdev, TPC6_QMAN_BASE_OFFSET, 6); 2050 goya_init_tpc_qman(hdev, TPC7_QMAN_BASE_OFFSET, 7); 2051 2052 for (i = 0 ; i < TPC_MAX_NUM ; i++) 2053 goya_init_tpc_cmdq(hdev, i); 2054 2055 goya->hw_cap_initialized |= HW_CAP_TPC; 2056 } 2057 2058 /* 2059 * goya_disable_internal_queues - Disable internal queues 2060 * 2061 * @hdev: pointer to hl_device structure 2062 * 2063 */ 2064 static void goya_disable_internal_queues(struct hl_device *hdev) 2065 { 2066 struct goya_device *goya = hdev->asic_specific; 2067 2068 if (!(goya->hw_cap_initialized & HW_CAP_MME)) 2069 goto disable_tpc; 2070 2071 WREG32(mmMME_QM_GLBL_CFG0, 0); 2072 WREG32(mmMME_CMDQ_GLBL_CFG0, 0); 2073 2074 disable_tpc: 2075 if (!(goya->hw_cap_initialized & HW_CAP_TPC)) 2076 return; 2077 2078 WREG32(mmTPC0_QM_GLBL_CFG0, 0); 2079 WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0); 2080 2081 WREG32(mmTPC1_QM_GLBL_CFG0, 0); 2082 WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0); 2083 2084 WREG32(mmTPC2_QM_GLBL_CFG0, 0); 2085 WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0); 2086 2087 WREG32(mmTPC3_QM_GLBL_CFG0, 0); 2088 WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0); 2089 2090 WREG32(mmTPC4_QM_GLBL_CFG0, 0); 2091 WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0); 2092 2093 WREG32(mmTPC5_QM_GLBL_CFG0, 0); 2094 WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0); 2095 2096 WREG32(mmTPC6_QM_GLBL_CFG0, 0); 2097 WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0); 2098 2099 WREG32(mmTPC7_QM_GLBL_CFG0, 0); 2100 WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0); 2101 } 2102 2103 /* 2104 * goya_stop_internal_queues - Stop internal queues 2105 * 2106 * @hdev: pointer to hl_device structure 2107 * 2108 * Returns 0 on success 2109 * 2110 */ 2111 static int goya_stop_internal_queues(struct hl_device *hdev) 2112 { 2113 struct goya_device *goya = hdev->asic_specific; 2114 int rc, retval = 0; 2115 2116 if (!(goya->hw_cap_initialized & HW_CAP_MME)) 2117 goto stop_tpc; 2118 2119 /* 2120 * Each queue (QMAN) is a separate H/W logic. That means that each 2121 * QMAN can be stopped independently and failure to stop one does NOT 2122 * mandate we should not try to stop other QMANs 2123 */ 2124 2125 rc = goya_stop_queue(hdev, 2126 mmMME_QM_GLBL_CFG1, 2127 mmMME_QM_CP_STS, 2128 mmMME_QM_GLBL_STS0); 2129 2130 if (rc) { 2131 dev_err(hdev->dev, "failed to stop MME QMAN\n"); 2132 retval = -EIO; 2133 } 2134 2135 rc = goya_stop_queue(hdev, 2136 mmMME_CMDQ_GLBL_CFG1, 2137 mmMME_CMDQ_CP_STS, 2138 mmMME_CMDQ_GLBL_STS0); 2139 2140 if (rc) { 2141 dev_err(hdev->dev, "failed to stop MME CMDQ\n"); 2142 retval = -EIO; 2143 } 2144 2145 stop_tpc: 2146 if (!(goya->hw_cap_initialized & HW_CAP_TPC)) 2147 return retval; 2148 2149 rc = goya_stop_queue(hdev, 2150 mmTPC0_QM_GLBL_CFG1, 2151 mmTPC0_QM_CP_STS, 2152 mmTPC0_QM_GLBL_STS0); 2153 2154 if (rc) { 2155 dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n"); 2156 retval = -EIO; 2157 } 2158 2159 rc = goya_stop_queue(hdev, 2160 mmTPC0_CMDQ_GLBL_CFG1, 2161 mmTPC0_CMDQ_CP_STS, 2162 mmTPC0_CMDQ_GLBL_STS0); 2163 2164 if (rc) { 2165 dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n"); 2166 retval = -EIO; 2167 } 2168 2169 rc = goya_stop_queue(hdev, 2170 mmTPC1_QM_GLBL_CFG1, 2171 mmTPC1_QM_CP_STS, 2172 mmTPC1_QM_GLBL_STS0); 2173 2174 if (rc) { 2175 dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n"); 2176 retval = -EIO; 2177 } 2178 2179 rc = goya_stop_queue(hdev, 2180 mmTPC1_CMDQ_GLBL_CFG1, 2181 mmTPC1_CMDQ_CP_STS, 2182 mmTPC1_CMDQ_GLBL_STS0); 2183 2184 if (rc) { 2185 dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n"); 2186 retval = -EIO; 2187 } 2188 2189 rc = goya_stop_queue(hdev, 2190 mmTPC2_QM_GLBL_CFG1, 2191 mmTPC2_QM_CP_STS, 2192 mmTPC2_QM_GLBL_STS0); 2193 2194 if (rc) { 2195 dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n"); 2196 retval = -EIO; 2197 } 2198 2199 rc = goya_stop_queue(hdev, 2200 mmTPC2_CMDQ_GLBL_CFG1, 2201 mmTPC2_CMDQ_CP_STS, 2202 mmTPC2_CMDQ_GLBL_STS0); 2203 2204 if (rc) { 2205 dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n"); 2206 retval = -EIO; 2207 } 2208 2209 rc = goya_stop_queue(hdev, 2210 mmTPC3_QM_GLBL_CFG1, 2211 mmTPC3_QM_CP_STS, 2212 mmTPC3_QM_GLBL_STS0); 2213 2214 if (rc) { 2215 dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n"); 2216 retval = -EIO; 2217 } 2218 2219 rc = goya_stop_queue(hdev, 2220 mmTPC3_CMDQ_GLBL_CFG1, 2221 mmTPC3_CMDQ_CP_STS, 2222 mmTPC3_CMDQ_GLBL_STS0); 2223 2224 if (rc) { 2225 dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n"); 2226 retval = -EIO; 2227 } 2228 2229 rc = goya_stop_queue(hdev, 2230 mmTPC4_QM_GLBL_CFG1, 2231 mmTPC4_QM_CP_STS, 2232 mmTPC4_QM_GLBL_STS0); 2233 2234 if (rc) { 2235 dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n"); 2236 retval = -EIO; 2237 } 2238 2239 rc = goya_stop_queue(hdev, 2240 mmTPC4_CMDQ_GLBL_CFG1, 2241 mmTPC4_CMDQ_CP_STS, 2242 mmTPC4_CMDQ_GLBL_STS0); 2243 2244 if (rc) { 2245 dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n"); 2246 retval = -EIO; 2247 } 2248 2249 rc = goya_stop_queue(hdev, 2250 mmTPC5_QM_GLBL_CFG1, 2251 mmTPC5_QM_CP_STS, 2252 mmTPC5_QM_GLBL_STS0); 2253 2254 if (rc) { 2255 dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n"); 2256 retval = -EIO; 2257 } 2258 2259 rc = goya_stop_queue(hdev, 2260 mmTPC5_CMDQ_GLBL_CFG1, 2261 mmTPC5_CMDQ_CP_STS, 2262 mmTPC5_CMDQ_GLBL_STS0); 2263 2264 if (rc) { 2265 dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n"); 2266 retval = -EIO; 2267 } 2268 2269 rc = goya_stop_queue(hdev, 2270 mmTPC6_QM_GLBL_CFG1, 2271 mmTPC6_QM_CP_STS, 2272 mmTPC6_QM_GLBL_STS0); 2273 2274 if (rc) { 2275 dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n"); 2276 retval = -EIO; 2277 } 2278 2279 rc = goya_stop_queue(hdev, 2280 mmTPC6_CMDQ_GLBL_CFG1, 2281 mmTPC6_CMDQ_CP_STS, 2282 mmTPC6_CMDQ_GLBL_STS0); 2283 2284 if (rc) { 2285 dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n"); 2286 retval = -EIO; 2287 } 2288 2289 rc = goya_stop_queue(hdev, 2290 mmTPC7_QM_GLBL_CFG1, 2291 mmTPC7_QM_CP_STS, 2292 mmTPC7_QM_GLBL_STS0); 2293 2294 if (rc) { 2295 dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n"); 2296 retval = -EIO; 2297 } 2298 2299 rc = goya_stop_queue(hdev, 2300 mmTPC7_CMDQ_GLBL_CFG1, 2301 mmTPC7_CMDQ_CP_STS, 2302 mmTPC7_CMDQ_GLBL_STS0); 2303 2304 if (rc) { 2305 dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n"); 2306 retval = -EIO; 2307 } 2308 2309 return retval; 2310 } 2311 2312 static void goya_dma_stall(struct hl_device *hdev) 2313 { 2314 struct goya_device *goya = hdev->asic_specific; 2315 2316 if (!(goya->hw_cap_initialized & HW_CAP_DMA)) 2317 return; 2318 2319 WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT); 2320 WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT); 2321 WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT); 2322 WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT); 2323 WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT); 2324 } 2325 2326 static void goya_tpc_stall(struct hl_device *hdev) 2327 { 2328 struct goya_device *goya = hdev->asic_specific; 2329 2330 if (!(goya->hw_cap_initialized & HW_CAP_TPC)) 2331 return; 2332 2333 WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); 2334 WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT); 2335 WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT); 2336 WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT); 2337 WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT); 2338 WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT); 2339 WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT); 2340 WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT); 2341 } 2342 2343 static void goya_mme_stall(struct hl_device *hdev) 2344 { 2345 struct goya_device *goya = hdev->asic_specific; 2346 2347 if (!(goya->hw_cap_initialized & HW_CAP_MME)) 2348 return; 2349 2350 WREG32(mmMME_STALL, 0xFFFFFFFF); 2351 } 2352 2353 static int goya_enable_msix(struct hl_device *hdev) 2354 { 2355 struct goya_device *goya = hdev->asic_specific; 2356 int cq_cnt = hdev->asic_prop.completion_queues_count; 2357 int rc, i, irq_cnt_init, irq; 2358 2359 if (goya->hw_cap_initialized & HW_CAP_MSIX) 2360 return 0; 2361 2362 rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES, 2363 GOYA_MSIX_ENTRIES, PCI_IRQ_MSIX); 2364 if (rc < 0) { 2365 dev_err(hdev->dev, 2366 "MSI-X: Failed to enable support -- %d/%d\n", 2367 GOYA_MSIX_ENTRIES, rc); 2368 return rc; 2369 } 2370 2371 for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) { 2372 irq = pci_irq_vector(hdev->pdev, i); 2373 rc = request_irq(irq, hl_irq_handler_cq, 0, goya_irq_name[i], 2374 &hdev->completion_queue[i]); 2375 if (rc) { 2376 dev_err(hdev->dev, "Failed to request IRQ %d", irq); 2377 goto free_irqs; 2378 } 2379 } 2380 2381 irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX); 2382 2383 rc = request_irq(irq, hl_irq_handler_eq, 0, 2384 goya_irq_name[GOYA_EVENT_QUEUE_MSIX_IDX], 2385 &hdev->event_queue); 2386 if (rc) { 2387 dev_err(hdev->dev, "Failed to request IRQ %d", irq); 2388 goto free_irqs; 2389 } 2390 2391 goya->hw_cap_initialized |= HW_CAP_MSIX; 2392 return 0; 2393 2394 free_irqs: 2395 for (i = 0 ; i < irq_cnt_init ; i++) 2396 free_irq(pci_irq_vector(hdev->pdev, i), 2397 &hdev->completion_queue[i]); 2398 2399 pci_free_irq_vectors(hdev->pdev); 2400 return rc; 2401 } 2402 2403 static void goya_sync_irqs(struct hl_device *hdev) 2404 { 2405 struct goya_device *goya = hdev->asic_specific; 2406 int i; 2407 2408 if (!(goya->hw_cap_initialized & HW_CAP_MSIX)) 2409 return; 2410 2411 /* Wait for all pending IRQs to be finished */ 2412 for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) 2413 synchronize_irq(pci_irq_vector(hdev->pdev, i)); 2414 2415 synchronize_irq(pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX)); 2416 } 2417 2418 static void goya_disable_msix(struct hl_device *hdev) 2419 { 2420 struct goya_device *goya = hdev->asic_specific; 2421 int i, irq; 2422 2423 if (!(goya->hw_cap_initialized & HW_CAP_MSIX)) 2424 return; 2425 2426 goya_sync_irqs(hdev); 2427 2428 irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX); 2429 free_irq(irq, &hdev->event_queue); 2430 2431 for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) { 2432 irq = pci_irq_vector(hdev->pdev, i); 2433 free_irq(irq, &hdev->completion_queue[i]); 2434 } 2435 2436 pci_free_irq_vectors(hdev->pdev); 2437 2438 goya->hw_cap_initialized &= ~HW_CAP_MSIX; 2439 } 2440 2441 static void goya_enable_timestamp(struct hl_device *hdev) 2442 { 2443 /* Disable the timestamp counter */ 2444 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0); 2445 2446 /* Zero the lower/upper parts of the 64-bit counter */ 2447 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0); 2448 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0); 2449 2450 /* Enable the counter */ 2451 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1); 2452 } 2453 2454 static void goya_disable_timestamp(struct hl_device *hdev) 2455 { 2456 /* Disable the timestamp counter */ 2457 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0); 2458 } 2459 2460 static void goya_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_reset) 2461 { 2462 u32 wait_timeout_ms; 2463 2464 if (hdev->pldm) 2465 wait_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC; 2466 else 2467 wait_timeout_ms = GOYA_RESET_WAIT_MSEC; 2468 2469 goya_stop_external_queues(hdev); 2470 goya_stop_internal_queues(hdev); 2471 2472 msleep(wait_timeout_ms); 2473 2474 goya_dma_stall(hdev); 2475 goya_tpc_stall(hdev); 2476 goya_mme_stall(hdev); 2477 2478 msleep(wait_timeout_ms); 2479 2480 goya_disable_external_queues(hdev); 2481 goya_disable_internal_queues(hdev); 2482 2483 goya_disable_timestamp(hdev); 2484 2485 if (hard_reset) { 2486 goya_disable_msix(hdev); 2487 goya_mmu_remove_device_cpu_mappings(hdev); 2488 } else { 2489 goya_sync_irqs(hdev); 2490 } 2491 } 2492 2493 /* 2494 * goya_load_firmware_to_device() - Load LINUX FW code to device. 2495 * @hdev: Pointer to hl_device structure. 2496 * 2497 * Copy LINUX fw code from firmware file to HBM BAR. 2498 * 2499 * Return: 0 on success, non-zero for failure. 2500 */ 2501 static int goya_load_firmware_to_device(struct hl_device *hdev) 2502 { 2503 void __iomem *dst; 2504 2505 dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET; 2506 2507 return hl_fw_load_fw_to_device(hdev, GOYA_LINUX_FW_FILE, dst, 0, 0); 2508 } 2509 2510 /* 2511 * goya_load_boot_fit_to_device() - Load boot fit to device. 2512 * @hdev: Pointer to hl_device structure. 2513 * 2514 * Copy boot fit file to SRAM BAR. 2515 * 2516 * Return: 0 on success, non-zero for failure. 2517 */ 2518 static int goya_load_boot_fit_to_device(struct hl_device *hdev) 2519 { 2520 void __iomem *dst; 2521 2522 dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + BOOT_FIT_SRAM_OFFSET; 2523 2524 return hl_fw_load_fw_to_device(hdev, GOYA_BOOT_FIT_FILE, dst, 0, 0); 2525 } 2526 2527 static void goya_init_dynamic_firmware_loader(struct hl_device *hdev) 2528 { 2529 struct dynamic_fw_load_mgr *dynamic_loader; 2530 struct cpu_dyn_regs *dyn_regs; 2531 2532 dynamic_loader = &hdev->fw_loader.dynamic_loader; 2533 2534 /* 2535 * here we update initial values for few specific dynamic regs (as 2536 * before reading the first descriptor from FW those value has to be 2537 * hard-coded) in later stages of the protocol those values will be 2538 * updated automatically by reading the FW descriptor so data there 2539 * will always be up-to-date 2540 */ 2541 dyn_regs = &dynamic_loader->comm_desc.cpu_dyn_regs; 2542 dyn_regs->kmd_msg_to_cpu = 2543 cpu_to_le32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU); 2544 dyn_regs->cpu_cmd_status_to_host = 2545 cpu_to_le32(mmCPU_CMD_STATUS_TO_HOST); 2546 2547 dynamic_loader->wait_for_bl_timeout = GOYA_WAIT_FOR_BL_TIMEOUT_USEC; 2548 } 2549 2550 static void goya_init_static_firmware_loader(struct hl_device *hdev) 2551 { 2552 struct static_fw_load_mgr *static_loader; 2553 2554 static_loader = &hdev->fw_loader.static_loader; 2555 2556 static_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN; 2557 static_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN; 2558 static_loader->kmd_msg_to_cpu_reg = mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU; 2559 static_loader->cpu_cmd_status_to_host_reg = mmCPU_CMD_STATUS_TO_HOST; 2560 static_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS; 2561 static_loader->cpu_boot_dev_status0_reg = mmCPU_BOOT_DEV_STS0; 2562 static_loader->cpu_boot_dev_status1_reg = mmCPU_BOOT_DEV_STS1; 2563 static_loader->boot_err0_reg = mmCPU_BOOT_ERR0; 2564 static_loader->boot_err1_reg = mmCPU_BOOT_ERR1; 2565 static_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET; 2566 static_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET; 2567 static_loader->sram_offset_mask = ~(lower_32_bits(SRAM_BASE_ADDR)); 2568 } 2569 2570 static void goya_init_firmware_preload_params(struct hl_device *hdev) 2571 { 2572 struct pre_fw_load_props *pre_fw_load = &hdev->fw_loader.pre_fw_load; 2573 2574 pre_fw_load->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS; 2575 pre_fw_load->sts_boot_dev_sts0_reg = mmCPU_BOOT_DEV_STS0; 2576 pre_fw_load->sts_boot_dev_sts1_reg = mmCPU_BOOT_DEV_STS1; 2577 pre_fw_load->boot_err0_reg = mmCPU_BOOT_ERR0; 2578 pre_fw_load->boot_err1_reg = mmCPU_BOOT_ERR1; 2579 pre_fw_load->wait_for_preboot_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC; 2580 } 2581 2582 static void goya_init_firmware_loader(struct hl_device *hdev) 2583 { 2584 struct asic_fixed_properties *prop = &hdev->asic_prop; 2585 struct fw_load_mgr *fw_loader = &hdev->fw_loader; 2586 2587 /* fill common fields */ 2588 fw_loader->fw_comp_loaded = FW_TYPE_NONE; 2589 fw_loader->boot_fit_img.image_name = GOYA_BOOT_FIT_FILE; 2590 fw_loader->linux_img.image_name = GOYA_LINUX_FW_FILE; 2591 fw_loader->cpu_timeout = GOYA_CPU_TIMEOUT_USEC; 2592 fw_loader->boot_fit_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC; 2593 fw_loader->skip_bmc = false; 2594 fw_loader->sram_bar_id = SRAM_CFG_BAR_ID; 2595 fw_loader->dram_bar_id = DDR_BAR_ID; 2596 2597 if (prop->dynamic_fw_load) 2598 goya_init_dynamic_firmware_loader(hdev); 2599 else 2600 goya_init_static_firmware_loader(hdev); 2601 } 2602 2603 static int goya_init_cpu(struct hl_device *hdev) 2604 { 2605 struct goya_device *goya = hdev->asic_specific; 2606 int rc; 2607 2608 if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU)) 2609 return 0; 2610 2611 if (goya->hw_cap_initialized & HW_CAP_CPU) 2612 return 0; 2613 2614 /* 2615 * Before pushing u-boot/linux to device, need to set the ddr bar to 2616 * base address of dram 2617 */ 2618 if (goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) { 2619 dev_err(hdev->dev, 2620 "failed to map DDR bar to DRAM base address\n"); 2621 return -EIO; 2622 } 2623 2624 rc = hl_fw_init_cpu(hdev); 2625 2626 if (rc) 2627 return rc; 2628 2629 goya->hw_cap_initialized |= HW_CAP_CPU; 2630 2631 return 0; 2632 } 2633 2634 static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid, 2635 u64 phys_addr) 2636 { 2637 u32 status, timeout_usec; 2638 int rc; 2639 2640 if (hdev->pldm) 2641 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC; 2642 else 2643 timeout_usec = MMU_CONFIG_TIMEOUT_USEC; 2644 2645 WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT); 2646 WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT); 2647 WREG32(MMU_ASID_BUSY, 0x80000000 | asid); 2648 2649 rc = hl_poll_timeout( 2650 hdev, 2651 MMU_ASID_BUSY, 2652 status, 2653 !(status & 0x80000000), 2654 1000, 2655 timeout_usec); 2656 2657 if (rc) { 2658 dev_err(hdev->dev, 2659 "Timeout during MMU hop0 config of asid %d\n", asid); 2660 return rc; 2661 } 2662 2663 return 0; 2664 } 2665 2666 int goya_mmu_init(struct hl_device *hdev) 2667 { 2668 struct asic_fixed_properties *prop = &hdev->asic_prop; 2669 struct goya_device *goya = hdev->asic_specific; 2670 u64 hop0_addr; 2671 int rc, i; 2672 2673 if (!hdev->mmu_enable) 2674 return 0; 2675 2676 if (goya->hw_cap_initialized & HW_CAP_MMU) 2677 return 0; 2678 2679 hdev->dram_default_page_mapping = true; 2680 2681 for (i = 0 ; i < prop->max_asid ; i++) { 2682 hop0_addr = prop->mmu_pgt_addr + 2683 (i * prop->mmu_hop_table_size); 2684 2685 rc = goya_mmu_update_asid_hop0_addr(hdev, i, hop0_addr); 2686 if (rc) { 2687 dev_err(hdev->dev, 2688 "failed to set hop0 addr for asid %d\n", i); 2689 goto err; 2690 } 2691 } 2692 2693 goya->hw_cap_initialized |= HW_CAP_MMU; 2694 2695 /* init MMU cache manage page */ 2696 WREG32(mmSTLB_CACHE_INV_BASE_39_8, 2697 lower_32_bits(MMU_CACHE_MNG_ADDR >> 8)); 2698 WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40); 2699 2700 /* Remove follower feature due to performance bug */ 2701 WREG32_AND(mmSTLB_STLB_FEATURE_EN, 2702 (~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK)); 2703 2704 hl_mmu_invalidate_cache(hdev, true, MMU_OP_USERPTR | MMU_OP_PHYS_PACK); 2705 2706 WREG32(mmMMU_MMU_ENABLE, 1); 2707 WREG32(mmMMU_SPI_MASK, 0xF); 2708 2709 return 0; 2710 2711 err: 2712 return rc; 2713 } 2714 2715 /* 2716 * goya_hw_init - Goya hardware initialization code 2717 * 2718 * @hdev: pointer to hl_device structure 2719 * 2720 * Returns 0 on success 2721 * 2722 */ 2723 static int goya_hw_init(struct hl_device *hdev) 2724 { 2725 struct asic_fixed_properties *prop = &hdev->asic_prop; 2726 int rc; 2727 2728 /* Perform read from the device to make sure device is up */ 2729 RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); 2730 2731 /* 2732 * Let's mark in the H/W that we have reached this point. We check 2733 * this value in the reset_before_init function to understand whether 2734 * we need to reset the chip before doing H/W init. This register is 2735 * cleared by the H/W upon H/W reset 2736 */ 2737 WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY); 2738 2739 rc = goya_init_cpu(hdev); 2740 if (rc) { 2741 dev_err(hdev->dev, "failed to initialize CPU\n"); 2742 return rc; 2743 } 2744 2745 goya_tpc_mbist_workaround(hdev); 2746 2747 goya_init_golden_registers(hdev); 2748 2749 /* 2750 * After CPU initialization is finished, change DDR bar mapping inside 2751 * iATU to point to the start address of the MMU page tables 2752 */ 2753 if (goya_set_ddr_bar_base(hdev, (MMU_PAGE_TABLES_ADDR & 2754 ~(prop->dram_pci_bar_size - 0x1ull))) == U64_MAX) { 2755 dev_err(hdev->dev, 2756 "failed to map DDR bar to MMU page tables\n"); 2757 return -EIO; 2758 } 2759 2760 rc = goya_mmu_init(hdev); 2761 if (rc) 2762 return rc; 2763 2764 goya_init_security(hdev); 2765 2766 goya_init_dma_qmans(hdev); 2767 2768 goya_init_mme_qmans(hdev); 2769 2770 goya_init_tpc_qmans(hdev); 2771 2772 goya_enable_timestamp(hdev); 2773 2774 /* MSI-X must be enabled before CPU queues are initialized */ 2775 rc = goya_enable_msix(hdev); 2776 if (rc) 2777 goto disable_queues; 2778 2779 /* Perform read from the device to flush all MSI-X configuration */ 2780 RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); 2781 2782 return 0; 2783 2784 disable_queues: 2785 goya_disable_internal_queues(hdev); 2786 goya_disable_external_queues(hdev); 2787 2788 return rc; 2789 } 2790 2791 static int goya_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset) 2792 { 2793 struct goya_device *goya = hdev->asic_specific; 2794 u32 reset_timeout_ms, cpu_timeout_ms, status; 2795 2796 if (hdev->pldm) { 2797 reset_timeout_ms = GOYA_PLDM_RESET_TIMEOUT_MSEC; 2798 cpu_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC; 2799 } else { 2800 reset_timeout_ms = GOYA_RESET_TIMEOUT_MSEC; 2801 cpu_timeout_ms = GOYA_CPU_RESET_WAIT_MSEC; 2802 } 2803 2804 if (hard_reset) { 2805 /* I don't know what is the state of the CPU so make sure it is 2806 * stopped in any means necessary 2807 */ 2808 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE); 2809 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, 2810 GOYA_ASYNC_EVENT_ID_HALT_MACHINE); 2811 2812 msleep(cpu_timeout_ms); 2813 2814 goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE); 2815 goya_disable_clk_rlx(hdev); 2816 goya_set_pll_refclk(hdev); 2817 2818 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL); 2819 dev_dbg(hdev->dev, 2820 "Issued HARD reset command, going to wait %dms\n", 2821 reset_timeout_ms); 2822 } else { 2823 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET); 2824 dev_dbg(hdev->dev, 2825 "Issued SOFT reset command, going to wait %dms\n", 2826 reset_timeout_ms); 2827 } 2828 2829 /* 2830 * After hard reset, we can't poll the BTM_FSM register because the PSOC 2831 * itself is in reset. In either reset we need to wait until the reset 2832 * is deasserted 2833 */ 2834 msleep(reset_timeout_ms); 2835 2836 status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM); 2837 if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK) 2838 dev_err(hdev->dev, 2839 "Timeout while waiting for device to reset 0x%x\n", 2840 status); 2841 2842 if (!hard_reset && goya) { 2843 goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME | 2844 HW_CAP_GOLDEN | HW_CAP_TPC); 2845 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, 2846 GOYA_ASYNC_EVENT_ID_SOFT_RESET); 2847 return 0; 2848 } 2849 2850 /* Chicken bit to re-initiate boot sequencer flow */ 2851 WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START, 2852 1 << PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT); 2853 /* Move boot manager FSM to pre boot sequencer init state */ 2854 WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM, 2855 0xA << PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT); 2856 2857 if (goya) { 2858 goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q | 2859 HW_CAP_DDR_0 | HW_CAP_DDR_1 | 2860 HW_CAP_DMA | HW_CAP_MME | 2861 HW_CAP_MMU | HW_CAP_TPC_MBIST | 2862 HW_CAP_GOLDEN | HW_CAP_TPC); 2863 2864 memset(goya->events_stat, 0, sizeof(goya->events_stat)); 2865 } 2866 return 0; 2867 } 2868 2869 int goya_suspend(struct hl_device *hdev) 2870 { 2871 int rc; 2872 2873 rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0); 2874 if (rc) 2875 dev_err(hdev->dev, "Failed to disable PCI access from CPU\n"); 2876 2877 return rc; 2878 } 2879 2880 int goya_resume(struct hl_device *hdev) 2881 { 2882 return goya_init_iatu(hdev); 2883 } 2884 2885 static int goya_mmap(struct hl_device *hdev, struct vm_area_struct *vma, 2886 void *cpu_addr, dma_addr_t dma_addr, size_t size) 2887 { 2888 int rc; 2889 2890 vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | 2891 VM_DONTCOPY | VM_NORESERVE); 2892 2893 rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr, 2894 (dma_addr - HOST_PHYS_BASE), size); 2895 if (rc) 2896 dev_err(hdev->dev, "dma_mmap_coherent error %d", rc); 2897 2898 return rc; 2899 } 2900 2901 void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi) 2902 { 2903 u32 db_reg_offset, db_value; 2904 2905 switch (hw_queue_id) { 2906 case GOYA_QUEUE_ID_DMA_0: 2907 db_reg_offset = mmDMA_QM_0_PQ_PI; 2908 break; 2909 2910 case GOYA_QUEUE_ID_DMA_1: 2911 db_reg_offset = mmDMA_QM_1_PQ_PI; 2912 break; 2913 2914 case GOYA_QUEUE_ID_DMA_2: 2915 db_reg_offset = mmDMA_QM_2_PQ_PI; 2916 break; 2917 2918 case GOYA_QUEUE_ID_DMA_3: 2919 db_reg_offset = mmDMA_QM_3_PQ_PI; 2920 break; 2921 2922 case GOYA_QUEUE_ID_DMA_4: 2923 db_reg_offset = mmDMA_QM_4_PQ_PI; 2924 break; 2925 2926 case GOYA_QUEUE_ID_CPU_PQ: 2927 db_reg_offset = mmCPU_IF_PF_PQ_PI; 2928 break; 2929 2930 case GOYA_QUEUE_ID_MME: 2931 db_reg_offset = mmMME_QM_PQ_PI; 2932 break; 2933 2934 case GOYA_QUEUE_ID_TPC0: 2935 db_reg_offset = mmTPC0_QM_PQ_PI; 2936 break; 2937 2938 case GOYA_QUEUE_ID_TPC1: 2939 db_reg_offset = mmTPC1_QM_PQ_PI; 2940 break; 2941 2942 case GOYA_QUEUE_ID_TPC2: 2943 db_reg_offset = mmTPC2_QM_PQ_PI; 2944 break; 2945 2946 case GOYA_QUEUE_ID_TPC3: 2947 db_reg_offset = mmTPC3_QM_PQ_PI; 2948 break; 2949 2950 case GOYA_QUEUE_ID_TPC4: 2951 db_reg_offset = mmTPC4_QM_PQ_PI; 2952 break; 2953 2954 case GOYA_QUEUE_ID_TPC5: 2955 db_reg_offset = mmTPC5_QM_PQ_PI; 2956 break; 2957 2958 case GOYA_QUEUE_ID_TPC6: 2959 db_reg_offset = mmTPC6_QM_PQ_PI; 2960 break; 2961 2962 case GOYA_QUEUE_ID_TPC7: 2963 db_reg_offset = mmTPC7_QM_PQ_PI; 2964 break; 2965 2966 default: 2967 /* Should never get here */ 2968 dev_err(hdev->dev, "H/W queue %d is invalid. Can't set pi\n", 2969 hw_queue_id); 2970 return; 2971 } 2972 2973 db_value = pi; 2974 2975 /* ring the doorbell */ 2976 WREG32(db_reg_offset, db_value); 2977 2978 if (hw_queue_id == GOYA_QUEUE_ID_CPU_PQ) { 2979 /* make sure device CPU will read latest data from host */ 2980 mb(); 2981 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, 2982 GOYA_ASYNC_EVENT_ID_PI_UPDATE); 2983 } 2984 } 2985 2986 void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd) 2987 { 2988 /* The QMANs are on the SRAM so need to copy to IO space */ 2989 memcpy_toio((void __iomem *) pqe, bd, sizeof(struct hl_bd)); 2990 } 2991 2992 static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size, 2993 dma_addr_t *dma_handle, gfp_t flags) 2994 { 2995 void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size, 2996 dma_handle, flags); 2997 2998 /* Shift to the device's base physical address of host memory */ 2999 if (kernel_addr) 3000 *dma_handle += HOST_PHYS_BASE; 3001 3002 return kernel_addr; 3003 } 3004 3005 static void goya_dma_free_coherent(struct hl_device *hdev, size_t size, 3006 void *cpu_addr, dma_addr_t dma_handle) 3007 { 3008 /* Cancel the device's base physical address of host memory */ 3009 dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE; 3010 3011 dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle); 3012 } 3013 3014 int goya_scrub_device_mem(struct hl_device *hdev) 3015 { 3016 return 0; 3017 } 3018 3019 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id, 3020 dma_addr_t *dma_handle, u16 *queue_len) 3021 { 3022 void *base; 3023 u32 offset; 3024 3025 *dma_handle = hdev->asic_prop.sram_base_address; 3026 3027 base = (__force void *) hdev->pcie_bar[SRAM_CFG_BAR_ID]; 3028 3029 switch (queue_id) { 3030 case GOYA_QUEUE_ID_MME: 3031 offset = MME_QMAN_BASE_OFFSET; 3032 *queue_len = MME_QMAN_LENGTH; 3033 break; 3034 case GOYA_QUEUE_ID_TPC0: 3035 offset = TPC0_QMAN_BASE_OFFSET; 3036 *queue_len = TPC_QMAN_LENGTH; 3037 break; 3038 case GOYA_QUEUE_ID_TPC1: 3039 offset = TPC1_QMAN_BASE_OFFSET; 3040 *queue_len = TPC_QMAN_LENGTH; 3041 break; 3042 case GOYA_QUEUE_ID_TPC2: 3043 offset = TPC2_QMAN_BASE_OFFSET; 3044 *queue_len = TPC_QMAN_LENGTH; 3045 break; 3046 case GOYA_QUEUE_ID_TPC3: 3047 offset = TPC3_QMAN_BASE_OFFSET; 3048 *queue_len = TPC_QMAN_LENGTH; 3049 break; 3050 case GOYA_QUEUE_ID_TPC4: 3051 offset = TPC4_QMAN_BASE_OFFSET; 3052 *queue_len = TPC_QMAN_LENGTH; 3053 break; 3054 case GOYA_QUEUE_ID_TPC5: 3055 offset = TPC5_QMAN_BASE_OFFSET; 3056 *queue_len = TPC_QMAN_LENGTH; 3057 break; 3058 case GOYA_QUEUE_ID_TPC6: 3059 offset = TPC6_QMAN_BASE_OFFSET; 3060 *queue_len = TPC_QMAN_LENGTH; 3061 break; 3062 case GOYA_QUEUE_ID_TPC7: 3063 offset = TPC7_QMAN_BASE_OFFSET; 3064 *queue_len = TPC_QMAN_LENGTH; 3065 break; 3066 default: 3067 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id); 3068 return NULL; 3069 } 3070 3071 base += offset; 3072 *dma_handle += offset; 3073 3074 return base; 3075 } 3076 3077 static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job) 3078 { 3079 struct packet_msg_prot *fence_pkt; 3080 u32 *fence_ptr; 3081 dma_addr_t fence_dma_addr; 3082 struct hl_cb *cb; 3083 u32 tmp, timeout; 3084 int rc; 3085 3086 if (hdev->pldm) 3087 timeout = GOYA_PLDM_QMAN0_TIMEOUT_USEC; 3088 else 3089 timeout = HL_DEVICE_TIMEOUT_USEC; 3090 3091 if (!hdev->asic_funcs->is_device_idle(hdev, NULL, 0, NULL)) { 3092 dev_err_ratelimited(hdev->dev, 3093 "Can't send driver job on QMAN0 because the device is not idle\n"); 3094 return -EBUSY; 3095 } 3096 3097 fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr); 3098 if (!fence_ptr) { 3099 dev_err(hdev->dev, 3100 "Failed to allocate fence memory for QMAN0\n"); 3101 return -ENOMEM; 3102 } 3103 3104 goya_qman0_set_security(hdev, true); 3105 3106 cb = job->patched_cb; 3107 3108 fence_pkt = cb->kernel_address + 3109 job->job_cb_size - sizeof(struct packet_msg_prot); 3110 3111 tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) | 3112 (1 << GOYA_PKT_CTL_EB_SHIFT) | 3113 (1 << GOYA_PKT_CTL_MB_SHIFT); 3114 fence_pkt->ctl = cpu_to_le32(tmp); 3115 fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL); 3116 fence_pkt->addr = cpu_to_le64(fence_dma_addr); 3117 3118 rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_DMA_0, 3119 job->job_cb_size, cb->bus_address); 3120 if (rc) { 3121 dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc); 3122 goto free_fence_ptr; 3123 } 3124 3125 rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, 3126 (tmp == GOYA_QMAN0_FENCE_VAL), 1000, 3127 timeout, true); 3128 3129 hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_DMA_0); 3130 3131 if (rc == -ETIMEDOUT) { 3132 dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp); 3133 goto free_fence_ptr; 3134 } 3135 3136 free_fence_ptr: 3137 hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr); 3138 3139 goya_qman0_set_security(hdev, false); 3140 3141 return rc; 3142 } 3143 3144 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len, 3145 u32 timeout, u64 *result) 3146 { 3147 struct goya_device *goya = hdev->asic_specific; 3148 3149 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) { 3150 if (result) 3151 *result = 0; 3152 return 0; 3153 } 3154 3155 if (!timeout) 3156 timeout = GOYA_MSG_TO_CPU_TIMEOUT_USEC; 3157 3158 return hl_fw_send_cpu_message(hdev, GOYA_QUEUE_ID_CPU_PQ, msg, len, 3159 timeout, result); 3160 } 3161 3162 int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id) 3163 { 3164 struct packet_msg_prot *fence_pkt; 3165 dma_addr_t pkt_dma_addr; 3166 u32 fence_val, tmp; 3167 dma_addr_t fence_dma_addr; 3168 u32 *fence_ptr; 3169 int rc; 3170 3171 fence_val = GOYA_QMAN0_FENCE_VAL; 3172 3173 fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr); 3174 if (!fence_ptr) { 3175 dev_err(hdev->dev, 3176 "Failed to allocate memory for H/W queue %d testing\n", 3177 hw_queue_id); 3178 return -ENOMEM; 3179 } 3180 3181 *fence_ptr = 0; 3182 3183 fence_pkt = hl_asic_dma_pool_zalloc(hdev, sizeof(struct packet_msg_prot), GFP_KERNEL, 3184 &pkt_dma_addr); 3185 if (!fence_pkt) { 3186 dev_err(hdev->dev, 3187 "Failed to allocate packet for H/W queue %d testing\n", 3188 hw_queue_id); 3189 rc = -ENOMEM; 3190 goto free_fence_ptr; 3191 } 3192 3193 tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) | 3194 (1 << GOYA_PKT_CTL_EB_SHIFT) | 3195 (1 << GOYA_PKT_CTL_MB_SHIFT); 3196 fence_pkt->ctl = cpu_to_le32(tmp); 3197 fence_pkt->value = cpu_to_le32(fence_val); 3198 fence_pkt->addr = cpu_to_le64(fence_dma_addr); 3199 3200 rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id, 3201 sizeof(struct packet_msg_prot), 3202 pkt_dma_addr); 3203 if (rc) { 3204 dev_err(hdev->dev, 3205 "Failed to send fence packet to H/W queue %d\n", 3206 hw_queue_id); 3207 goto free_pkt; 3208 } 3209 3210 rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, (tmp == fence_val), 3211 1000, GOYA_TEST_QUEUE_WAIT_USEC, true); 3212 3213 hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id); 3214 3215 if (rc == -ETIMEDOUT) { 3216 dev_err(hdev->dev, 3217 "H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n", 3218 hw_queue_id, (unsigned long long) fence_dma_addr, tmp); 3219 rc = -EIO; 3220 } 3221 3222 free_pkt: 3223 hl_asic_dma_pool_free(hdev, (void *) fence_pkt, pkt_dma_addr); 3224 free_fence_ptr: 3225 hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr); 3226 return rc; 3227 } 3228 3229 int goya_test_cpu_queue(struct hl_device *hdev) 3230 { 3231 struct goya_device *goya = hdev->asic_specific; 3232 3233 /* 3234 * check capability here as send_cpu_message() won't update the result 3235 * value if no capability 3236 */ 3237 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) 3238 return 0; 3239 3240 return hl_fw_test_cpu_queue(hdev); 3241 } 3242 3243 int goya_test_queues(struct hl_device *hdev) 3244 { 3245 int i, rc, ret_val = 0; 3246 3247 for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) { 3248 rc = goya_test_queue(hdev, i); 3249 if (rc) 3250 ret_val = -EINVAL; 3251 } 3252 3253 return ret_val; 3254 } 3255 3256 static void *goya_dma_pool_zalloc(struct hl_device *hdev, size_t size, 3257 gfp_t mem_flags, dma_addr_t *dma_handle) 3258 { 3259 void *kernel_addr; 3260 3261 if (size > GOYA_DMA_POOL_BLK_SIZE) 3262 return NULL; 3263 3264 kernel_addr = dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle); 3265 3266 /* Shift to the device's base physical address of host memory */ 3267 if (kernel_addr) 3268 *dma_handle += HOST_PHYS_BASE; 3269 3270 return kernel_addr; 3271 } 3272 3273 static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr, 3274 dma_addr_t dma_addr) 3275 { 3276 /* Cancel the device's base physical address of host memory */ 3277 dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE; 3278 3279 dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr); 3280 } 3281 3282 void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size, 3283 dma_addr_t *dma_handle) 3284 { 3285 void *vaddr; 3286 3287 vaddr = hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle); 3288 *dma_handle = (*dma_handle) - hdev->cpu_accessible_dma_address + 3289 VA_CPU_ACCESSIBLE_MEM_ADDR; 3290 3291 return vaddr; 3292 } 3293 3294 void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, 3295 void *vaddr) 3296 { 3297 hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr); 3298 } 3299 3300 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt) 3301 { 3302 struct scatterlist *sg, *sg_next_iter; 3303 u32 count, dma_desc_cnt; 3304 u64 len, len_next; 3305 dma_addr_t addr, addr_next; 3306 3307 dma_desc_cnt = 0; 3308 3309 for_each_sgtable_dma_sg(sgt, sg, count) { 3310 len = sg_dma_len(sg); 3311 addr = sg_dma_address(sg); 3312 3313 if (len == 0) 3314 break; 3315 3316 while ((count + 1) < sgt->nents) { 3317 sg_next_iter = sg_next(sg); 3318 len_next = sg_dma_len(sg_next_iter); 3319 addr_next = sg_dma_address(sg_next_iter); 3320 3321 if (len_next == 0) 3322 break; 3323 3324 if ((addr + len == addr_next) && 3325 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) { 3326 len += len_next; 3327 count++; 3328 sg = sg_next_iter; 3329 } else { 3330 break; 3331 } 3332 } 3333 3334 dma_desc_cnt++; 3335 } 3336 3337 return dma_desc_cnt * sizeof(struct packet_lin_dma); 3338 } 3339 3340 static int goya_pin_memory_before_cs(struct hl_device *hdev, 3341 struct hl_cs_parser *parser, 3342 struct packet_lin_dma *user_dma_pkt, 3343 u64 addr, enum dma_data_direction dir) 3344 { 3345 struct hl_userptr *userptr; 3346 int rc; 3347 3348 if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize), 3349 parser->job_userptr_list, &userptr)) 3350 goto already_pinned; 3351 3352 userptr = kzalloc(sizeof(*userptr), GFP_KERNEL); 3353 if (!userptr) 3354 return -ENOMEM; 3355 3356 rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize), 3357 userptr); 3358 if (rc) 3359 goto free_userptr; 3360 3361 list_add_tail(&userptr->job_node, parser->job_userptr_list); 3362 3363 rc = hdev->asic_funcs->asic_dma_map_sgtable(hdev, userptr->sgt, dir); 3364 if (rc) { 3365 dev_err(hdev->dev, "failed to map sgt with DMA region\n"); 3366 goto unpin_memory; 3367 } 3368 3369 userptr->dma_mapped = true; 3370 userptr->dir = dir; 3371 3372 already_pinned: 3373 parser->patched_cb_size += 3374 goya_get_dma_desc_list_size(hdev, userptr->sgt); 3375 3376 return 0; 3377 3378 unpin_memory: 3379 list_del(&userptr->job_node); 3380 hl_unpin_host_memory(hdev, userptr); 3381 free_userptr: 3382 kfree(userptr); 3383 return rc; 3384 } 3385 3386 static int goya_validate_dma_pkt_host(struct hl_device *hdev, 3387 struct hl_cs_parser *parser, 3388 struct packet_lin_dma *user_dma_pkt) 3389 { 3390 u64 device_memory_addr, addr; 3391 enum dma_data_direction dir; 3392 enum hl_goya_dma_direction user_dir; 3393 bool sram_addr = true; 3394 bool skip_host_mem_pin = false; 3395 bool user_memset; 3396 u32 ctl; 3397 int rc = 0; 3398 3399 ctl = le32_to_cpu(user_dma_pkt->ctl); 3400 3401 user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >> 3402 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT; 3403 3404 user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >> 3405 GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT; 3406 3407 switch (user_dir) { 3408 case HL_DMA_HOST_TO_DRAM: 3409 dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n"); 3410 dir = DMA_TO_DEVICE; 3411 sram_addr = false; 3412 addr = le64_to_cpu(user_dma_pkt->src_addr); 3413 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); 3414 if (user_memset) 3415 skip_host_mem_pin = true; 3416 break; 3417 3418 case HL_DMA_DRAM_TO_HOST: 3419 dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n"); 3420 dir = DMA_FROM_DEVICE; 3421 sram_addr = false; 3422 addr = le64_to_cpu(user_dma_pkt->dst_addr); 3423 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); 3424 break; 3425 3426 case HL_DMA_HOST_TO_SRAM: 3427 dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n"); 3428 dir = DMA_TO_DEVICE; 3429 addr = le64_to_cpu(user_dma_pkt->src_addr); 3430 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); 3431 if (user_memset) 3432 skip_host_mem_pin = true; 3433 break; 3434 3435 case HL_DMA_SRAM_TO_HOST: 3436 dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n"); 3437 dir = DMA_FROM_DEVICE; 3438 addr = le64_to_cpu(user_dma_pkt->dst_addr); 3439 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); 3440 break; 3441 default: 3442 dev_err(hdev->dev, "DMA direction %d is unsupported/undefined\n", user_dir); 3443 return -EFAULT; 3444 } 3445 3446 if (sram_addr) { 3447 if (!hl_mem_area_inside_range(device_memory_addr, 3448 le32_to_cpu(user_dma_pkt->tsize), 3449 hdev->asic_prop.sram_user_base_address, 3450 hdev->asic_prop.sram_end_address)) { 3451 3452 dev_err(hdev->dev, 3453 "SRAM address 0x%llx + 0x%x is invalid\n", 3454 device_memory_addr, 3455 user_dma_pkt->tsize); 3456 return -EFAULT; 3457 } 3458 } else { 3459 if (!hl_mem_area_inside_range(device_memory_addr, 3460 le32_to_cpu(user_dma_pkt->tsize), 3461 hdev->asic_prop.dram_user_base_address, 3462 hdev->asic_prop.dram_end_address)) { 3463 3464 dev_err(hdev->dev, 3465 "DRAM address 0x%llx + 0x%x is invalid\n", 3466 device_memory_addr, 3467 user_dma_pkt->tsize); 3468 return -EFAULT; 3469 } 3470 } 3471 3472 if (skip_host_mem_pin) 3473 parser->patched_cb_size += sizeof(*user_dma_pkt); 3474 else { 3475 if ((dir == DMA_TO_DEVICE) && 3476 (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1)) { 3477 dev_err(hdev->dev, 3478 "Can't DMA from host on queue other then 1\n"); 3479 return -EFAULT; 3480 } 3481 3482 rc = goya_pin_memory_before_cs(hdev, parser, user_dma_pkt, 3483 addr, dir); 3484 } 3485 3486 return rc; 3487 } 3488 3489 static int goya_validate_dma_pkt_no_host(struct hl_device *hdev, 3490 struct hl_cs_parser *parser, 3491 struct packet_lin_dma *user_dma_pkt) 3492 { 3493 u64 sram_memory_addr, dram_memory_addr; 3494 enum hl_goya_dma_direction user_dir; 3495 u32 ctl; 3496 3497 ctl = le32_to_cpu(user_dma_pkt->ctl); 3498 user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >> 3499 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT; 3500 3501 if (user_dir == HL_DMA_DRAM_TO_SRAM) { 3502 dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n"); 3503 dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); 3504 sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); 3505 } else { 3506 dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n"); 3507 sram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); 3508 dram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); 3509 } 3510 3511 if (!hl_mem_area_inside_range(sram_memory_addr, 3512 le32_to_cpu(user_dma_pkt->tsize), 3513 hdev->asic_prop.sram_user_base_address, 3514 hdev->asic_prop.sram_end_address)) { 3515 dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n", 3516 sram_memory_addr, user_dma_pkt->tsize); 3517 return -EFAULT; 3518 } 3519 3520 if (!hl_mem_area_inside_range(dram_memory_addr, 3521 le32_to_cpu(user_dma_pkt->tsize), 3522 hdev->asic_prop.dram_user_base_address, 3523 hdev->asic_prop.dram_end_address)) { 3524 dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n", 3525 dram_memory_addr, user_dma_pkt->tsize); 3526 return -EFAULT; 3527 } 3528 3529 parser->patched_cb_size += sizeof(*user_dma_pkt); 3530 3531 return 0; 3532 } 3533 3534 static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev, 3535 struct hl_cs_parser *parser, 3536 struct packet_lin_dma *user_dma_pkt) 3537 { 3538 enum hl_goya_dma_direction user_dir; 3539 u32 ctl; 3540 int rc; 3541 3542 dev_dbg(hdev->dev, "DMA packet details:\n"); 3543 dev_dbg(hdev->dev, "source == 0x%llx\n", 3544 le64_to_cpu(user_dma_pkt->src_addr)); 3545 dev_dbg(hdev->dev, "destination == 0x%llx\n", 3546 le64_to_cpu(user_dma_pkt->dst_addr)); 3547 dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize)); 3548 3549 ctl = le32_to_cpu(user_dma_pkt->ctl); 3550 user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >> 3551 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT; 3552 3553 /* 3554 * Special handling for DMA with size 0. The H/W has a bug where 3555 * this can cause the QMAN DMA to get stuck, so block it here. 3556 */ 3557 if (user_dma_pkt->tsize == 0) { 3558 dev_err(hdev->dev, 3559 "Got DMA with size 0, might reset the device\n"); 3560 return -EINVAL; 3561 } 3562 3563 if ((user_dir == HL_DMA_DRAM_TO_SRAM) || (user_dir == HL_DMA_SRAM_TO_DRAM)) 3564 rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt); 3565 else 3566 rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt); 3567 3568 return rc; 3569 } 3570 3571 static int goya_validate_dma_pkt_mmu(struct hl_device *hdev, 3572 struct hl_cs_parser *parser, 3573 struct packet_lin_dma *user_dma_pkt) 3574 { 3575 dev_dbg(hdev->dev, "DMA packet details:\n"); 3576 dev_dbg(hdev->dev, "source == 0x%llx\n", 3577 le64_to_cpu(user_dma_pkt->src_addr)); 3578 dev_dbg(hdev->dev, "destination == 0x%llx\n", 3579 le64_to_cpu(user_dma_pkt->dst_addr)); 3580 dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize)); 3581 3582 /* 3583 * WA for HW-23. 3584 * We can't allow user to read from Host using QMANs other than 1. 3585 * PMMU and HPMMU addresses are equal, check only one of them. 3586 */ 3587 if (parser->hw_queue_id != GOYA_QUEUE_ID_DMA_1 && 3588 hl_mem_area_inside_range(le64_to_cpu(user_dma_pkt->src_addr), 3589 le32_to_cpu(user_dma_pkt->tsize), 3590 hdev->asic_prop.pmmu.start_addr, 3591 hdev->asic_prop.pmmu.end_addr)) { 3592 dev_err(hdev->dev, 3593 "Can't DMA from host on queue other then 1\n"); 3594 return -EFAULT; 3595 } 3596 3597 if (user_dma_pkt->tsize == 0) { 3598 dev_err(hdev->dev, 3599 "Got DMA with size 0, might reset the device\n"); 3600 return -EINVAL; 3601 } 3602 3603 parser->patched_cb_size += sizeof(*user_dma_pkt); 3604 3605 return 0; 3606 } 3607 3608 static int goya_validate_wreg32(struct hl_device *hdev, 3609 struct hl_cs_parser *parser, 3610 struct packet_wreg32 *wreg_pkt) 3611 { 3612 struct goya_device *goya = hdev->asic_specific; 3613 u32 sob_start_addr, sob_end_addr; 3614 u16 reg_offset; 3615 3616 reg_offset = le32_to_cpu(wreg_pkt->ctl) & 3617 GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK; 3618 3619 dev_dbg(hdev->dev, "WREG32 packet details:\n"); 3620 dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset); 3621 dev_dbg(hdev->dev, "value == 0x%x\n", 3622 le32_to_cpu(wreg_pkt->value)); 3623 3624 if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) { 3625 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n", 3626 reg_offset); 3627 return -EPERM; 3628 } 3629 3630 /* 3631 * With MMU, DMA channels are not secured, so it doesn't matter where 3632 * the WR COMP will be written to because it will go out with 3633 * non-secured property 3634 */ 3635 if (goya->hw_cap_initialized & HW_CAP_MMU) 3636 return 0; 3637 3638 sob_start_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); 3639 sob_end_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1023); 3640 3641 if ((le32_to_cpu(wreg_pkt->value) < sob_start_addr) || 3642 (le32_to_cpu(wreg_pkt->value) > sob_end_addr)) { 3643 3644 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n", 3645 wreg_pkt->value); 3646 return -EPERM; 3647 } 3648 3649 return 0; 3650 } 3651 3652 static int goya_validate_cb(struct hl_device *hdev, 3653 struct hl_cs_parser *parser, bool is_mmu) 3654 { 3655 u32 cb_parsed_length = 0; 3656 int rc = 0; 3657 3658 parser->patched_cb_size = 0; 3659 3660 /* cb_user_size is more than 0 so loop will always be executed */ 3661 while (cb_parsed_length < parser->user_cb_size) { 3662 enum packet_id pkt_id; 3663 u16 pkt_size; 3664 struct goya_packet *user_pkt; 3665 3666 user_pkt = parser->user_cb->kernel_address + cb_parsed_length; 3667 3668 pkt_id = (enum packet_id) ( 3669 (le64_to_cpu(user_pkt->header) & 3670 PACKET_HEADER_PACKET_ID_MASK) >> 3671 PACKET_HEADER_PACKET_ID_SHIFT); 3672 3673 if (!validate_packet_id(pkt_id)) { 3674 dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id); 3675 rc = -EINVAL; 3676 break; 3677 } 3678 3679 pkt_size = goya_packet_sizes[pkt_id]; 3680 cb_parsed_length += pkt_size; 3681 if (cb_parsed_length > parser->user_cb_size) { 3682 dev_err(hdev->dev, 3683 "packet 0x%x is out of CB boundary\n", pkt_id); 3684 rc = -EINVAL; 3685 break; 3686 } 3687 3688 switch (pkt_id) { 3689 case PACKET_WREG_32: 3690 /* 3691 * Although it is validated after copy in patch_cb(), 3692 * need to validate here as well because patch_cb() is 3693 * not called in MMU path while this function is called 3694 */ 3695 rc = goya_validate_wreg32(hdev, 3696 parser, (struct packet_wreg32 *) user_pkt); 3697 parser->patched_cb_size += pkt_size; 3698 break; 3699 3700 case PACKET_WREG_BULK: 3701 dev_err(hdev->dev, 3702 "User not allowed to use WREG_BULK\n"); 3703 rc = -EPERM; 3704 break; 3705 3706 case PACKET_MSG_PROT: 3707 dev_err(hdev->dev, 3708 "User not allowed to use MSG_PROT\n"); 3709 rc = -EPERM; 3710 break; 3711 3712 case PACKET_CP_DMA: 3713 dev_err(hdev->dev, "User not allowed to use CP_DMA\n"); 3714 rc = -EPERM; 3715 break; 3716 3717 case PACKET_STOP: 3718 dev_err(hdev->dev, "User not allowed to use STOP\n"); 3719 rc = -EPERM; 3720 break; 3721 3722 case PACKET_LIN_DMA: 3723 if (is_mmu) 3724 rc = goya_validate_dma_pkt_mmu(hdev, parser, 3725 (struct packet_lin_dma *) user_pkt); 3726 else 3727 rc = goya_validate_dma_pkt_no_mmu(hdev, parser, 3728 (struct packet_lin_dma *) user_pkt); 3729 break; 3730 3731 case PACKET_MSG_LONG: 3732 case PACKET_MSG_SHORT: 3733 case PACKET_FENCE: 3734 case PACKET_NOP: 3735 parser->patched_cb_size += pkt_size; 3736 break; 3737 3738 default: 3739 dev_err(hdev->dev, "Invalid packet header 0x%x\n", 3740 pkt_id); 3741 rc = -EINVAL; 3742 break; 3743 } 3744 3745 if (rc) 3746 break; 3747 } 3748 3749 /* 3750 * The new CB should have space at the end for two MSG_PROT packets: 3751 * 1. A packet that will act as a completion packet 3752 * 2. A packet that will generate MSI-X interrupt 3753 */ 3754 parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2; 3755 3756 return rc; 3757 } 3758 3759 static int goya_patch_dma_packet(struct hl_device *hdev, 3760 struct hl_cs_parser *parser, 3761 struct packet_lin_dma *user_dma_pkt, 3762 struct packet_lin_dma *new_dma_pkt, 3763 u32 *new_dma_pkt_size) 3764 { 3765 struct hl_userptr *userptr; 3766 struct scatterlist *sg, *sg_next_iter; 3767 u32 count, dma_desc_cnt; 3768 u64 len, len_next; 3769 dma_addr_t dma_addr, dma_addr_next; 3770 enum hl_goya_dma_direction user_dir; 3771 u64 device_memory_addr, addr; 3772 enum dma_data_direction dir; 3773 struct sg_table *sgt; 3774 bool skip_host_mem_pin = false; 3775 bool user_memset; 3776 u32 user_rdcomp_mask, user_wrcomp_mask, ctl; 3777 3778 ctl = le32_to_cpu(user_dma_pkt->ctl); 3779 3780 user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >> 3781 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT; 3782 3783 user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >> 3784 GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT; 3785 3786 if ((user_dir == HL_DMA_DRAM_TO_SRAM) || (user_dir == HL_DMA_SRAM_TO_DRAM) || 3787 (user_dma_pkt->tsize == 0)) { 3788 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt)); 3789 *new_dma_pkt_size = sizeof(*new_dma_pkt); 3790 return 0; 3791 } 3792 3793 if ((user_dir == HL_DMA_HOST_TO_DRAM) || (user_dir == HL_DMA_HOST_TO_SRAM)) { 3794 addr = le64_to_cpu(user_dma_pkt->src_addr); 3795 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); 3796 dir = DMA_TO_DEVICE; 3797 if (user_memset) 3798 skip_host_mem_pin = true; 3799 } else { 3800 addr = le64_to_cpu(user_dma_pkt->dst_addr); 3801 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); 3802 dir = DMA_FROM_DEVICE; 3803 } 3804 3805 if ((!skip_host_mem_pin) && 3806 (hl_userptr_is_pinned(hdev, addr, 3807 le32_to_cpu(user_dma_pkt->tsize), 3808 parser->job_userptr_list, &userptr) == false)) { 3809 dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n", 3810 addr, user_dma_pkt->tsize); 3811 return -EFAULT; 3812 } 3813 3814 if ((user_memset) && (dir == DMA_TO_DEVICE)) { 3815 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt)); 3816 *new_dma_pkt_size = sizeof(*user_dma_pkt); 3817 return 0; 3818 } 3819 3820 user_rdcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK; 3821 3822 user_wrcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK; 3823 3824 sgt = userptr->sgt; 3825 dma_desc_cnt = 0; 3826 3827 for_each_sgtable_dma_sg(sgt, sg, count) { 3828 len = sg_dma_len(sg); 3829 dma_addr = sg_dma_address(sg); 3830 3831 if (len == 0) 3832 break; 3833 3834 while ((count + 1) < sgt->nents) { 3835 sg_next_iter = sg_next(sg); 3836 len_next = sg_dma_len(sg_next_iter); 3837 dma_addr_next = sg_dma_address(sg_next_iter); 3838 3839 if (len_next == 0) 3840 break; 3841 3842 if ((dma_addr + len == dma_addr_next) && 3843 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) { 3844 len += len_next; 3845 count++; 3846 sg = sg_next_iter; 3847 } else { 3848 break; 3849 } 3850 } 3851 3852 ctl = le32_to_cpu(user_dma_pkt->ctl); 3853 if (likely(dma_desc_cnt)) 3854 ctl &= ~GOYA_PKT_CTL_EB_MASK; 3855 ctl &= ~(GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK | 3856 GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK); 3857 new_dma_pkt->ctl = cpu_to_le32(ctl); 3858 new_dma_pkt->tsize = cpu_to_le32((u32) len); 3859 3860 if (dir == DMA_TO_DEVICE) { 3861 new_dma_pkt->src_addr = cpu_to_le64(dma_addr); 3862 new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr); 3863 } else { 3864 new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr); 3865 new_dma_pkt->dst_addr = cpu_to_le64(dma_addr); 3866 } 3867 3868 if (!user_memset) 3869 device_memory_addr += len; 3870 dma_desc_cnt++; 3871 new_dma_pkt++; 3872 } 3873 3874 if (!dma_desc_cnt) { 3875 dev_err(hdev->dev, 3876 "Error of 0 SG entries when patching DMA packet\n"); 3877 return -EFAULT; 3878 } 3879 3880 /* Fix the last dma packet - rdcomp/wrcomp must be as user set them */ 3881 new_dma_pkt--; 3882 new_dma_pkt->ctl |= cpu_to_le32(user_rdcomp_mask | user_wrcomp_mask); 3883 3884 *new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma); 3885 3886 return 0; 3887 } 3888 3889 static int goya_patch_cb(struct hl_device *hdev, 3890 struct hl_cs_parser *parser) 3891 { 3892 u32 cb_parsed_length = 0; 3893 u32 cb_patched_cur_length = 0; 3894 int rc = 0; 3895 3896 /* cb_user_size is more than 0 so loop will always be executed */ 3897 while (cb_parsed_length < parser->user_cb_size) { 3898 enum packet_id pkt_id; 3899 u16 pkt_size; 3900 u32 new_pkt_size = 0; 3901 struct goya_packet *user_pkt, *kernel_pkt; 3902 3903 user_pkt = parser->user_cb->kernel_address + cb_parsed_length; 3904 kernel_pkt = parser->patched_cb->kernel_address + 3905 cb_patched_cur_length; 3906 3907 pkt_id = (enum packet_id) ( 3908 (le64_to_cpu(user_pkt->header) & 3909 PACKET_HEADER_PACKET_ID_MASK) >> 3910 PACKET_HEADER_PACKET_ID_SHIFT); 3911 3912 if (!validate_packet_id(pkt_id)) { 3913 dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id); 3914 rc = -EINVAL; 3915 break; 3916 } 3917 3918 pkt_size = goya_packet_sizes[pkt_id]; 3919 cb_parsed_length += pkt_size; 3920 if (cb_parsed_length > parser->user_cb_size) { 3921 dev_err(hdev->dev, 3922 "packet 0x%x is out of CB boundary\n", pkt_id); 3923 rc = -EINVAL; 3924 break; 3925 } 3926 3927 switch (pkt_id) { 3928 case PACKET_LIN_DMA: 3929 rc = goya_patch_dma_packet(hdev, parser, 3930 (struct packet_lin_dma *) user_pkt, 3931 (struct packet_lin_dma *) kernel_pkt, 3932 &new_pkt_size); 3933 cb_patched_cur_length += new_pkt_size; 3934 break; 3935 3936 case PACKET_WREG_32: 3937 memcpy(kernel_pkt, user_pkt, pkt_size); 3938 cb_patched_cur_length += pkt_size; 3939 rc = goya_validate_wreg32(hdev, parser, 3940 (struct packet_wreg32 *) kernel_pkt); 3941 break; 3942 3943 case PACKET_WREG_BULK: 3944 dev_err(hdev->dev, 3945 "User not allowed to use WREG_BULK\n"); 3946 rc = -EPERM; 3947 break; 3948 3949 case PACKET_MSG_PROT: 3950 dev_err(hdev->dev, 3951 "User not allowed to use MSG_PROT\n"); 3952 rc = -EPERM; 3953 break; 3954 3955 case PACKET_CP_DMA: 3956 dev_err(hdev->dev, "User not allowed to use CP_DMA\n"); 3957 rc = -EPERM; 3958 break; 3959 3960 case PACKET_STOP: 3961 dev_err(hdev->dev, "User not allowed to use STOP\n"); 3962 rc = -EPERM; 3963 break; 3964 3965 case PACKET_MSG_LONG: 3966 case PACKET_MSG_SHORT: 3967 case PACKET_FENCE: 3968 case PACKET_NOP: 3969 memcpy(kernel_pkt, user_pkt, pkt_size); 3970 cb_patched_cur_length += pkt_size; 3971 break; 3972 3973 default: 3974 dev_err(hdev->dev, "Invalid packet header 0x%x\n", 3975 pkt_id); 3976 rc = -EINVAL; 3977 break; 3978 } 3979 3980 if (rc) 3981 break; 3982 } 3983 3984 return rc; 3985 } 3986 3987 static int goya_parse_cb_mmu(struct hl_device *hdev, 3988 struct hl_cs_parser *parser) 3989 { 3990 u64 handle; 3991 u32 patched_cb_size; 3992 struct hl_cb *user_cb; 3993 int rc; 3994 3995 /* 3996 * The new CB should have space at the end for two MSG_PROT pkt: 3997 * 1. A packet that will act as a completion packet 3998 * 2. A packet that will generate MSI-X interrupt 3999 */ 4000 parser->patched_cb_size = parser->user_cb_size + 4001 sizeof(struct packet_msg_prot) * 2; 4002 4003 rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx, 4004 parser->patched_cb_size, false, false, 4005 &handle); 4006 4007 if (rc) { 4008 dev_err(hdev->dev, 4009 "Failed to allocate patched CB for DMA CS %d\n", 4010 rc); 4011 return rc; 4012 } 4013 4014 parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle); 4015 /* hl_cb_get should never fail here */ 4016 if (!parser->patched_cb) { 4017 dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle); 4018 rc = -EFAULT; 4019 goto out; 4020 } 4021 4022 /* 4023 * The check that parser->user_cb_size <= parser->user_cb->size was done 4024 * in validate_queue_index(). 4025 */ 4026 memcpy(parser->patched_cb->kernel_address, 4027 parser->user_cb->kernel_address, 4028 parser->user_cb_size); 4029 4030 patched_cb_size = parser->patched_cb_size; 4031 4032 /* validate patched CB instead of user CB */ 4033 user_cb = parser->user_cb; 4034 parser->user_cb = parser->patched_cb; 4035 rc = goya_validate_cb(hdev, parser, true); 4036 parser->user_cb = user_cb; 4037 4038 if (rc) { 4039 hl_cb_put(parser->patched_cb); 4040 goto out; 4041 } 4042 4043 if (patched_cb_size != parser->patched_cb_size) { 4044 dev_err(hdev->dev, "user CB size mismatch\n"); 4045 hl_cb_put(parser->patched_cb); 4046 rc = -EINVAL; 4047 goto out; 4048 } 4049 4050 out: 4051 /* 4052 * Always call cb destroy here because we still have 1 reference 4053 * to it by calling cb_get earlier. After the job will be completed, 4054 * cb_put will release it, but here we want to remove it from the 4055 * idr 4056 */ 4057 hl_cb_destroy(&hdev->kernel_mem_mgr, handle); 4058 4059 return rc; 4060 } 4061 4062 static int goya_parse_cb_no_mmu(struct hl_device *hdev, 4063 struct hl_cs_parser *parser) 4064 { 4065 u64 handle; 4066 int rc; 4067 4068 rc = goya_validate_cb(hdev, parser, false); 4069 4070 if (rc) 4071 goto free_userptr; 4072 4073 rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx, 4074 parser->patched_cb_size, false, false, 4075 &handle); 4076 if (rc) { 4077 dev_err(hdev->dev, 4078 "Failed to allocate patched CB for DMA CS %d\n", rc); 4079 goto free_userptr; 4080 } 4081 4082 parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle); 4083 /* hl_cb_get should never fail here */ 4084 if (!parser->patched_cb) { 4085 dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle); 4086 rc = -EFAULT; 4087 goto out; 4088 } 4089 4090 rc = goya_patch_cb(hdev, parser); 4091 4092 if (rc) 4093 hl_cb_put(parser->patched_cb); 4094 4095 out: 4096 /* 4097 * Always call cb destroy here because we still have 1 reference 4098 * to it by calling cb_get earlier. After the job will be completed, 4099 * cb_put will release it, but here we want to remove it from the 4100 * idr 4101 */ 4102 hl_cb_destroy(&hdev->kernel_mem_mgr, handle); 4103 4104 free_userptr: 4105 if (rc) 4106 hl_userptr_delete_list(hdev, parser->job_userptr_list); 4107 return rc; 4108 } 4109 4110 static int goya_parse_cb_no_ext_queue(struct hl_device *hdev, 4111 struct hl_cs_parser *parser) 4112 { 4113 struct asic_fixed_properties *asic_prop = &hdev->asic_prop; 4114 struct goya_device *goya = hdev->asic_specific; 4115 4116 if (goya->hw_cap_initialized & HW_CAP_MMU) 4117 return 0; 4118 4119 /* For internal queue jobs, just check if CB address is valid */ 4120 if (hl_mem_area_inside_range( 4121 (u64) (uintptr_t) parser->user_cb, 4122 parser->user_cb_size, 4123 asic_prop->sram_user_base_address, 4124 asic_prop->sram_end_address)) 4125 return 0; 4126 4127 if (hl_mem_area_inside_range( 4128 (u64) (uintptr_t) parser->user_cb, 4129 parser->user_cb_size, 4130 asic_prop->dram_user_base_address, 4131 asic_prop->dram_end_address)) 4132 return 0; 4133 4134 dev_err(hdev->dev, 4135 "Internal CB address 0x%px + 0x%x is not in SRAM nor in DRAM\n", 4136 parser->user_cb, parser->user_cb_size); 4137 4138 return -EFAULT; 4139 } 4140 4141 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser) 4142 { 4143 struct goya_device *goya = hdev->asic_specific; 4144 4145 if (parser->queue_type == QUEUE_TYPE_INT) 4146 return goya_parse_cb_no_ext_queue(hdev, parser); 4147 4148 if (goya->hw_cap_initialized & HW_CAP_MMU) 4149 return goya_parse_cb_mmu(hdev, parser); 4150 else 4151 return goya_parse_cb_no_mmu(hdev, parser); 4152 } 4153 4154 void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address, 4155 u32 len, u32 original_len, u64 cq_addr, u32 cq_val, 4156 u32 msix_vec, bool eb) 4157 { 4158 struct packet_msg_prot *cq_pkt; 4159 u32 tmp; 4160 4161 cq_pkt = kernel_address + len - (sizeof(struct packet_msg_prot) * 2); 4162 4163 tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) | 4164 (1 << GOYA_PKT_CTL_EB_SHIFT) | 4165 (1 << GOYA_PKT_CTL_MB_SHIFT); 4166 cq_pkt->ctl = cpu_to_le32(tmp); 4167 cq_pkt->value = cpu_to_le32(cq_val); 4168 cq_pkt->addr = cpu_to_le64(cq_addr); 4169 4170 cq_pkt++; 4171 4172 tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) | 4173 (1 << GOYA_PKT_CTL_MB_SHIFT); 4174 cq_pkt->ctl = cpu_to_le32(tmp); 4175 cq_pkt->value = cpu_to_le32(msix_vec & 0x7FF); 4176 cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF); 4177 } 4178 4179 void goya_update_eq_ci(struct hl_device *hdev, u32 val) 4180 { 4181 WREG32(mmCPU_EQ_CI, val); 4182 } 4183 4184 void goya_restore_phase_topology(struct hl_device *hdev) 4185 { 4186 4187 } 4188 4189 static void goya_clear_sm_regs(struct hl_device *hdev) 4190 { 4191 int i, num_of_sob_in_longs, num_of_mon_in_longs; 4192 4193 num_of_sob_in_longs = 4194 ((mmSYNC_MNGR_SOB_OBJ_1023 - mmSYNC_MNGR_SOB_OBJ_0) + 4); 4195 4196 num_of_mon_in_longs = 4197 ((mmSYNC_MNGR_MON_STATUS_255 - mmSYNC_MNGR_MON_STATUS_0) + 4); 4198 4199 for (i = 0 ; i < num_of_sob_in_longs ; i += 4) 4200 WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0); 4201 4202 for (i = 0 ; i < num_of_mon_in_longs ; i += 4) 4203 WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0); 4204 4205 /* Flush all WREG to prevent race */ 4206 i = RREG32(mmSYNC_MNGR_SOB_OBJ_0); 4207 } 4208 4209 static int goya_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size, void *blob_addr) 4210 { 4211 dev_err(hdev->dev, "Reading via DMA is unimplemented yet\n"); 4212 return -EPERM; 4213 } 4214 4215 static u64 goya_read_pte(struct hl_device *hdev, u64 addr) 4216 { 4217 struct goya_device *goya = hdev->asic_specific; 4218 4219 if (hdev->reset_info.hard_reset_pending) 4220 return U64_MAX; 4221 4222 return readq(hdev->pcie_bar[DDR_BAR_ID] + 4223 (addr - goya->ddr_bar_cur_addr)); 4224 } 4225 4226 static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val) 4227 { 4228 struct goya_device *goya = hdev->asic_specific; 4229 4230 if (hdev->reset_info.hard_reset_pending) 4231 return; 4232 4233 writeq(val, hdev->pcie_bar[DDR_BAR_ID] + 4234 (addr - goya->ddr_bar_cur_addr)); 4235 } 4236 4237 static const char *_goya_get_event_desc(u16 event_type) 4238 { 4239 switch (event_type) { 4240 case GOYA_ASYNC_EVENT_ID_PCIE_IF: 4241 return "PCIe_if"; 4242 case GOYA_ASYNC_EVENT_ID_TPC0_ECC: 4243 case GOYA_ASYNC_EVENT_ID_TPC1_ECC: 4244 case GOYA_ASYNC_EVENT_ID_TPC2_ECC: 4245 case GOYA_ASYNC_EVENT_ID_TPC3_ECC: 4246 case GOYA_ASYNC_EVENT_ID_TPC4_ECC: 4247 case GOYA_ASYNC_EVENT_ID_TPC5_ECC: 4248 case GOYA_ASYNC_EVENT_ID_TPC6_ECC: 4249 case GOYA_ASYNC_EVENT_ID_TPC7_ECC: 4250 return "TPC%d_ecc"; 4251 case GOYA_ASYNC_EVENT_ID_MME_ECC: 4252 return "MME_ecc"; 4253 case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT: 4254 return "MME_ecc_ext"; 4255 case GOYA_ASYNC_EVENT_ID_MMU_ECC: 4256 return "MMU_ecc"; 4257 case GOYA_ASYNC_EVENT_ID_DMA_MACRO: 4258 return "DMA_macro"; 4259 case GOYA_ASYNC_EVENT_ID_DMA_ECC: 4260 return "DMA_ecc"; 4261 case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC: 4262 return "CPU_if_ecc"; 4263 case GOYA_ASYNC_EVENT_ID_PSOC_MEM: 4264 return "PSOC_mem"; 4265 case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT: 4266 return "PSOC_coresight"; 4267 case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29: 4268 return "SRAM%d"; 4269 case GOYA_ASYNC_EVENT_ID_GIC500: 4270 return "GIC500"; 4271 case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6: 4272 return "PLL%d"; 4273 case GOYA_ASYNC_EVENT_ID_AXI_ECC: 4274 return "AXI_ecc"; 4275 case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC: 4276 return "L2_ram_ecc"; 4277 case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET: 4278 return "PSOC_gpio_05_sw_reset"; 4279 case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT: 4280 return "PSOC_gpio_10_vrhot_icrit"; 4281 case GOYA_ASYNC_EVENT_ID_PCIE_DEC: 4282 return "PCIe_dec"; 4283 case GOYA_ASYNC_EVENT_ID_TPC0_DEC: 4284 case GOYA_ASYNC_EVENT_ID_TPC1_DEC: 4285 case GOYA_ASYNC_EVENT_ID_TPC2_DEC: 4286 case GOYA_ASYNC_EVENT_ID_TPC3_DEC: 4287 case GOYA_ASYNC_EVENT_ID_TPC4_DEC: 4288 case GOYA_ASYNC_EVENT_ID_TPC5_DEC: 4289 case GOYA_ASYNC_EVENT_ID_TPC6_DEC: 4290 case GOYA_ASYNC_EVENT_ID_TPC7_DEC: 4291 return "TPC%d_dec"; 4292 case GOYA_ASYNC_EVENT_ID_MME_WACS: 4293 return "MME_wacs"; 4294 case GOYA_ASYNC_EVENT_ID_MME_WACSD: 4295 return "MME_wacsd"; 4296 case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER: 4297 return "CPU_axi_splitter"; 4298 case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC: 4299 return "PSOC_axi_dec"; 4300 case GOYA_ASYNC_EVENT_ID_PSOC: 4301 return "PSOC"; 4302 case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR: 4303 case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR: 4304 case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR: 4305 case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR: 4306 case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR: 4307 case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR: 4308 case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR: 4309 case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR: 4310 return "TPC%d_krn_err"; 4311 case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ: 4312 return "TPC%d_cq"; 4313 case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM: 4314 return "TPC%d_qm"; 4315 case GOYA_ASYNC_EVENT_ID_MME_QM: 4316 return "MME_qm"; 4317 case GOYA_ASYNC_EVENT_ID_MME_CMDQ: 4318 return "MME_cq"; 4319 case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM: 4320 return "DMA%d_qm"; 4321 case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH: 4322 return "DMA%d_ch"; 4323 case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU: 4324 case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU: 4325 case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU: 4326 case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU: 4327 case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU: 4328 case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU: 4329 case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU: 4330 case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU: 4331 return "TPC%d_bmon_spmu"; 4332 case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4: 4333 return "DMA_bm_ch%d"; 4334 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S: 4335 return "POWER_ENV_S"; 4336 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E: 4337 return "POWER_ENV_E"; 4338 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S: 4339 return "THERMAL_ENV_S"; 4340 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E: 4341 return "THERMAL_ENV_E"; 4342 case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC: 4343 return "QUEUE_OUT_OF_SYNC"; 4344 default: 4345 return "N/A"; 4346 } 4347 } 4348 4349 static void goya_get_event_desc(u16 event_type, char *desc, size_t size) 4350 { 4351 u8 index; 4352 4353 switch (event_type) { 4354 case GOYA_ASYNC_EVENT_ID_TPC0_ECC: 4355 case GOYA_ASYNC_EVENT_ID_TPC1_ECC: 4356 case GOYA_ASYNC_EVENT_ID_TPC2_ECC: 4357 case GOYA_ASYNC_EVENT_ID_TPC3_ECC: 4358 case GOYA_ASYNC_EVENT_ID_TPC4_ECC: 4359 case GOYA_ASYNC_EVENT_ID_TPC5_ECC: 4360 case GOYA_ASYNC_EVENT_ID_TPC6_ECC: 4361 case GOYA_ASYNC_EVENT_ID_TPC7_ECC: 4362 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_ECC) / 3; 4363 snprintf(desc, size, _goya_get_event_desc(event_type), index); 4364 break; 4365 case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29: 4366 index = event_type - GOYA_ASYNC_EVENT_ID_SRAM0; 4367 snprintf(desc, size, _goya_get_event_desc(event_type), index); 4368 break; 4369 case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6: 4370 index = event_type - GOYA_ASYNC_EVENT_ID_PLL0; 4371 snprintf(desc, size, _goya_get_event_desc(event_type), index); 4372 break; 4373 case GOYA_ASYNC_EVENT_ID_TPC0_DEC: 4374 case GOYA_ASYNC_EVENT_ID_TPC1_DEC: 4375 case GOYA_ASYNC_EVENT_ID_TPC2_DEC: 4376 case GOYA_ASYNC_EVENT_ID_TPC3_DEC: 4377 case GOYA_ASYNC_EVENT_ID_TPC4_DEC: 4378 case GOYA_ASYNC_EVENT_ID_TPC5_DEC: 4379 case GOYA_ASYNC_EVENT_ID_TPC6_DEC: 4380 case GOYA_ASYNC_EVENT_ID_TPC7_DEC: 4381 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_DEC) / 3; 4382 snprintf(desc, size, _goya_get_event_desc(event_type), index); 4383 break; 4384 case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR: 4385 case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR: 4386 case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR: 4387 case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR: 4388 case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR: 4389 case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR: 4390 case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR: 4391 case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR: 4392 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR) / 10; 4393 snprintf(desc, size, _goya_get_event_desc(event_type), index); 4394 break; 4395 case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ: 4396 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_CMDQ; 4397 snprintf(desc, size, _goya_get_event_desc(event_type), index); 4398 break; 4399 case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM: 4400 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_QM; 4401 snprintf(desc, size, _goya_get_event_desc(event_type), index); 4402 break; 4403 case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM: 4404 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_QM; 4405 snprintf(desc, size, _goya_get_event_desc(event_type), index); 4406 break; 4407 case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH: 4408 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_CH; 4409 snprintf(desc, size, _goya_get_event_desc(event_type), index); 4410 break; 4411 case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU: 4412 case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU: 4413 case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU: 4414 case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU: 4415 case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU: 4416 case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU: 4417 case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU: 4418 case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU: 4419 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU) / 10; 4420 snprintf(desc, size, _goya_get_event_desc(event_type), index); 4421 break; 4422 case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4: 4423 index = event_type - GOYA_ASYNC_EVENT_ID_DMA_BM_CH0; 4424 snprintf(desc, size, _goya_get_event_desc(event_type), index); 4425 break; 4426 case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC: 4427 snprintf(desc, size, _goya_get_event_desc(event_type)); 4428 break; 4429 default: 4430 snprintf(desc, size, _goya_get_event_desc(event_type)); 4431 break; 4432 } 4433 } 4434 4435 static void goya_print_razwi_info(struct hl_device *hdev) 4436 { 4437 if (RREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD)) { 4438 dev_err_ratelimited(hdev->dev, "Illegal write to LBW\n"); 4439 WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0); 4440 } 4441 4442 if (RREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD)) { 4443 dev_err_ratelimited(hdev->dev, "Illegal read from LBW\n"); 4444 WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0); 4445 } 4446 4447 if (RREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD)) { 4448 dev_err_ratelimited(hdev->dev, "Illegal write to HBW\n"); 4449 WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0); 4450 } 4451 4452 if (RREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD)) { 4453 dev_err_ratelimited(hdev->dev, "Illegal read from HBW\n"); 4454 WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0); 4455 } 4456 } 4457 4458 static void goya_print_mmu_error_info(struct hl_device *hdev) 4459 { 4460 struct goya_device *goya = hdev->asic_specific; 4461 u64 addr; 4462 u32 val; 4463 4464 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) 4465 return; 4466 4467 val = RREG32(mmMMU_PAGE_ERROR_CAPTURE); 4468 if (val & MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) { 4469 addr = val & MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK; 4470 addr <<= 32; 4471 addr |= RREG32(mmMMU_PAGE_ERROR_CAPTURE_VA); 4472 4473 dev_err_ratelimited(hdev->dev, "MMU page fault on va 0x%llx\n", 4474 addr); 4475 4476 WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0); 4477 } 4478 } 4479 4480 static void goya_print_out_of_sync_info(struct hl_device *hdev, 4481 struct cpucp_pkt_sync_err *sync_err) 4482 { 4483 struct hl_hw_queue *q = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ]; 4484 4485 dev_err(hdev->dev, "Out of sync with FW, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%d\n", 4486 le32_to_cpu(sync_err->pi), le32_to_cpu(sync_err->ci), q->pi, atomic_read(&q->ci)); 4487 } 4488 4489 static void goya_print_irq_info(struct hl_device *hdev, u16 event_type, 4490 bool razwi) 4491 { 4492 char desc[20] = ""; 4493 4494 goya_get_event_desc(event_type, desc, sizeof(desc)); 4495 dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n", 4496 event_type, desc); 4497 4498 if (razwi) { 4499 goya_print_razwi_info(hdev); 4500 goya_print_mmu_error_info(hdev); 4501 } 4502 } 4503 4504 static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr, 4505 size_t irq_arr_size) 4506 { 4507 struct cpucp_unmask_irq_arr_packet *pkt; 4508 size_t total_pkt_size; 4509 u64 result; 4510 int rc; 4511 int irq_num_entries, irq_arr_index; 4512 __le32 *goya_irq_arr; 4513 4514 total_pkt_size = sizeof(struct cpucp_unmask_irq_arr_packet) + 4515 irq_arr_size; 4516 4517 /* data should be aligned to 8 bytes in order to CPU-CP to copy it */ 4518 total_pkt_size = (total_pkt_size + 0x7) & ~0x7; 4519 4520 /* total_pkt_size is casted to u16 later on */ 4521 if (total_pkt_size > USHRT_MAX) { 4522 dev_err(hdev->dev, "too many elements in IRQ array\n"); 4523 return -EINVAL; 4524 } 4525 4526 pkt = kzalloc(total_pkt_size, GFP_KERNEL); 4527 if (!pkt) 4528 return -ENOMEM; 4529 4530 irq_num_entries = irq_arr_size / sizeof(irq_arr[0]); 4531 pkt->length = cpu_to_le32(irq_num_entries); 4532 4533 /* We must perform any necessary endianness conversation on the irq 4534 * array being passed to the goya hardware 4535 */ 4536 for (irq_arr_index = 0, goya_irq_arr = (__le32 *) &pkt->irqs; 4537 irq_arr_index < irq_num_entries ; irq_arr_index++) 4538 goya_irq_arr[irq_arr_index] = 4539 cpu_to_le32(irq_arr[irq_arr_index]); 4540 4541 pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY << 4542 CPUCP_PKT_CTL_OPCODE_SHIFT); 4543 4544 rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt, 4545 total_pkt_size, 0, &result); 4546 4547 if (rc) 4548 dev_err(hdev->dev, "failed to unmask IRQ array\n"); 4549 4550 kfree(pkt); 4551 4552 return rc; 4553 } 4554 4555 static int goya_compute_reset_late_init(struct hl_device *hdev) 4556 { 4557 /* 4558 * Unmask all IRQs since some could have been received 4559 * during the soft reset 4560 */ 4561 return goya_unmask_irq_arr(hdev, goya_all_events, 4562 sizeof(goya_all_events)); 4563 } 4564 4565 static int goya_unmask_irq(struct hl_device *hdev, u16 event_type) 4566 { 4567 struct cpucp_packet pkt; 4568 u64 result; 4569 int rc; 4570 4571 memset(&pkt, 0, sizeof(pkt)); 4572 4573 pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ << 4574 CPUCP_PKT_CTL_OPCODE_SHIFT); 4575 pkt.value = cpu_to_le64(event_type); 4576 4577 rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 4578 0, &result); 4579 4580 if (rc) 4581 dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type); 4582 4583 return rc; 4584 } 4585 4586 static void goya_print_clk_change_info(struct hl_device *hdev, u16 event_type) 4587 { 4588 ktime_t zero_time = ktime_set(0, 0); 4589 4590 mutex_lock(&hdev->clk_throttling.lock); 4591 4592 switch (event_type) { 4593 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S: 4594 hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_POWER; 4595 hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_POWER; 4596 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].start = ktime_get(); 4597 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = zero_time; 4598 dev_info_ratelimited(hdev->dev, 4599 "Clock throttling due to power consumption\n"); 4600 break; 4601 4602 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E: 4603 hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_POWER; 4604 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = ktime_get(); 4605 dev_info_ratelimited(hdev->dev, 4606 "Power envelop is safe, back to optimal clock\n"); 4607 break; 4608 4609 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S: 4610 hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_THERMAL; 4611 hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_THERMAL; 4612 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].start = ktime_get(); 4613 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = zero_time; 4614 dev_info_ratelimited(hdev->dev, 4615 "Clock throttling due to overheating\n"); 4616 break; 4617 4618 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E: 4619 hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_THERMAL; 4620 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = ktime_get(); 4621 dev_info_ratelimited(hdev->dev, 4622 "Thermal envelop is safe, back to optimal clock\n"); 4623 break; 4624 4625 default: 4626 dev_err(hdev->dev, "Received invalid clock change event %d\n", 4627 event_type); 4628 break; 4629 } 4630 4631 mutex_unlock(&hdev->clk_throttling.lock); 4632 } 4633 4634 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry) 4635 { 4636 u32 ctl = le32_to_cpu(eq_entry->hdr.ctl); 4637 u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK) 4638 >> EQ_CTL_EVENT_TYPE_SHIFT); 4639 struct goya_device *goya = hdev->asic_specific; 4640 4641 if (event_type >= GOYA_ASYNC_EVENT_ID_SIZE) { 4642 dev_err(hdev->dev, "Event type %u exceeds maximum of %u", 4643 event_type, GOYA_ASYNC_EVENT_ID_SIZE - 1); 4644 return; 4645 } 4646 4647 goya->events_stat[event_type]++; 4648 goya->events_stat_aggregate[event_type]++; 4649 4650 switch (event_type) { 4651 case GOYA_ASYNC_EVENT_ID_PCIE_IF: 4652 case GOYA_ASYNC_EVENT_ID_TPC0_ECC: 4653 case GOYA_ASYNC_EVENT_ID_TPC1_ECC: 4654 case GOYA_ASYNC_EVENT_ID_TPC2_ECC: 4655 case GOYA_ASYNC_EVENT_ID_TPC3_ECC: 4656 case GOYA_ASYNC_EVENT_ID_TPC4_ECC: 4657 case GOYA_ASYNC_EVENT_ID_TPC5_ECC: 4658 case GOYA_ASYNC_EVENT_ID_TPC6_ECC: 4659 case GOYA_ASYNC_EVENT_ID_TPC7_ECC: 4660 case GOYA_ASYNC_EVENT_ID_MME_ECC: 4661 case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT: 4662 case GOYA_ASYNC_EVENT_ID_MMU_ECC: 4663 case GOYA_ASYNC_EVENT_ID_DMA_MACRO: 4664 case GOYA_ASYNC_EVENT_ID_DMA_ECC: 4665 case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC: 4666 case GOYA_ASYNC_EVENT_ID_PSOC_MEM: 4667 case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT: 4668 case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29: 4669 case GOYA_ASYNC_EVENT_ID_GIC500: 4670 case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6: 4671 case GOYA_ASYNC_EVENT_ID_AXI_ECC: 4672 case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC: 4673 goya_print_irq_info(hdev, event_type, false); 4674 if (hdev->hard_reset_on_fw_events) 4675 hl_device_reset(hdev, (HL_DRV_RESET_HARD | 4676 HL_DRV_RESET_FW_FATAL_ERR)); 4677 break; 4678 4679 case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET: 4680 goya_print_irq_info(hdev, event_type, false); 4681 if (hdev->hard_reset_on_fw_events) 4682 hl_device_reset(hdev, HL_DRV_RESET_HARD); 4683 break; 4684 4685 case GOYA_ASYNC_EVENT_ID_PCIE_DEC: 4686 case GOYA_ASYNC_EVENT_ID_TPC0_DEC: 4687 case GOYA_ASYNC_EVENT_ID_TPC1_DEC: 4688 case GOYA_ASYNC_EVENT_ID_TPC2_DEC: 4689 case GOYA_ASYNC_EVENT_ID_TPC3_DEC: 4690 case GOYA_ASYNC_EVENT_ID_TPC4_DEC: 4691 case GOYA_ASYNC_EVENT_ID_TPC5_DEC: 4692 case GOYA_ASYNC_EVENT_ID_TPC6_DEC: 4693 case GOYA_ASYNC_EVENT_ID_TPC7_DEC: 4694 case GOYA_ASYNC_EVENT_ID_MME_WACS: 4695 case GOYA_ASYNC_EVENT_ID_MME_WACSD: 4696 case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER: 4697 case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC: 4698 case GOYA_ASYNC_EVENT_ID_PSOC: 4699 case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR: 4700 case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR: 4701 case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR: 4702 case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR: 4703 case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR: 4704 case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR: 4705 case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR: 4706 case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR: 4707 case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_QM: 4708 case GOYA_ASYNC_EVENT_ID_MME_QM: 4709 case GOYA_ASYNC_EVENT_ID_MME_CMDQ: 4710 case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM: 4711 case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH: 4712 goya_print_irq_info(hdev, event_type, true); 4713 goya_unmask_irq(hdev, event_type); 4714 break; 4715 4716 case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT: 4717 case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU: 4718 case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU: 4719 case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU: 4720 case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU: 4721 case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU: 4722 case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU: 4723 case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU: 4724 case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU: 4725 case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4: 4726 goya_print_irq_info(hdev, event_type, false); 4727 goya_unmask_irq(hdev, event_type); 4728 break; 4729 4730 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S: 4731 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E: 4732 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S: 4733 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E: 4734 goya_print_clk_change_info(hdev, event_type); 4735 goya_unmask_irq(hdev, event_type); 4736 break; 4737 4738 case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC: 4739 goya_print_irq_info(hdev, event_type, false); 4740 goya_print_out_of_sync_info(hdev, &eq_entry->pkt_sync_err); 4741 if (hdev->hard_reset_on_fw_events) 4742 hl_device_reset(hdev, HL_DRV_RESET_HARD); 4743 else 4744 hl_fw_unmask_irq(hdev, event_type); 4745 break; 4746 4747 default: 4748 dev_err(hdev->dev, "Received invalid H/W interrupt %d\n", 4749 event_type); 4750 break; 4751 } 4752 } 4753 4754 void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size) 4755 { 4756 struct goya_device *goya = hdev->asic_specific; 4757 4758 if (aggregate) { 4759 *size = (u32) sizeof(goya->events_stat_aggregate); 4760 return goya->events_stat_aggregate; 4761 } 4762 4763 *size = (u32) sizeof(goya->events_stat); 4764 return goya->events_stat; 4765 } 4766 4767 static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size, 4768 u64 val, bool is_dram) 4769 { 4770 struct packet_lin_dma *lin_dma_pkt; 4771 struct hl_cs_job *job; 4772 u32 cb_size, ctl; 4773 struct hl_cb *cb; 4774 int rc, lin_dma_pkts_cnt; 4775 4776 lin_dma_pkts_cnt = DIV_ROUND_UP_ULL(size, SZ_2G); 4777 cb_size = lin_dma_pkts_cnt * sizeof(struct packet_lin_dma) + 4778 sizeof(struct packet_msg_prot); 4779 cb = hl_cb_kernel_create(hdev, cb_size, false); 4780 if (!cb) 4781 return -ENOMEM; 4782 4783 lin_dma_pkt = cb->kernel_address; 4784 4785 do { 4786 memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt)); 4787 4788 ctl = ((PACKET_LIN_DMA << GOYA_PKT_CTL_OPCODE_SHIFT) | 4789 (1 << GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT) | 4790 (1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) | 4791 (1 << GOYA_PKT_CTL_RB_SHIFT) | 4792 (1 << GOYA_PKT_CTL_MB_SHIFT)); 4793 ctl |= (is_dram ? HL_DMA_HOST_TO_DRAM : HL_DMA_HOST_TO_SRAM) << 4794 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT; 4795 lin_dma_pkt->ctl = cpu_to_le32(ctl); 4796 4797 lin_dma_pkt->src_addr = cpu_to_le64(val); 4798 lin_dma_pkt->dst_addr = cpu_to_le64(addr); 4799 if (lin_dma_pkts_cnt > 1) 4800 lin_dma_pkt->tsize = cpu_to_le32(SZ_2G); 4801 else 4802 lin_dma_pkt->tsize = cpu_to_le32(size); 4803 4804 size -= SZ_2G; 4805 addr += SZ_2G; 4806 lin_dma_pkt++; 4807 } while (--lin_dma_pkts_cnt); 4808 4809 job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true); 4810 if (!job) { 4811 dev_err(hdev->dev, "Failed to allocate a new job\n"); 4812 rc = -ENOMEM; 4813 goto release_cb; 4814 } 4815 4816 job->id = 0; 4817 job->user_cb = cb; 4818 atomic_inc(&job->user_cb->cs_cnt); 4819 job->user_cb_size = cb_size; 4820 job->hw_queue_id = GOYA_QUEUE_ID_DMA_0; 4821 job->patched_cb = job->user_cb; 4822 job->job_cb_size = job->user_cb_size; 4823 4824 hl_debugfs_add_job(hdev, job); 4825 4826 rc = goya_send_job_on_qman0(hdev, job); 4827 4828 hl_debugfs_remove_job(hdev, job); 4829 kfree(job); 4830 atomic_dec(&cb->cs_cnt); 4831 4832 release_cb: 4833 hl_cb_put(cb); 4834 hl_cb_destroy(&hdev->kernel_mem_mgr, cb->buf->handle); 4835 4836 return rc; 4837 } 4838 4839 int goya_context_switch(struct hl_device *hdev, u32 asid) 4840 { 4841 struct asic_fixed_properties *prop = &hdev->asic_prop; 4842 u64 addr = prop->sram_base_address, sob_addr; 4843 u32 size = hdev->pldm ? 0x10000 : prop->sram_size; 4844 u64 val = 0x7777777777777777ull; 4845 int rc, dma_id; 4846 u32 channel_off = mmDMA_CH_1_WR_COMP_ADDR_LO - 4847 mmDMA_CH_0_WR_COMP_ADDR_LO; 4848 4849 rc = goya_memset_device_memory(hdev, addr, size, val, false); 4850 if (rc) { 4851 dev_err(hdev->dev, "Failed to clear SRAM in context switch\n"); 4852 return rc; 4853 } 4854 4855 /* we need to reset registers that the user is allowed to change */ 4856 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007; 4857 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO, lower_32_bits(sob_addr)); 4858 4859 for (dma_id = 1 ; dma_id < NUMBER_OF_EXT_HW_QUEUES ; dma_id++) { 4860 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 + 4861 (dma_id - 1) * 4; 4862 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + channel_off * dma_id, 4863 lower_32_bits(sob_addr)); 4864 } 4865 4866 WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020); 4867 4868 goya_clear_sm_regs(hdev); 4869 4870 return 0; 4871 } 4872 4873 static int goya_mmu_clear_pgt_range(struct hl_device *hdev) 4874 { 4875 struct asic_fixed_properties *prop = &hdev->asic_prop; 4876 struct goya_device *goya = hdev->asic_specific; 4877 u64 addr = prop->mmu_pgt_addr; 4878 u32 size = prop->mmu_pgt_size + MMU_DRAM_DEFAULT_PAGE_SIZE + 4879 MMU_CACHE_MNG_SIZE; 4880 4881 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) 4882 return 0; 4883 4884 return goya_memset_device_memory(hdev, addr, size, 0, true); 4885 } 4886 4887 static int goya_mmu_set_dram_default_page(struct hl_device *hdev) 4888 { 4889 struct goya_device *goya = hdev->asic_specific; 4890 u64 addr = hdev->asic_prop.mmu_dram_default_page_addr; 4891 u32 size = MMU_DRAM_DEFAULT_PAGE_SIZE; 4892 u64 val = 0x9999999999999999ull; 4893 4894 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) 4895 return 0; 4896 4897 return goya_memset_device_memory(hdev, addr, size, val, true); 4898 } 4899 4900 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev) 4901 { 4902 struct asic_fixed_properties *prop = &hdev->asic_prop; 4903 struct goya_device *goya = hdev->asic_specific; 4904 s64 off, cpu_off; 4905 int rc; 4906 4907 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) 4908 return 0; 4909 4910 for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB) { 4911 rc = hl_mmu_map_page(hdev->kernel_ctx, 4912 prop->dram_base_address + off, 4913 prop->dram_base_address + off, PAGE_SIZE_2MB, 4914 (off + PAGE_SIZE_2MB) == CPU_FW_IMAGE_SIZE); 4915 if (rc) { 4916 dev_err(hdev->dev, "Map failed for address 0x%llx\n", 4917 prop->dram_base_address + off); 4918 goto unmap; 4919 } 4920 } 4921 4922 if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) { 4923 rc = hl_mmu_map_page(hdev->kernel_ctx, 4924 VA_CPU_ACCESSIBLE_MEM_ADDR, 4925 hdev->cpu_accessible_dma_address, 4926 PAGE_SIZE_2MB, true); 4927 4928 if (rc) { 4929 dev_err(hdev->dev, 4930 "Map failed for CPU accessible memory\n"); 4931 off -= PAGE_SIZE_2MB; 4932 goto unmap; 4933 } 4934 } else { 4935 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB) { 4936 rc = hl_mmu_map_page(hdev->kernel_ctx, 4937 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off, 4938 hdev->cpu_accessible_dma_address + cpu_off, 4939 PAGE_SIZE_4KB, true); 4940 if (rc) { 4941 dev_err(hdev->dev, 4942 "Map failed for CPU accessible memory\n"); 4943 cpu_off -= PAGE_SIZE_4KB; 4944 goto unmap_cpu; 4945 } 4946 } 4947 } 4948 4949 goya_mmu_prepare_reg(hdev, mmCPU_IF_ARUSER_OVR, HL_KERNEL_ASID_ID); 4950 goya_mmu_prepare_reg(hdev, mmCPU_IF_AWUSER_OVR, HL_KERNEL_ASID_ID); 4951 WREG32(mmCPU_IF_ARUSER_OVR_EN, 0x7FF); 4952 WREG32(mmCPU_IF_AWUSER_OVR_EN, 0x7FF); 4953 4954 /* Make sure configuration is flushed to device */ 4955 RREG32(mmCPU_IF_AWUSER_OVR_EN); 4956 4957 goya->device_cpu_mmu_mappings_done = true; 4958 4959 return 0; 4960 4961 unmap_cpu: 4962 for (; cpu_off >= 0 ; cpu_off -= PAGE_SIZE_4KB) 4963 if (hl_mmu_unmap_page(hdev->kernel_ctx, 4964 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off, 4965 PAGE_SIZE_4KB, true)) 4966 dev_warn_ratelimited(hdev->dev, 4967 "failed to unmap address 0x%llx\n", 4968 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off); 4969 unmap: 4970 for (; off >= 0 ; off -= PAGE_SIZE_2MB) 4971 if (hl_mmu_unmap_page(hdev->kernel_ctx, 4972 prop->dram_base_address + off, PAGE_SIZE_2MB, 4973 true)) 4974 dev_warn_ratelimited(hdev->dev, 4975 "failed to unmap address 0x%llx\n", 4976 prop->dram_base_address + off); 4977 4978 return rc; 4979 } 4980 4981 void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev) 4982 { 4983 struct asic_fixed_properties *prop = &hdev->asic_prop; 4984 struct goya_device *goya = hdev->asic_specific; 4985 u32 off, cpu_off; 4986 4987 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) 4988 return; 4989 4990 if (!goya->device_cpu_mmu_mappings_done) 4991 return; 4992 4993 WREG32(mmCPU_IF_ARUSER_OVR_EN, 0); 4994 WREG32(mmCPU_IF_AWUSER_OVR_EN, 0); 4995 4996 if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) { 4997 if (hl_mmu_unmap_page(hdev->kernel_ctx, 4998 VA_CPU_ACCESSIBLE_MEM_ADDR, 4999 PAGE_SIZE_2MB, true)) 5000 dev_warn(hdev->dev, 5001 "Failed to unmap CPU accessible memory\n"); 5002 } else { 5003 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB) 5004 if (hl_mmu_unmap_page(hdev->kernel_ctx, 5005 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off, 5006 PAGE_SIZE_4KB, 5007 (cpu_off + PAGE_SIZE_4KB) >= SZ_2M)) 5008 dev_warn_ratelimited(hdev->dev, 5009 "failed to unmap address 0x%llx\n", 5010 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off); 5011 } 5012 5013 for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB) 5014 if (hl_mmu_unmap_page(hdev->kernel_ctx, 5015 prop->dram_base_address + off, PAGE_SIZE_2MB, 5016 (off + PAGE_SIZE_2MB) >= CPU_FW_IMAGE_SIZE)) 5017 dev_warn_ratelimited(hdev->dev, 5018 "Failed to unmap address 0x%llx\n", 5019 prop->dram_base_address + off); 5020 5021 goya->device_cpu_mmu_mappings_done = false; 5022 } 5023 5024 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid) 5025 { 5026 struct goya_device *goya = hdev->asic_specific; 5027 int i; 5028 5029 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) 5030 return; 5031 5032 if (asid & ~MME_QM_GLBL_SECURE_PROPS_ASID_MASK) { 5033 dev_crit(hdev->dev, "asid %u is too big\n", asid); 5034 return; 5035 } 5036 5037 /* zero the MMBP and ASID bits and then set the ASID */ 5038 for (i = 0 ; i < GOYA_MMU_REGS_NUM ; i++) 5039 goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid); 5040 } 5041 5042 static int goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, 5043 u32 flags) 5044 { 5045 struct goya_device *goya = hdev->asic_specific; 5046 u32 status, timeout_usec; 5047 int rc; 5048 5049 if (!(goya->hw_cap_initialized & HW_CAP_MMU) || 5050 hdev->reset_info.hard_reset_pending) 5051 return 0; 5052 5053 /* no need in L1 only invalidation in Goya */ 5054 if (!is_hard) 5055 return 0; 5056 5057 if (hdev->pldm) 5058 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC; 5059 else 5060 timeout_usec = MMU_CONFIG_TIMEOUT_USEC; 5061 5062 /* L0 & L1 invalidation */ 5063 WREG32(mmSTLB_INV_ALL_START, 1); 5064 5065 rc = hl_poll_timeout( 5066 hdev, 5067 mmSTLB_INV_ALL_START, 5068 status, 5069 !status, 5070 1000, 5071 timeout_usec); 5072 5073 return rc; 5074 } 5075 5076 static int goya_mmu_invalidate_cache_range(struct hl_device *hdev, 5077 bool is_hard, u32 flags, 5078 u32 asid, u64 va, u64 size) 5079 { 5080 /* Treat as invalidate all because there is no range invalidation 5081 * in Goya 5082 */ 5083 return hl_mmu_invalidate_cache(hdev, is_hard, flags); 5084 } 5085 5086 int goya_send_heartbeat(struct hl_device *hdev) 5087 { 5088 struct goya_device *goya = hdev->asic_specific; 5089 5090 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) 5091 return 0; 5092 5093 return hl_fw_send_heartbeat(hdev); 5094 } 5095 5096 int goya_cpucp_info_get(struct hl_device *hdev) 5097 { 5098 struct goya_device *goya = hdev->asic_specific; 5099 struct asic_fixed_properties *prop = &hdev->asic_prop; 5100 u64 dram_size; 5101 int rc; 5102 5103 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) 5104 return 0; 5105 5106 rc = hl_fw_cpucp_handshake(hdev, mmCPU_BOOT_DEV_STS0, 5107 mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0, 5108 mmCPU_BOOT_ERR1); 5109 if (rc) 5110 return rc; 5111 5112 dram_size = le64_to_cpu(prop->cpucp_info.dram_size); 5113 if (dram_size) { 5114 if ((!is_power_of_2(dram_size)) || 5115 (dram_size < DRAM_PHYS_DEFAULT_SIZE)) { 5116 dev_err(hdev->dev, 5117 "F/W reported invalid DRAM size %llu. Trying to use default size\n", 5118 dram_size); 5119 dram_size = DRAM_PHYS_DEFAULT_SIZE; 5120 } 5121 5122 prop->dram_size = dram_size; 5123 prop->dram_end_address = prop->dram_base_address + dram_size; 5124 } 5125 5126 if (!strlen(prop->cpucp_info.card_name)) 5127 strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME, 5128 CARD_NAME_MAX_LEN); 5129 5130 return 0; 5131 } 5132 5133 static bool goya_is_device_idle(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, 5134 struct engines_data *e) 5135 { 5136 const char *fmt = "%-5d%-9s%#-14x%#-16x%#x\n"; 5137 const char *dma_fmt = "%-5d%-9s%#-14x%#x\n"; 5138 unsigned long *mask = (unsigned long *)mask_arr; 5139 u32 qm_glbl_sts0, cmdq_glbl_sts0, dma_core_sts0, tpc_cfg_sts, 5140 mme_arch_sts; 5141 bool is_idle = true, is_eng_idle; 5142 u64 offset; 5143 int i; 5144 5145 if (e) 5146 hl_engine_data_sprintf(e, "\nDMA is_idle QM_GLBL_STS0 DMA_CORE_STS0\n" 5147 "--- ------- ------------ -------------\n"); 5148 5149 offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0; 5150 5151 for (i = 0 ; i < DMA_MAX_NUM ; i++) { 5152 qm_glbl_sts0 = RREG32(mmDMA_QM_0_GLBL_STS0 + i * offset); 5153 dma_core_sts0 = RREG32(mmDMA_CH_0_STS0 + i * offset); 5154 is_eng_idle = IS_DMA_QM_IDLE(qm_glbl_sts0) && 5155 IS_DMA_IDLE(dma_core_sts0); 5156 is_idle &= is_eng_idle; 5157 5158 if (mask && !is_eng_idle) 5159 set_bit(GOYA_ENGINE_ID_DMA_0 + i, mask); 5160 if (e) 5161 hl_engine_data_sprintf(e, dma_fmt, i, is_eng_idle ? "Y" : "N", 5162 qm_glbl_sts0, dma_core_sts0); 5163 } 5164 5165 if (e) 5166 hl_engine_data_sprintf(e, 5167 "\nTPC is_idle QM_GLBL_STS0 CMDQ_GLBL_STS0 CFG_STATUS\n" 5168 "--- ------- ------------ -------------- ----------\n"); 5169 5170 offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0; 5171 5172 for (i = 0 ; i < TPC_MAX_NUM ; i++) { 5173 qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + i * offset); 5174 cmdq_glbl_sts0 = RREG32(mmTPC0_CMDQ_GLBL_STS0 + i * offset); 5175 tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + i * offset); 5176 is_eng_idle = IS_TPC_QM_IDLE(qm_glbl_sts0) && 5177 IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) && 5178 IS_TPC_IDLE(tpc_cfg_sts); 5179 is_idle &= is_eng_idle; 5180 5181 if (mask && !is_eng_idle) 5182 set_bit(GOYA_ENGINE_ID_TPC_0 + i, mask); 5183 if (e) 5184 hl_engine_data_sprintf(e, fmt, i, is_eng_idle ? "Y" : "N", 5185 qm_glbl_sts0, cmdq_glbl_sts0, tpc_cfg_sts); 5186 } 5187 5188 if (e) 5189 hl_engine_data_sprintf(e, 5190 "\nMME is_idle QM_GLBL_STS0 CMDQ_GLBL_STS0 ARCH_STATUS\n" 5191 "--- ------- ------------ -------------- -----------\n"); 5192 5193 qm_glbl_sts0 = RREG32(mmMME_QM_GLBL_STS0); 5194 cmdq_glbl_sts0 = RREG32(mmMME_CMDQ_GLBL_STS0); 5195 mme_arch_sts = RREG32(mmMME_ARCH_STATUS); 5196 is_eng_idle = IS_MME_QM_IDLE(qm_glbl_sts0) && 5197 IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) && 5198 IS_MME_IDLE(mme_arch_sts); 5199 is_idle &= is_eng_idle; 5200 5201 if (mask && !is_eng_idle) 5202 set_bit(GOYA_ENGINE_ID_MME_0, mask); 5203 if (e) { 5204 hl_engine_data_sprintf(e, fmt, 0, is_eng_idle ? "Y" : "N", qm_glbl_sts0, 5205 cmdq_glbl_sts0, mme_arch_sts); 5206 hl_engine_data_sprintf(e, "\n"); 5207 } 5208 5209 return is_idle; 5210 } 5211 5212 static void goya_hw_queues_lock(struct hl_device *hdev) 5213 __acquires(&goya->hw_queues_lock) 5214 { 5215 struct goya_device *goya = hdev->asic_specific; 5216 5217 spin_lock(&goya->hw_queues_lock); 5218 } 5219 5220 static void goya_hw_queues_unlock(struct hl_device *hdev) 5221 __releases(&goya->hw_queues_lock) 5222 { 5223 struct goya_device *goya = hdev->asic_specific; 5224 5225 spin_unlock(&goya->hw_queues_lock); 5226 } 5227 5228 static u32 goya_get_pci_id(struct hl_device *hdev) 5229 { 5230 return hdev->pdev->device; 5231 } 5232 5233 static int goya_get_eeprom_data(struct hl_device *hdev, void *data, 5234 size_t max_size) 5235 { 5236 struct goya_device *goya = hdev->asic_specific; 5237 5238 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) 5239 return 0; 5240 5241 return hl_fw_get_eeprom_data(hdev, data, max_size); 5242 } 5243 5244 static void goya_cpu_init_scrambler_dram(struct hl_device *hdev) 5245 { 5246 5247 } 5248 5249 static int goya_ctx_init(struct hl_ctx *ctx) 5250 { 5251 if (ctx->asid != HL_KERNEL_ASID_ID) 5252 goya_mmu_prepare(ctx->hdev, ctx->asid); 5253 5254 return 0; 5255 } 5256 5257 static int goya_pre_schedule_cs(struct hl_cs *cs) 5258 { 5259 return 0; 5260 } 5261 5262 u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx) 5263 { 5264 return cq_idx; 5265 } 5266 5267 static u32 goya_get_signal_cb_size(struct hl_device *hdev) 5268 { 5269 return 0; 5270 } 5271 5272 static u32 goya_get_wait_cb_size(struct hl_device *hdev) 5273 { 5274 return 0; 5275 } 5276 5277 static u32 goya_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id, 5278 u32 size, bool eb) 5279 { 5280 return 0; 5281 } 5282 5283 static u32 goya_gen_wait_cb(struct hl_device *hdev, 5284 struct hl_gen_wait_properties *prop) 5285 { 5286 return 0; 5287 } 5288 5289 static void goya_reset_sob(struct hl_device *hdev, void *data) 5290 { 5291 5292 } 5293 5294 static void goya_reset_sob_group(struct hl_device *hdev, u16 sob_group) 5295 { 5296 5297 } 5298 5299 u64 goya_get_device_time(struct hl_device *hdev) 5300 { 5301 u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32; 5302 5303 return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL); 5304 } 5305 5306 static int goya_collective_wait_init_cs(struct hl_cs *cs) 5307 { 5308 return 0; 5309 } 5310 5311 static int goya_collective_wait_create_jobs(struct hl_device *hdev, 5312 struct hl_ctx *ctx, struct hl_cs *cs, u32 wait_queue_id, 5313 u32 collective_engine_id, u32 encaps_signal_offset) 5314 { 5315 return -EINVAL; 5316 } 5317 5318 static void goya_ctx_fini(struct hl_ctx *ctx) 5319 { 5320 5321 } 5322 5323 static int goya_get_hw_block_id(struct hl_device *hdev, u64 block_addr, 5324 u32 *block_size, u32 *block_id) 5325 { 5326 return -EPERM; 5327 } 5328 5329 static int goya_block_mmap(struct hl_device *hdev, struct vm_area_struct *vma, 5330 u32 block_id, u32 block_size) 5331 { 5332 return -EPERM; 5333 } 5334 5335 static void goya_enable_events_from_fw(struct hl_device *hdev) 5336 { 5337 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, 5338 GOYA_ASYNC_EVENT_ID_INTS_REGISTER); 5339 } 5340 5341 static int goya_ack_mmu_page_fault_or_access_error(struct hl_device *hdev, u64 mmu_cap_mask) 5342 { 5343 return -EINVAL; 5344 } 5345 5346 static int goya_map_pll_idx_to_fw_idx(u32 pll_idx) 5347 { 5348 switch (pll_idx) { 5349 case HL_GOYA_CPU_PLL: return CPU_PLL; 5350 case HL_GOYA_PCI_PLL: return PCI_PLL; 5351 case HL_GOYA_MME_PLL: return MME_PLL; 5352 case HL_GOYA_TPC_PLL: return TPC_PLL; 5353 case HL_GOYA_IC_PLL: return IC_PLL; 5354 case HL_GOYA_MC_PLL: return MC_PLL; 5355 case HL_GOYA_EMMC_PLL: return EMMC_PLL; 5356 default: return -EINVAL; 5357 } 5358 } 5359 5360 static int goya_gen_sync_to_engine_map(struct hl_device *hdev, 5361 struct hl_sync_to_engine_map *map) 5362 { 5363 /* Not implemented */ 5364 return 0; 5365 } 5366 5367 static int goya_monitor_valid(struct hl_mon_state_dump *mon) 5368 { 5369 /* Not implemented */ 5370 return 0; 5371 } 5372 5373 static int goya_print_single_monitor(char **buf, size_t *size, size_t *offset, 5374 struct hl_device *hdev, 5375 struct hl_mon_state_dump *mon) 5376 { 5377 /* Not implemented */ 5378 return 0; 5379 } 5380 5381 5382 static int goya_print_fences_single_engine( 5383 struct hl_device *hdev, u64 base_offset, u64 status_base_offset, 5384 enum hl_sync_engine_type engine_type, u32 engine_id, char **buf, 5385 size_t *size, size_t *offset) 5386 { 5387 /* Not implemented */ 5388 return 0; 5389 } 5390 5391 5392 static struct hl_state_dump_specs_funcs goya_state_dump_funcs = { 5393 .monitor_valid = goya_monitor_valid, 5394 .print_single_monitor = goya_print_single_monitor, 5395 .gen_sync_to_engine_map = goya_gen_sync_to_engine_map, 5396 .print_fences_single_engine = goya_print_fences_single_engine, 5397 }; 5398 5399 static void goya_state_dump_init(struct hl_device *hdev) 5400 { 5401 /* Not implemented */ 5402 hdev->state_dump_specs.props = goya_state_dump_specs_props; 5403 hdev->state_dump_specs.funcs = goya_state_dump_funcs; 5404 } 5405 5406 static u32 goya_get_sob_addr(struct hl_device *hdev, u32 sob_id) 5407 { 5408 return 0; 5409 } 5410 5411 static u32 *goya_get_stream_master_qid_arr(void) 5412 { 5413 return NULL; 5414 } 5415 5416 static int goya_get_monitor_dump(struct hl_device *hdev, void *data) 5417 { 5418 return -EOPNOTSUPP; 5419 } 5420 5421 static void goya_check_if_razwi_happened(struct hl_device *hdev) 5422 { 5423 } 5424 5425 static int goya_scrub_device_dram(struct hl_device *hdev, u64 val) 5426 { 5427 return -EOPNOTSUPP; 5428 } 5429 5430 static int goya_set_dram_properties(struct hl_device *hdev) 5431 { 5432 return 0; 5433 } 5434 5435 static int goya_set_binning_masks(struct hl_device *hdev) 5436 { 5437 return 0; 5438 } 5439 5440 static int goya_send_device_activity(struct hl_device *hdev, bool open) 5441 { 5442 return 0; 5443 } 5444 5445 static const struct hl_asic_funcs goya_funcs = { 5446 .early_init = goya_early_init, 5447 .early_fini = goya_early_fini, 5448 .late_init = goya_late_init, 5449 .late_fini = goya_late_fini, 5450 .sw_init = goya_sw_init, 5451 .sw_fini = goya_sw_fini, 5452 .hw_init = goya_hw_init, 5453 .hw_fini = goya_hw_fini, 5454 .halt_engines = goya_halt_engines, 5455 .suspend = goya_suspend, 5456 .resume = goya_resume, 5457 .mmap = goya_mmap, 5458 .ring_doorbell = goya_ring_doorbell, 5459 .pqe_write = goya_pqe_write, 5460 .asic_dma_alloc_coherent = goya_dma_alloc_coherent, 5461 .asic_dma_free_coherent = goya_dma_free_coherent, 5462 .scrub_device_mem = goya_scrub_device_mem, 5463 .scrub_device_dram = goya_scrub_device_dram, 5464 .get_int_queue_base = goya_get_int_queue_base, 5465 .test_queues = goya_test_queues, 5466 .asic_dma_pool_zalloc = goya_dma_pool_zalloc, 5467 .asic_dma_pool_free = goya_dma_pool_free, 5468 .cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc, 5469 .cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free, 5470 .hl_dma_unmap_sgtable = hl_dma_unmap_sgtable, 5471 .cs_parser = goya_cs_parser, 5472 .asic_dma_map_sgtable = hl_dma_map_sgtable, 5473 .add_end_of_cb_packets = goya_add_end_of_cb_packets, 5474 .update_eq_ci = goya_update_eq_ci, 5475 .context_switch = goya_context_switch, 5476 .restore_phase_topology = goya_restore_phase_topology, 5477 .debugfs_read_dma = goya_debugfs_read_dma, 5478 .add_device_attr = goya_add_device_attr, 5479 .handle_eqe = goya_handle_eqe, 5480 .get_events_stat = goya_get_events_stat, 5481 .read_pte = goya_read_pte, 5482 .write_pte = goya_write_pte, 5483 .mmu_invalidate_cache = goya_mmu_invalidate_cache, 5484 .mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range, 5485 .mmu_prefetch_cache_range = NULL, 5486 .send_heartbeat = goya_send_heartbeat, 5487 .debug_coresight = goya_debug_coresight, 5488 .is_device_idle = goya_is_device_idle, 5489 .compute_reset_late_init = goya_compute_reset_late_init, 5490 .hw_queues_lock = goya_hw_queues_lock, 5491 .hw_queues_unlock = goya_hw_queues_unlock, 5492 .get_pci_id = goya_get_pci_id, 5493 .get_eeprom_data = goya_get_eeprom_data, 5494 .get_monitor_dump = goya_get_monitor_dump, 5495 .send_cpu_message = goya_send_cpu_message, 5496 .pci_bars_map = goya_pci_bars_map, 5497 .init_iatu = goya_init_iatu, 5498 .rreg = hl_rreg, 5499 .wreg = hl_wreg, 5500 .halt_coresight = goya_halt_coresight, 5501 .ctx_init = goya_ctx_init, 5502 .ctx_fini = goya_ctx_fini, 5503 .pre_schedule_cs = goya_pre_schedule_cs, 5504 .get_queue_id_for_cq = goya_get_queue_id_for_cq, 5505 .load_firmware_to_device = goya_load_firmware_to_device, 5506 .load_boot_fit_to_device = goya_load_boot_fit_to_device, 5507 .get_signal_cb_size = goya_get_signal_cb_size, 5508 .get_wait_cb_size = goya_get_wait_cb_size, 5509 .gen_signal_cb = goya_gen_signal_cb, 5510 .gen_wait_cb = goya_gen_wait_cb, 5511 .reset_sob = goya_reset_sob, 5512 .reset_sob_group = goya_reset_sob_group, 5513 .get_device_time = goya_get_device_time, 5514 .pb_print_security_errors = NULL, 5515 .collective_wait_init_cs = goya_collective_wait_init_cs, 5516 .collective_wait_create_jobs = goya_collective_wait_create_jobs, 5517 .get_dec_base_addr = NULL, 5518 .scramble_addr = hl_mmu_scramble_addr, 5519 .descramble_addr = hl_mmu_descramble_addr, 5520 .ack_protection_bits_errors = goya_ack_protection_bits_errors, 5521 .get_hw_block_id = goya_get_hw_block_id, 5522 .hw_block_mmap = goya_block_mmap, 5523 .enable_events_from_fw = goya_enable_events_from_fw, 5524 .ack_mmu_errors = goya_ack_mmu_page_fault_or_access_error, 5525 .map_pll_idx_to_fw_idx = goya_map_pll_idx_to_fw_idx, 5526 .init_firmware_preload_params = goya_init_firmware_preload_params, 5527 .init_firmware_loader = goya_init_firmware_loader, 5528 .init_cpu_scrambler_dram = goya_cpu_init_scrambler_dram, 5529 .state_dump_init = goya_state_dump_init, 5530 .get_sob_addr = &goya_get_sob_addr, 5531 .set_pci_memory_regions = goya_set_pci_memory_regions, 5532 .get_stream_master_qid_arr = goya_get_stream_master_qid_arr, 5533 .check_if_razwi_happened = goya_check_if_razwi_happened, 5534 .mmu_get_real_page_size = hl_mmu_get_real_page_size, 5535 .access_dev_mem = hl_access_dev_mem, 5536 .set_dram_bar_base = goya_set_ddr_bar_base, 5537 .send_device_activity = goya_send_device_activity, 5538 .set_dram_properties = goya_set_dram_properties, 5539 .set_binning_masks = goya_set_binning_masks, 5540 }; 5541 5542 /* 5543 * goya_set_asic_funcs - set Goya function pointers 5544 * 5545 * @*hdev: pointer to hl_device structure 5546 * 5547 */ 5548 void goya_set_asic_funcs(struct hl_device *hdev) 5549 { 5550 hdev->asic_funcs = &goya_funcs; 5551 } 5552