1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2020-2022 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef GAUDI2P_H_ 9 #define GAUDI2P_H_ 10 11 #include <uapi/drm/habanalabs_accel.h> 12 #include "../common/habanalabs.h" 13 #include <linux/habanalabs/hl_boot_if.h> 14 #include "../include/gaudi2/gaudi2.h" 15 #include "../include/gaudi2/gaudi2_packets.h" 16 #include "../include/gaudi2/gaudi2_fw_if.h" 17 #include "../include/gaudi2/gaudi2_async_events.h" 18 19 #define GAUDI2_LINUX_FW_FILE "habanalabs/gaudi2/gaudi2-fit.itb" 20 #define GAUDI2_BOOT_FIT_FILE "habanalabs/gaudi2/gaudi2-boot-fit.itb" 21 22 #define MMU_PAGE_TABLES_INITIAL_SIZE 0x10000000 /* 256MB */ 23 24 #define GAUDI2_CPU_TIMEOUT_USEC 30000000 /* 30s */ 25 26 #define NUMBER_OF_PDMA_QUEUES 2 27 #define NUMBER_OF_EDMA_QUEUES 8 28 #define NUMBER_OF_MME_QUEUES 4 29 #define NUMBER_OF_TPC_QUEUES 25 30 #define NUMBER_OF_NIC_QUEUES 24 31 #define NUMBER_OF_ROT_QUEUES 2 32 #define NUMBER_OF_CPU_QUEUES 1 33 34 #define NUMBER_OF_HW_QUEUES ((NUMBER_OF_PDMA_QUEUES + \ 35 NUMBER_OF_EDMA_QUEUES + \ 36 NUMBER_OF_MME_QUEUES + \ 37 NUMBER_OF_TPC_QUEUES + \ 38 NUMBER_OF_NIC_QUEUES + \ 39 NUMBER_OF_ROT_QUEUES + \ 40 NUMBER_OF_CPU_QUEUES) * \ 41 NUM_OF_PQ_PER_QMAN) 42 43 #define NUMBER_OF_QUEUES (NUMBER_OF_CPU_QUEUES + NUMBER_OF_HW_QUEUES) 44 45 #define DCORE_NUM_OF_SOB \ 46 (((mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8191 - \ 47 mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2) 48 49 #define DCORE_NUM_OF_MONITORS \ 50 (((mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2047 - \ 51 mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2) 52 53 #define NUMBER_OF_DEC ((NUM_OF_DEC_PER_DCORE * NUM_OF_DCORES) + NUMBER_OF_PCIE_DEC) 54 55 /* Map all arcs dccm + arc schedulers acp blocks */ 56 #define NUM_OF_USER_ACP_BLOCKS (NUM_OF_SCHEDULER_ARC + 2) 57 #define NUM_OF_USER_NIC_UMR_BLOCKS 15 58 #define NUM_OF_EXPOSED_SM_BLOCKS ((NUM_OF_DCORES - 1) * 2) 59 #define NUM_USER_MAPPED_BLOCKS \ 60 (NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + NUMBER_OF_DEC + \ 61 NUM_OF_EXPOSED_SM_BLOCKS + \ 62 (NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS)) 63 64 /* Within the user mapped array, decoder entries start post all the ARC related 65 * entries 66 */ 67 #define USR_MAPPED_BLK_DEC_START_IDX \ 68 (NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + \ 69 (NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS)) 70 71 #define USR_MAPPED_BLK_SM_START_IDX \ 72 (NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + NUMBER_OF_DEC + \ 73 (NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS)) 74 75 #define SM_OBJS_BLOCK_SIZE (mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 - \ 76 mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0) 77 78 #define GAUDI2_MAX_PENDING_CS 64 79 80 #if !IS_MAX_PENDING_CS_VALID(GAUDI2_MAX_PENDING_CS) 81 #error "GAUDI2_MAX_PENDING_CS must be power of 2 and greater than 1" 82 #endif 83 84 #define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */ 85 86 #define GAUDI2_PREBOOT_REQ_TIMEOUT_USEC 25000000 /* 25s */ 87 #define GAUDI2_PREBOOT_EXTENDED_REQ_TIMEOUT_USEC 85000000 /* 85s */ 88 89 #define GAUDI2_BOOT_FIT_REQ_TIMEOUT_USEC 10000000 /* 10s */ 90 91 #define GAUDI2_NIC_CLK_FREQ 450000000ull /* 450 MHz */ 92 93 #define DC_POWER_DEFAULT 60000 /* 60W */ 94 95 #define GAUDI2_HBM_NUM 6 96 97 #define DMA_MAX_TRANSFER_SIZE U32_MAX 98 99 #define GAUDI2_DEFAULT_CARD_NAME "HL225" 100 101 #define QMAN_STREAMS 4 102 103 #define NUM_OF_MME_SBTE_PORTS 5 104 #define NUM_OF_MME_WB_PORTS 2 105 106 #define GAUDI2_ENGINE_ID_DCORE_OFFSET \ 107 (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0) 108 109 /* DRAM Memory Map */ 110 111 #define CPU_FW_IMAGE_SIZE 0x10000000 /* 256MB */ 112 113 /* This define should be used only when working in a debug mode without dram. 114 * When working with dram, the driver size will be calculated dynamically. 115 */ 116 #define NIC_DEFAULT_DRV_SIZE 0x20000000 /* 512MB */ 117 118 #define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE 119 120 #define NIC_NUMBER_OF_PORTS NIC_NUMBER_OF_ENGINES 121 122 #define NUMBER_OF_PCIE_DEC 2 123 #define PCIE_DEC_SHIFT 8 124 125 #define SRAM_USER_BASE_OFFSET 0 126 127 /* cluster binning */ 128 #define MAX_FAULTY_HBMS 1 129 #define GAUDI2_XBAR_EDGE_FULL_MASK 0xF 130 #define GAUDI2_EDMA_FULL_MASK 0xFF 131 #define GAUDI2_DRAM_FULL_MASK 0x3F 132 133 /* Host virtual address space. */ 134 135 #define VA_HOST_SPACE_PAGE_START 0xFFF0000000000000ull 136 #define VA_HOST_SPACE_PAGE_END 0xFFF0800000000000ull /* 140TB */ 137 138 #define VA_HOST_SPACE_HPAGE_START 0xFFF0800000000000ull 139 #define VA_HOST_SPACE_HPAGE_END 0xFFF1000000000000ull /* 140TB */ 140 141 /* 140TB */ 142 #define VA_HOST_SPACE_PAGE_SIZE (VA_HOST_SPACE_PAGE_END - VA_HOST_SPACE_PAGE_START) 143 144 /* 140TB */ 145 #define VA_HOST_SPACE_HPAGE_SIZE (VA_HOST_SPACE_HPAGE_END - VA_HOST_SPACE_HPAGE_START) 146 147 #define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_PAGE_SIZE + VA_HOST_SPACE_HPAGE_SIZE) 148 149 #define HOST_SPACE_INTERNAL_CB_SZ SZ_2M 150 151 /* 152 * HBM virtual address space 153 * Gaudi2 has 6 HBM devices, each supporting 16GB total of 96GB at most. 154 * No core separation is supported so we can have one chunk of virtual address 155 * space just above the physical ones. 156 * The virtual address space starts immediately after the end of the physical 157 * address space which is determined at run-time. 158 */ 159 #define VA_HBM_SPACE_END 0x1002000000000000ull 160 161 #define HW_CAP_PLL BIT_ULL(0) 162 #define HW_CAP_DRAM BIT_ULL(1) 163 #define HW_CAP_PMMU BIT_ULL(2) 164 #define HW_CAP_CPU BIT_ULL(3) 165 #define HW_CAP_MSIX BIT_ULL(4) 166 167 #define HW_CAP_CPU_Q BIT_ULL(5) 168 #define HW_CAP_CPU_Q_SHIFT 5 169 170 #define HW_CAP_CLK_GATE BIT_ULL(6) 171 #define HW_CAP_KDMA BIT_ULL(7) 172 #define HW_CAP_SRAM_SCRAMBLER BIT_ULL(8) 173 174 #define HW_CAP_DCORE0_DMMU0 BIT_ULL(9) 175 #define HW_CAP_DCORE0_DMMU1 BIT_ULL(10) 176 #define HW_CAP_DCORE0_DMMU2 BIT_ULL(11) 177 #define HW_CAP_DCORE0_DMMU3 BIT_ULL(12) 178 #define HW_CAP_DCORE1_DMMU0 BIT_ULL(13) 179 #define HW_CAP_DCORE1_DMMU1 BIT_ULL(14) 180 #define HW_CAP_DCORE1_DMMU2 BIT_ULL(15) 181 #define HW_CAP_DCORE1_DMMU3 BIT_ULL(16) 182 #define HW_CAP_DCORE2_DMMU0 BIT_ULL(17) 183 #define HW_CAP_DCORE2_DMMU1 BIT_ULL(18) 184 #define HW_CAP_DCORE2_DMMU2 BIT_ULL(19) 185 #define HW_CAP_DCORE2_DMMU3 BIT_ULL(20) 186 #define HW_CAP_DCORE3_DMMU0 BIT_ULL(21) 187 #define HW_CAP_DCORE3_DMMU1 BIT_ULL(22) 188 #define HW_CAP_DCORE3_DMMU2 BIT_ULL(23) 189 #define HW_CAP_DCORE3_DMMU3 BIT_ULL(24) 190 #define HW_CAP_DMMU_MASK GENMASK_ULL(24, 9) 191 #define HW_CAP_DMMU_SHIFT 9 192 #define HW_CAP_PDMA_MASK BIT_ULL(26) 193 #define HW_CAP_EDMA_MASK GENMASK_ULL(34, 27) 194 #define HW_CAP_EDMA_SHIFT 27 195 #define HW_CAP_MME_MASK GENMASK_ULL(38, 35) 196 #define HW_CAP_MME_SHIFT 35 197 #define HW_CAP_ROT_MASK GENMASK_ULL(40, 39) 198 #define HW_CAP_ROT_SHIFT 39 199 #define HW_CAP_HBM_SCRAMBLER_HW_RESET BIT_ULL(41) 200 #define HW_CAP_HBM_SCRAMBLER_SW_RESET BIT_ULL(42) 201 #define HW_CAP_HBM_SCRAMBLER_MASK (HW_CAP_HBM_SCRAMBLER_HW_RESET | \ 202 HW_CAP_HBM_SCRAMBLER_SW_RESET) 203 #define HW_CAP_HBM_SCRAMBLER_SHIFT 41 204 #define HW_CAP_RESERVED BIT(43) 205 #define HW_CAP_MMU_MASK (HW_CAP_PMMU | HW_CAP_DMMU_MASK) 206 207 /* Range Registers */ 208 #define RR_TYPE_SHORT 0 209 #define RR_TYPE_LONG 1 210 #define RR_TYPE_SHORT_PRIV 2 211 #define RR_TYPE_LONG_PRIV 3 212 #define NUM_SHORT_LBW_RR 14 213 #define NUM_LONG_LBW_RR 4 214 #define NUM_SHORT_HBW_RR 6 215 #define NUM_LONG_HBW_RR 4 216 217 /* RAZWI initiator coordinates- X- 5 bits, Y- 4 bits */ 218 #define RAZWI_INITIATOR_X_SHIFT 0 219 #define RAZWI_INITIATOR_X_MASK 0x1F 220 #define RAZWI_INITIATOR_Y_SHIFT 5 221 #define RAZWI_INITIATOR_Y_MASK 0xF 222 223 #define RTR_ID_X_Y(x, y) \ 224 ((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \ 225 (((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT)) 226 227 /* decoders have separate mask */ 228 #define HW_CAP_DEC_SHIFT 0 229 #define HW_CAP_DEC_MASK GENMASK_ULL(9, 0) 230 231 /* TPCs have separate mask */ 232 #define HW_CAP_TPC_SHIFT 0 233 #define HW_CAP_TPC_MASK GENMASK_ULL(24, 0) 234 235 /* nics have separate mask */ 236 #define HW_CAP_NIC_SHIFT 0 237 #define HW_CAP_NIC_MASK GENMASK_ULL(NIC_NUMBER_OF_ENGINES - 1, 0) 238 239 #define GAUDI2_ARC_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 28)) >> 28) 240 241 #define GAUDI2_SOB_INCREMENT_BY_ONE (FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK, 1) | \ 242 FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK, 1)) 243 244 #define GAUDI2_NUM_TESTED_QS (GAUDI2_QUEUE_ID_CPU_PQ - GAUDI2_QUEUE_ID_PDMA_0_0) 245 246 #define GAUDI2_NUM_OF_GLBL_ERR_CAUSE 8 247 248 enum gaudi2_reserved_sob_id { 249 GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST, 250 GAUDI2_RESERVED_SOB_CS_COMPLETION_LAST = 251 GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1, 252 GAUDI2_RESERVED_SOB_KDMA_COMPLETION, 253 GAUDI2_RESERVED_SOB_DEC_NRM_FIRST, 254 GAUDI2_RESERVED_SOB_DEC_NRM_LAST = 255 GAUDI2_RESERVED_SOB_DEC_NRM_FIRST + NUMBER_OF_DEC - 1, 256 GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST, 257 GAUDI2_RESERVED_SOB_DEC_ABNRM_LAST = 258 GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + NUMBER_OF_DEC - 1, 259 GAUDI2_RESERVED_SOB_NUMBER 260 }; 261 262 enum gaudi2_reserved_mon_id { 263 GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST, 264 GAUDI2_RESERVED_MON_CS_COMPLETION_LAST = 265 GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1, 266 GAUDI2_RESERVED_MON_KDMA_COMPLETION, 267 GAUDI2_RESERVED_MON_DEC_NRM_FIRST, 268 GAUDI2_RESERVED_MON_DEC_NRM_LAST = 269 GAUDI2_RESERVED_MON_DEC_NRM_FIRST + 3 * NUMBER_OF_DEC - 1, 270 GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST, 271 GAUDI2_RESERVED_MON_DEC_ABNRM_LAST = 272 GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST + 3 * NUMBER_OF_DEC - 1, 273 GAUDI2_RESERVED_MON_NUMBER 274 }; 275 276 enum gaudi2_reserved_cq_id { 277 GAUDI2_RESERVED_CQ_CS_COMPLETION, 278 GAUDI2_RESERVED_CQ_KDMA_COMPLETION, 279 GAUDI2_RESERVED_CQ_NUMBER 280 }; 281 282 /* 283 * Gaudi2 subtitute TPCs Numbering 284 * At most- two faulty TPCs are allowed 285 * First replacement to a faulty TPC will be TPC24, second- TPC23 286 */ 287 enum substitude_tpc { 288 FAULTY_TPC_SUBTS_1_TPC_24, 289 FAULTY_TPC_SUBTS_2_TPC_23, 290 MAX_FAULTY_TPCS 291 }; 292 293 enum gaudi2_dma_core_id { 294 DMA_CORE_ID_PDMA0, /* Dcore 0 */ 295 DMA_CORE_ID_PDMA1, /* Dcore 0 */ 296 DMA_CORE_ID_EDMA0, /* Dcore 0 */ 297 DMA_CORE_ID_EDMA1, /* Dcore 0 */ 298 DMA_CORE_ID_EDMA2, /* Dcore 1 */ 299 DMA_CORE_ID_EDMA3, /* Dcore 1 */ 300 DMA_CORE_ID_EDMA4, /* Dcore 2 */ 301 DMA_CORE_ID_EDMA5, /* Dcore 2 */ 302 DMA_CORE_ID_EDMA6, /* Dcore 3 */ 303 DMA_CORE_ID_EDMA7, /* Dcore 3 */ 304 DMA_CORE_ID_KDMA, /* Dcore 0 */ 305 DMA_CORE_ID_SIZE 306 }; 307 308 enum gaudi2_rotator_id { 309 ROTATOR_ID_0, 310 ROTATOR_ID_1, 311 ROTATOR_ID_SIZE, 312 }; 313 314 enum gaudi2_mme_id { 315 MME_ID_DCORE0, 316 MME_ID_DCORE1, 317 MME_ID_DCORE2, 318 MME_ID_DCORE3, 319 MME_ID_SIZE, 320 }; 321 322 enum gaudi2_tpc_id { 323 TPC_ID_DCORE0_TPC0, 324 TPC_ID_DCORE0_TPC1, 325 TPC_ID_DCORE0_TPC2, 326 TPC_ID_DCORE0_TPC3, 327 TPC_ID_DCORE0_TPC4, 328 TPC_ID_DCORE0_TPC5, 329 TPC_ID_DCORE1_TPC0, 330 TPC_ID_DCORE1_TPC1, 331 TPC_ID_DCORE1_TPC2, 332 TPC_ID_DCORE1_TPC3, 333 TPC_ID_DCORE1_TPC4, 334 TPC_ID_DCORE1_TPC5, 335 TPC_ID_DCORE2_TPC0, 336 TPC_ID_DCORE2_TPC1, 337 TPC_ID_DCORE2_TPC2, 338 TPC_ID_DCORE2_TPC3, 339 TPC_ID_DCORE2_TPC4, 340 TPC_ID_DCORE2_TPC5, 341 TPC_ID_DCORE3_TPC0, 342 TPC_ID_DCORE3_TPC1, 343 TPC_ID_DCORE3_TPC2, 344 TPC_ID_DCORE3_TPC3, 345 TPC_ID_DCORE3_TPC4, 346 TPC_ID_DCORE3_TPC5, 347 /* the PCI TPC is placed last (mapped liked HW) */ 348 TPC_ID_DCORE0_TPC6, 349 TPC_ID_SIZE, 350 }; 351 352 enum gaudi2_dec_id { 353 DEC_ID_DCORE0_DEC0, 354 DEC_ID_DCORE0_DEC1, 355 DEC_ID_DCORE1_DEC0, 356 DEC_ID_DCORE1_DEC1, 357 DEC_ID_DCORE2_DEC0, 358 DEC_ID_DCORE2_DEC1, 359 DEC_ID_DCORE3_DEC0, 360 DEC_ID_DCORE3_DEC1, 361 DEC_ID_PCIE_VDEC0, 362 DEC_ID_PCIE_VDEC1, 363 DEC_ID_SIZE, 364 }; 365 366 enum gaudi2_hbm_id { 367 HBM_ID0, 368 HBM_ID1, 369 HBM_ID2, 370 HBM_ID3, 371 HBM_ID4, 372 HBM_ID5, 373 HBM_ID_SIZE, 374 }; 375 376 /* specific EDMA enumeration */ 377 enum gaudi2_edma_id { 378 EDMA_ID_DCORE0_INSTANCE0, 379 EDMA_ID_DCORE0_INSTANCE1, 380 EDMA_ID_DCORE1_INSTANCE0, 381 EDMA_ID_DCORE1_INSTANCE1, 382 EDMA_ID_DCORE2_INSTANCE0, 383 EDMA_ID_DCORE2_INSTANCE1, 384 EDMA_ID_DCORE3_INSTANCE0, 385 EDMA_ID_DCORE3_INSTANCE1, 386 EDMA_ID_SIZE, 387 }; 388 389 /* User interrupt count is aligned with HW CQ count. 390 * We have 64 CQ's per dcore, CQ0 in dcore 0 is reserved for legacy mode 391 */ 392 #define GAUDI2_NUM_USER_INTERRUPTS 255 393 #define GAUDI2_NUM_RESERVED_INTERRUPTS 1 394 #define GAUDI2_TOTAL_USER_INTERRUPTS (GAUDI2_NUM_USER_INTERRUPTS + GAUDI2_NUM_RESERVED_INTERRUPTS) 395 396 enum gaudi2_irq_num { 397 GAUDI2_IRQ_NUM_EVENT_QUEUE = GAUDI2_EVENT_QUEUE_MSIX_IDX, 398 GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM, 399 GAUDI2_IRQ_NUM_DCORE0_DEC0_ABNRM, 400 GAUDI2_IRQ_NUM_DCORE0_DEC1_NRM, 401 GAUDI2_IRQ_NUM_DCORE0_DEC1_ABNRM, 402 GAUDI2_IRQ_NUM_DCORE1_DEC0_NRM, 403 GAUDI2_IRQ_NUM_DCORE1_DEC0_ABNRM, 404 GAUDI2_IRQ_NUM_DCORE1_DEC1_NRM, 405 GAUDI2_IRQ_NUM_DCORE1_DEC1_ABNRM, 406 GAUDI2_IRQ_NUM_DCORE2_DEC0_NRM, 407 GAUDI2_IRQ_NUM_DCORE2_DEC0_ABNRM, 408 GAUDI2_IRQ_NUM_DCORE2_DEC1_NRM, 409 GAUDI2_IRQ_NUM_DCORE2_DEC1_ABNRM, 410 GAUDI2_IRQ_NUM_DCORE3_DEC0_NRM, 411 GAUDI2_IRQ_NUM_DCORE3_DEC0_ABNRM, 412 GAUDI2_IRQ_NUM_DCORE3_DEC1_NRM, 413 GAUDI2_IRQ_NUM_DCORE3_DEC1_ABNRM, 414 GAUDI2_IRQ_NUM_SHARED_DEC0_NRM, 415 GAUDI2_IRQ_NUM_SHARED_DEC0_ABNRM, 416 GAUDI2_IRQ_NUM_SHARED_DEC1_NRM, 417 GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM, 418 GAUDI2_IRQ_NUM_DEC_LAST = GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM, 419 GAUDI2_IRQ_NUM_COMPLETION, 420 GAUDI2_IRQ_NUM_NIC_PORT_FIRST, 421 GAUDI2_IRQ_NUM_NIC_PORT_LAST = (GAUDI2_IRQ_NUM_NIC_PORT_FIRST + NIC_NUMBER_OF_PORTS - 1), 422 GAUDI2_IRQ_NUM_TPC_ASSERT, 423 GAUDI2_IRQ_NUM_EQ_ERROR, 424 GAUDI2_IRQ_NUM_RESERVED_FIRST, 425 GAUDI2_IRQ_NUM_RESERVED_LAST = (GAUDI2_MSIX_ENTRIES - GAUDI2_TOTAL_USER_INTERRUPTS - 1), 426 GAUDI2_IRQ_NUM_UNEXPECTED_ERROR = RESERVED_MSIX_UNEXPECTED_USER_ERROR_INTERRUPT, 427 GAUDI2_IRQ_NUM_USER_FIRST = GAUDI2_IRQ_NUM_UNEXPECTED_ERROR + 1, 428 GAUDI2_IRQ_NUM_USER_LAST = (GAUDI2_IRQ_NUM_USER_FIRST + GAUDI2_NUM_USER_INTERRUPTS - 1), 429 GAUDI2_IRQ_NUM_LAST = (GAUDI2_MSIX_ENTRIES - 1) 430 }; 431 432 static_assert(GAUDI2_IRQ_NUM_USER_FIRST > GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM); 433 434 /** 435 * struct dup_block_ctx - context to initialize unit instances across multiple 436 * blocks where block can be either a dcore of duplicated 437 * common module. this code relies on constant offsets 438 * of blocks and unit instances in a block. 439 * @instance_cfg_fn: instance specific configuration function. 440 * @data: private configuration data. 441 * @base: base address of the first instance in the first block. 442 * @block_off: subsequent blocks address spacing. 443 * @instance_off: subsequent block's instances address spacing. 444 * @enabled_mask: mask of enabled instances (1- enabled, 0- disabled). 445 * @blocks: number of blocks. 446 * @instances: unit instances per block. 447 */ 448 struct dup_block_ctx { 449 void (*instance_cfg_fn)(struct hl_device *hdev, u64 base, void *data); 450 void *data; 451 u64 base; 452 u64 block_off; 453 u64 instance_off; 454 u64 enabled_mask; 455 unsigned int blocks; 456 unsigned int instances; 457 }; 458 459 /** 460 * struct gaudi2_queues_test_info - Holds the address of a the messages used for testing the 461 * device queues. 462 * @dma_addr: the address used by the HW for accessing the message. 463 * @kern_addr: The address used by the driver for accessing the message. 464 */ 465 struct gaudi2_queues_test_info { 466 dma_addr_t dma_addr; 467 void *kern_addr; 468 }; 469 470 /** 471 * struct gaudi2_device - ASIC specific manage structure. 472 * @cpucp_info_get: get information on device from CPU-CP 473 * @mapped_blocks: array that holds the base address and size of all blocks 474 * the user can map. 475 * @lfsr_rand_seeds: array of MME ACC random seeds to set. 476 * @hw_queues_lock: protects the H/W queues from concurrent access. 477 * @scratchpad_kernel_address: general purpose PAGE_SIZE contiguous memory, 478 * this memory region should be write-only. 479 * currently used for HBW QMAN writes which is 480 * redundant. 481 * @scratchpad_bus_address: scratchpad bus address 482 * @virt_msix_db_cpu_addr: host memory page for the virtual MSI-X doorbell. 483 * @virt_msix_db_dma_addr: bus address of the page for the virtual MSI-X doorbell. 484 * @dram_bar_cur_addr: current address of DRAM PCI bar. 485 * @hw_cap_initialized: This field contains a bit per H/W engine. When that 486 * engine is initialized, that bit is set by the driver to 487 * signal we can use this engine in later code paths. 488 * Each bit is cleared upon reset of its corresponding H/W 489 * engine. 490 * @active_hw_arc: This field contains a bit per ARC of an H/W engine with 491 * exception of TPC and NIC engines. Once an engine arc is 492 * initialized, its respective bit is set. Driver can uniquely 493 * identify each initialized ARC and use this information in 494 * later code paths. Each respective bit is cleared upon reset 495 * of its corresponding ARC of the H/W engine. 496 * @dec_hw_cap_initialized: This field contains a bit per decoder H/W engine. 497 * When that engine is initialized, that bit is set by 498 * the driver to signal we can use this engine in later 499 * code paths. 500 * Each bit is cleared upon reset of its corresponding H/W 501 * engine. 502 * @tpc_hw_cap_initialized: This field contains a bit per TPC H/W engine. 503 * When that engine is initialized, that bit is set by 504 * the driver to signal we can use this engine in later 505 * code paths. 506 * Each bit is cleared upon reset of its corresponding H/W 507 * engine. 508 * @active_tpc_arc: This field contains a bit per ARC of the TPC engines. 509 * Once an engine arc is initialized, its respective bit is 510 * set. Each respective bit is cleared upon reset of its 511 * corresponding ARC of the TPC engine. 512 * @nic_hw_cap_initialized: This field contains a bit per nic H/W engine. 513 * @active_nic_arc: This field contains a bit per ARC of the NIC engines. 514 * Once an engine arc is initialized, its respective bit is 515 * set. Each respective bit is cleared upon reset of its 516 * corresponding ARC of the NIC engine. 517 * @hw_events: array that holds all H/W events that are defined valid. 518 * @events_stat: array that holds histogram of all received events. 519 * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset. 520 * @num_of_valid_hw_events: used to hold the number of valid H/W events. 521 * @nic_ports: array that holds all NIC ports manage structures. 522 * @nic_macros: array that holds all NIC macro manage structures. 523 * @core_info: core info to be used by the Ethernet driver. 524 * @aux_ops: functions for core <-> aux drivers communication. 525 * @flush_db_fifo: flag to force flush DB FIFO after a write. 526 * @hbm_cfg: HBM subsystem settings 527 * @hw_queues_lock_mutex: used by simulator instead of hw_queues_lock. 528 * @queues_test_info: information used by the driver when testing the HW queues. 529 */ 530 struct gaudi2_device { 531 int (*cpucp_info_get)(struct hl_device *hdev); 532 533 struct user_mapped_block mapped_blocks[NUM_USER_MAPPED_BLOCKS]; 534 int lfsr_rand_seeds[MME_NUM_OF_LFSR_SEEDS]; 535 536 spinlock_t hw_queues_lock; 537 538 void *scratchpad_kernel_address; 539 dma_addr_t scratchpad_bus_address; 540 541 void *virt_msix_db_cpu_addr; 542 dma_addr_t virt_msix_db_dma_addr; 543 544 u64 dram_bar_cur_addr; 545 u64 hw_cap_initialized; 546 u64 active_hw_arc; 547 u64 dec_hw_cap_initialized; 548 u64 tpc_hw_cap_initialized; 549 u64 active_tpc_arc; 550 u64 nic_hw_cap_initialized; 551 u64 active_nic_arc; 552 u32 hw_events[GAUDI2_EVENT_SIZE]; 553 u32 events_stat[GAUDI2_EVENT_SIZE]; 554 u32 events_stat_aggregate[GAUDI2_EVENT_SIZE]; 555 u32 num_of_valid_hw_events; 556 557 /* Queue testing */ 558 struct gaudi2_queues_test_info queues_test_info[GAUDI2_NUM_TESTED_QS]; 559 }; 560 561 /* 562 * Types of the Gaudi2 IP blocks, used by special blocks iterator. 563 * Required for scenarios where only particular block types can be 564 * addressed (e.g., special PLDM images). 565 */ 566 enum gaudi2_block_types { 567 GAUDI2_BLOCK_TYPE_PLL, 568 GAUDI2_BLOCK_TYPE_RTR, 569 GAUDI2_BLOCK_TYPE_CPU, 570 GAUDI2_BLOCK_TYPE_HIF, 571 GAUDI2_BLOCK_TYPE_HBM, 572 GAUDI2_BLOCK_TYPE_NIC, 573 GAUDI2_BLOCK_TYPE_PCIE, 574 GAUDI2_BLOCK_TYPE_PCIE_PMA, 575 GAUDI2_BLOCK_TYPE_PDMA, 576 GAUDI2_BLOCK_TYPE_EDMA, 577 GAUDI2_BLOCK_TYPE_PMMU, 578 GAUDI2_BLOCK_TYPE_PSOC, 579 GAUDI2_BLOCK_TYPE_ROT, 580 GAUDI2_BLOCK_TYPE_ARC_FARM, 581 GAUDI2_BLOCK_TYPE_DEC, 582 GAUDI2_BLOCK_TYPE_MME, 583 GAUDI2_BLOCK_TYPE_EU_BIST, 584 GAUDI2_BLOCK_TYPE_SYNC_MNGR, 585 GAUDI2_BLOCK_TYPE_STLB, 586 GAUDI2_BLOCK_TYPE_TPC, 587 GAUDI2_BLOCK_TYPE_HMMU, 588 GAUDI2_BLOCK_TYPE_SRAM, 589 GAUDI2_BLOCK_TYPE_XBAR, 590 GAUDI2_BLOCK_TYPE_KDMA, 591 GAUDI2_BLOCK_TYPE_XDMA, 592 GAUDI2_BLOCK_TYPE_XFT, 593 GAUDI2_BLOCK_TYPE_MAX 594 }; 595 596 extern const u32 gaudi2_dma_core_blocks_bases[DMA_CORE_ID_SIZE]; 597 extern const u32 gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_SIZE]; 598 extern const u32 gaudi2_mme_acc_blocks_bases[MME_ID_SIZE]; 599 extern const u32 gaudi2_mme_ctrl_lo_blocks_bases[MME_ID_SIZE]; 600 extern const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES]; 601 extern const u32 gaudi2_rot_blocks_bases[ROTATOR_ID_SIZE]; 602 603 void gaudi2_iterate_tpcs(struct hl_device *hdev, struct iterate_module_ctx *ctx); 604 int gaudi2_coresight_init(struct hl_device *hdev); 605 int gaudi2_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data); 606 void gaudi2_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx); 607 void gaudi2_init_blocks(struct hl_device *hdev, struct dup_block_ctx *cfg_ctx); 608 bool gaudi2_is_hmmu_enabled(struct hl_device *hdev, int dcore_id, int hmmu_id); 609 void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val, 610 u64 max_val); 611 void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause, 612 u32 offended_addr); 613 int gaudi2_init_security(struct hl_device *hdev); 614 void gaudi2_ack_protection_bits_errors(struct hl_device *hdev); 615 int gaudi2_send_device_activity(struct hl_device *hdev, bool open); 616 617 #endif /* GAUDI2P_H_ */ 618