1e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2e65e175bSOded Gabbay * 3e65e175bSOded Gabbay * Copyright 2019-2022 HabanaLabs, Ltd. 4e65e175bSOded Gabbay * All Rights Reserved. 5e65e175bSOded Gabbay * 6e65e175bSOded Gabbay */ 7e65e175bSOded Gabbay 8e65e175bSOded Gabbay #ifndef GAUDIP_H_ 9e65e175bSOded Gabbay #define GAUDIP_H_ 10e65e175bSOded Gabbay 11e65e175bSOded Gabbay #include <uapi/drm/habanalabs_accel.h> 12e65e175bSOded Gabbay #include "../common/habanalabs.h" 13*2b76129cSDavid Meriin #include <linux/habanalabs/hl_boot_if.h> 14e65e175bSOded Gabbay #include "../include/gaudi/gaudi_packets.h" 15e65e175bSOded Gabbay #include "../include/gaudi/gaudi.h" 16e65e175bSOded Gabbay #include "../include/gaudi/gaudi_async_events.h" 17e65e175bSOded Gabbay #include "../include/gaudi/gaudi_fw_if.h" 18e65e175bSOded Gabbay 19e65e175bSOded Gabbay #define NUMBER_OF_EXT_HW_QUEUES 8 20e65e175bSOded Gabbay #define NUMBER_OF_CMPLT_QUEUES NUMBER_OF_EXT_HW_QUEUES 21e65e175bSOded Gabbay #define NUMBER_OF_CPU_HW_QUEUES 1 22e65e175bSOded Gabbay #define NUMBER_OF_INT_HW_QUEUES 100 23e65e175bSOded Gabbay #define NUMBER_OF_HW_QUEUES (NUMBER_OF_EXT_HW_QUEUES + \ 24e65e175bSOded Gabbay NUMBER_OF_CPU_HW_QUEUES + \ 25e65e175bSOded Gabbay NUMBER_OF_INT_HW_QUEUES) 26e65e175bSOded Gabbay 27e65e175bSOded Gabbay /* 10 NIC QMANs, DMA5 QMAN, TPC7 QMAN */ 28e65e175bSOded Gabbay #define NUMBER_OF_COLLECTIVE_QUEUES 12 29e65e175bSOded Gabbay #define NUMBER_OF_SOBS_IN_GRP 11 30e65e175bSOded Gabbay 31e65e175bSOded Gabbay #define GAUDI_STREAM_MASTER_ARR_SIZE 8 32e65e175bSOded Gabbay 33e65e175bSOded Gabbay #define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */ 34e65e175bSOded Gabbay 35e65e175bSOded Gabbay #define GAUDI_MAX_CLK_FREQ 2200000000ull /* 2200 MHz */ 36e65e175bSOded Gabbay 37e65e175bSOded Gabbay #define MAX_POWER_DEFAULT_PCI 200000 /* 200W */ 38e65e175bSOded Gabbay #define MAX_POWER_DEFAULT_PMC 350000 /* 350W */ 39e65e175bSOded Gabbay 40e65e175bSOded Gabbay #define DC_POWER_DEFAULT_PCI 60000 /* 60W */ 41e65e175bSOded Gabbay #define DC_POWER_DEFAULT_PMC 60000 /* 60W */ 42e65e175bSOded Gabbay 43e65e175bSOded Gabbay #define DC_POWER_DEFAULT_PMC_SEC 97000 /* 97W */ 44e65e175bSOded Gabbay 45e65e175bSOded Gabbay #define GAUDI_CPU_TIMEOUT_USEC 30000000 /* 30s */ 46e65e175bSOded Gabbay 47e65e175bSOded Gabbay #define TPC_ENABLED_MASK 0xFF 48e65e175bSOded Gabbay 49e65e175bSOded Gabbay #define GAUDI_HBM_SIZE_32GB 0x800000000ull 50e65e175bSOded Gabbay #define GAUDI_HBM_DEVICES 4 51e65e175bSOded Gabbay #define GAUDI_HBM_CHANNELS 8 52e65e175bSOded Gabbay #define GAUDI_HBM_CFG_BASE (mmHBM0_BASE - CFG_BASE) 53e65e175bSOded Gabbay #define GAUDI_HBM_CFG_OFFSET (mmHBM1_BASE - mmHBM0_BASE) 54e65e175bSOded Gabbay 55e65e175bSOded Gabbay #define DMA_MAX_TRANSFER_SIZE U32_MAX 56e65e175bSOded Gabbay 57e65e175bSOded Gabbay #define GAUDI_DEFAULT_CARD_NAME "HL205" 58e65e175bSOded Gabbay 59e65e175bSOded Gabbay #define GAUDI_MAX_PENDING_CS SZ_16K 60e65e175bSOded Gabbay 61e65e175bSOded Gabbay #if !IS_MAX_PENDING_CS_VALID(GAUDI_MAX_PENDING_CS) 62e65e175bSOded Gabbay #error "GAUDI_MAX_PENDING_CS must be power of 2 and greater than 1" 63e65e175bSOded Gabbay #endif 64e65e175bSOded Gabbay 65e65e175bSOded Gabbay #define PCI_DMA_NUMBER_OF_CHNLS 2 66e65e175bSOded Gabbay #define HBM_DMA_NUMBER_OF_CHNLS 6 67e65e175bSOded Gabbay #define DMA_NUMBER_OF_CHNLS (PCI_DMA_NUMBER_OF_CHNLS + \ 68e65e175bSOded Gabbay HBM_DMA_NUMBER_OF_CHNLS) 69e65e175bSOded Gabbay 70e65e175bSOded Gabbay #define MME_NUMBER_OF_SLAVE_ENGINES 2 71e65e175bSOded Gabbay #define MME_NUMBER_OF_ENGINES (MME_NUMBER_OF_MASTER_ENGINES + \ 72e65e175bSOded Gabbay MME_NUMBER_OF_SLAVE_ENGINES) 73e65e175bSOded Gabbay #define MME_NUMBER_OF_QMANS (MME_NUMBER_OF_MASTER_ENGINES * \ 74e65e175bSOded Gabbay QMAN_STREAMS) 75e65e175bSOded Gabbay 76e65e175bSOded Gabbay #define QMAN_STREAMS 4 77e65e175bSOded Gabbay #define PQ_FETCHER_CACHE_SIZE 8 78e65e175bSOded Gabbay 79e65e175bSOded Gabbay #define DMA_QMAN_OFFSET (mmDMA1_QM_BASE - mmDMA0_QM_BASE) 80e65e175bSOded Gabbay #define TPC_QMAN_OFFSET (mmTPC1_QM_BASE - mmTPC0_QM_BASE) 81e65e175bSOded Gabbay #define MME_QMAN_OFFSET (mmMME1_QM_BASE - mmMME0_QM_BASE) 82e65e175bSOded Gabbay #define NIC_MACRO_QMAN_OFFSET (mmNIC1_QM0_BASE - mmNIC0_QM0_BASE) 83e65e175bSOded Gabbay #define NIC_ENGINE_QMAN_OFFSET (mmNIC0_QM1_BASE - mmNIC0_QM0_BASE) 84e65e175bSOded Gabbay 85e65e175bSOded Gabbay #define TPC_CFG_OFFSET (mmTPC1_CFG_BASE - mmTPC0_CFG_BASE) 86e65e175bSOded Gabbay 87e65e175bSOded Gabbay #define DMA_CORE_OFFSET (mmDMA1_CORE_BASE - mmDMA0_CORE_BASE) 88e65e175bSOded Gabbay 89e65e175bSOded Gabbay #define QMAN_LDMA_SRC_OFFSET (mmDMA0_CORE_SRC_BASE_LO - mmDMA0_CORE_CFG_0) 90e65e175bSOded Gabbay #define QMAN_LDMA_DST_OFFSET (mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0) 91e65e175bSOded Gabbay #define QMAN_LDMA_SIZE_OFFSET (mmDMA0_CORE_DST_TSIZE_0 - mmDMA0_CORE_CFG_0) 92e65e175bSOded Gabbay 93e65e175bSOded Gabbay #define QMAN_CPDMA_SRC_OFFSET (mmDMA0_QM_CQ_PTR_LO_4 - mmDMA0_CORE_CFG_0) 94e65e175bSOded Gabbay #define QMAN_CPDMA_DST_OFFSET (mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0) 95e65e175bSOded Gabbay #define QMAN_CPDMA_SIZE_OFFSET (mmDMA0_QM_CQ_TSIZE_4 - mmDMA0_CORE_CFG_0) 96e65e175bSOded Gabbay 97e65e175bSOded Gabbay #define SIF_RTR_CTRL_OFFSET (mmSIF_RTR_CTRL_1_BASE - mmSIF_RTR_CTRL_0_BASE) 98e65e175bSOded Gabbay 99e65e175bSOded Gabbay #define NIF_RTR_CTRL_OFFSET (mmNIF_RTR_CTRL_1_BASE - mmNIF_RTR_CTRL_0_BASE) 100e65e175bSOded Gabbay 101e65e175bSOded Gabbay #define MME_ACC_OFFSET (mmMME1_ACC_BASE - mmMME0_ACC_BASE) 102e65e175bSOded Gabbay #define SRAM_BANK_OFFSET (mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE) 103e65e175bSOded Gabbay 104e65e175bSOded Gabbay #define NUM_OF_SOB_IN_BLOCK \ 105e65e175bSOded Gabbay (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \ 106e65e175bSOded Gabbay mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2) 107e65e175bSOded Gabbay 108e65e175bSOded Gabbay #define NUM_OF_MONITORS_IN_BLOCK \ 109e65e175bSOded Gabbay (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 - \ 110e65e175bSOded Gabbay mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2) 111e65e175bSOded Gabbay 112e65e175bSOded Gabbay #define MONITOR_MAX_SOBS 8 113e65e175bSOded Gabbay 114e65e175bSOded Gabbay /* DRAM Memory Map */ 115e65e175bSOded Gabbay 116e65e175bSOded Gabbay #define CPU_FW_IMAGE_SIZE 0x10000000 /* 256MB */ 117e65e175bSOded Gabbay #define MMU_PAGE_TABLES_SIZE 0x0BF00000 /* 191MB */ 118e65e175bSOded Gabbay #define MMU_CACHE_MNG_SIZE 0x00100000 /* 1MB */ 119e65e175bSOded Gabbay #define RESERVED 0x04000000 /* 64MB */ 120e65e175bSOded Gabbay 121e65e175bSOded Gabbay #define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE 122e65e175bSOded Gabbay #define MMU_PAGE_TABLES_ADDR (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE) 123e65e175bSOded Gabbay #define MMU_CACHE_MNG_ADDR (MMU_PAGE_TABLES_ADDR + MMU_PAGE_TABLES_SIZE) 124e65e175bSOded Gabbay 125e65e175bSOded Gabbay #define DRAM_DRIVER_END_ADDR (MMU_CACHE_MNG_ADDR + MMU_CACHE_MNG_SIZE +\ 126e65e175bSOded Gabbay RESERVED) 127e65e175bSOded Gabbay 128e65e175bSOded Gabbay #define DRAM_BASE_ADDR_USER 0x20000000 129e65e175bSOded Gabbay 130e65e175bSOded Gabbay #if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER) 131e65e175bSOded Gabbay #error "Driver must reserve no more than 512MB" 132e65e175bSOded Gabbay #endif 133e65e175bSOded Gabbay 134e65e175bSOded Gabbay /* Internal QMANs PQ sizes */ 135e65e175bSOded Gabbay 136e65e175bSOded Gabbay #define MME_QMAN_LENGTH 1024 137e65e175bSOded Gabbay #define MME_QMAN_SIZE_IN_BYTES (MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE) 138e65e175bSOded Gabbay 139e65e175bSOded Gabbay #define HBM_DMA_QMAN_LENGTH 4096 140e65e175bSOded Gabbay #define HBM_DMA_QMAN_SIZE_IN_BYTES \ 141e65e175bSOded Gabbay (HBM_DMA_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE) 142e65e175bSOded Gabbay 143e65e175bSOded Gabbay #define TPC_QMAN_LENGTH 1024 144e65e175bSOded Gabbay #define TPC_QMAN_SIZE_IN_BYTES (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE) 145e65e175bSOded Gabbay 146e65e175bSOded Gabbay #define NIC_QMAN_LENGTH 4096 147e65e175bSOded Gabbay #define NIC_QMAN_SIZE_IN_BYTES (NIC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE) 148e65e175bSOded Gabbay 149e65e175bSOded Gabbay 150e65e175bSOded Gabbay #define SRAM_USER_BASE_OFFSET GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 151e65e175bSOded Gabbay 152e65e175bSOded Gabbay /* Virtual address space */ 153e65e175bSOded Gabbay #define VA_HOST_SPACE_START 0x1000000000000ull /* 256TB */ 154e65e175bSOded Gabbay #define VA_HOST_SPACE_END 0x3FF8000000000ull /* 1PB - 512GB */ 155e65e175bSOded Gabbay #define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \ 156e65e175bSOded Gabbay VA_HOST_SPACE_START) /* 767TB */ 157e65e175bSOded Gabbay #define HOST_SPACE_INTERNAL_CB_SZ SZ_2M 158e65e175bSOded Gabbay 159e65e175bSOded Gabbay #define HW_CAP_PLL BIT(0) 160e65e175bSOded Gabbay #define HW_CAP_HBM BIT(1) 161e65e175bSOded Gabbay #define HW_CAP_MMU BIT(2) 162e65e175bSOded Gabbay #define HW_CAP_MME BIT(3) 163e65e175bSOded Gabbay #define HW_CAP_CPU BIT(4) 164e65e175bSOded Gabbay #define HW_CAP_PCI_DMA BIT(5) 165e65e175bSOded Gabbay #define HW_CAP_MSI BIT(6) 166e65e175bSOded Gabbay #define HW_CAP_CPU_Q BIT(7) 167e65e175bSOded Gabbay #define HW_CAP_HBM_DMA BIT(8) 168e65e175bSOded Gabbay #define HW_CAP_SRAM_SCRAMBLER BIT(10) 169e65e175bSOded Gabbay #define HW_CAP_HBM_SCRAMBLER BIT(11) 170e65e175bSOded Gabbay 171e65e175bSOded Gabbay #define HW_CAP_NIC0 BIT(14) 172e65e175bSOded Gabbay #define HW_CAP_NIC1 BIT(15) 173e65e175bSOded Gabbay #define HW_CAP_NIC2 BIT(16) 174e65e175bSOded Gabbay #define HW_CAP_NIC3 BIT(17) 175e65e175bSOded Gabbay #define HW_CAP_NIC4 BIT(18) 176e65e175bSOded Gabbay #define HW_CAP_NIC5 BIT(19) 177e65e175bSOded Gabbay #define HW_CAP_NIC6 BIT(20) 178e65e175bSOded Gabbay #define HW_CAP_NIC7 BIT(21) 179e65e175bSOded Gabbay #define HW_CAP_NIC8 BIT(22) 180e65e175bSOded Gabbay #define HW_CAP_NIC9 BIT(23) 181e65e175bSOded Gabbay #define HW_CAP_NIC_MASK GENMASK(23, 14) 182e65e175bSOded Gabbay #define HW_CAP_NIC_SHIFT 14 183e65e175bSOded Gabbay 184e65e175bSOded Gabbay #define HW_CAP_TPC0 BIT(24) 185e65e175bSOded Gabbay #define HW_CAP_TPC1 BIT(25) 186e65e175bSOded Gabbay #define HW_CAP_TPC2 BIT(26) 187e65e175bSOded Gabbay #define HW_CAP_TPC3 BIT(27) 188e65e175bSOded Gabbay #define HW_CAP_TPC4 BIT(28) 189e65e175bSOded Gabbay #define HW_CAP_TPC5 BIT(29) 190e65e175bSOded Gabbay #define HW_CAP_TPC6 BIT(30) 191e65e175bSOded Gabbay #define HW_CAP_TPC7 BIT(31) 192e65e175bSOded Gabbay #define HW_CAP_TPC_MASK GENMASK(31, 24) 193e65e175bSOded Gabbay #define HW_CAP_TPC_SHIFT 24 194e65e175bSOded Gabbay 195e65e175bSOded Gabbay #define NEXT_SYNC_OBJ_ADDR_INTERVAL \ 196e65e175bSOded Gabbay (mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0 - \ 197e65e175bSOded Gabbay mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) 198e65e175bSOded Gabbay #define NUM_OF_MME_ENGINES 2 199e65e175bSOded Gabbay #define NUM_OF_MME_SUB_ENGINES 2 200e65e175bSOded Gabbay #define NUM_OF_TPC_ENGINES 8 201e65e175bSOded Gabbay #define NUM_OF_DMA_ENGINES 8 202e65e175bSOded Gabbay #define NUM_OF_QUEUES 5 203e65e175bSOded Gabbay #define NUM_OF_STREAMS 4 204e65e175bSOded Gabbay #define NUM_OF_FENCES 4 205e65e175bSOded Gabbay 206e65e175bSOded Gabbay 207e65e175bSOded Gabbay #define GAUDI_CPU_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 39)) >> 39) 208e65e175bSOded Gabbay #define GAUDI_PCI_TO_CPU_ADDR(addr) \ 209e65e175bSOded Gabbay do { \ 210e65e175bSOded Gabbay (addr) &= ~GENMASK_ULL(49, 39); \ 211e65e175bSOded Gabbay (addr) |= BIT_ULL(39); \ 212e65e175bSOded Gabbay } while (0) 213e65e175bSOded Gabbay #define GAUDI_CPU_TO_PCI_ADDR(addr, extension) \ 214e65e175bSOded Gabbay do { \ 215e65e175bSOded Gabbay (addr) &= ~GENMASK_ULL(49, 39); \ 216e65e175bSOded Gabbay (addr) |= (u64) (extension) << 39; \ 217e65e175bSOded Gabbay } while (0) 218e65e175bSOded Gabbay 219e65e175bSOded Gabbay enum gaudi_dma_channels { 220e65e175bSOded Gabbay GAUDI_PCI_DMA_1, 221e65e175bSOded Gabbay GAUDI_PCI_DMA_2, 222e65e175bSOded Gabbay GAUDI_HBM_DMA_1, 223e65e175bSOded Gabbay GAUDI_HBM_DMA_2, 224e65e175bSOded Gabbay GAUDI_HBM_DMA_3, 225e65e175bSOded Gabbay GAUDI_HBM_DMA_4, 226e65e175bSOded Gabbay GAUDI_HBM_DMA_5, 227e65e175bSOded Gabbay GAUDI_HBM_DMA_6, 228e65e175bSOded Gabbay GAUDI_DMA_MAX 229e65e175bSOded Gabbay }; 230e65e175bSOded Gabbay 231e65e175bSOded Gabbay enum gaudi_tpc_mask { 232e65e175bSOded Gabbay GAUDI_TPC_MASK_TPC0 = 0x01, 233e65e175bSOded Gabbay GAUDI_TPC_MASK_TPC1 = 0x02, 234e65e175bSOded Gabbay GAUDI_TPC_MASK_TPC2 = 0x04, 235e65e175bSOded Gabbay GAUDI_TPC_MASK_TPC3 = 0x08, 236e65e175bSOded Gabbay GAUDI_TPC_MASK_TPC4 = 0x10, 237e65e175bSOded Gabbay GAUDI_TPC_MASK_TPC5 = 0x20, 238e65e175bSOded Gabbay GAUDI_TPC_MASK_TPC6 = 0x40, 239e65e175bSOded Gabbay GAUDI_TPC_MASK_TPC7 = 0x80, 240e65e175bSOded Gabbay GAUDI_TPC_MASK_ALL = 0xFF 241e65e175bSOded Gabbay }; 242e65e175bSOded Gabbay 243e65e175bSOded Gabbay enum gaudi_nic_mask { 244e65e175bSOded Gabbay GAUDI_NIC_MASK_NIC0 = 0x01, 245e65e175bSOded Gabbay GAUDI_NIC_MASK_NIC1 = 0x02, 246e65e175bSOded Gabbay GAUDI_NIC_MASK_NIC2 = 0x04, 247e65e175bSOded Gabbay GAUDI_NIC_MASK_NIC3 = 0x08, 248e65e175bSOded Gabbay GAUDI_NIC_MASK_NIC4 = 0x10, 249e65e175bSOded Gabbay GAUDI_NIC_MASK_NIC5 = 0x20, 250e65e175bSOded Gabbay GAUDI_NIC_MASK_NIC6 = 0x40, 251e65e175bSOded Gabbay GAUDI_NIC_MASK_NIC7 = 0x80, 252e65e175bSOded Gabbay GAUDI_NIC_MASK_NIC8 = 0x100, 253e65e175bSOded Gabbay GAUDI_NIC_MASK_NIC9 = 0x200, 254e65e175bSOded Gabbay GAUDI_NIC_MASK_ALL = 0x3FF 255e65e175bSOded Gabbay }; 256e65e175bSOded Gabbay 257e65e175bSOded Gabbay /* 258e65e175bSOded Gabbay * struct gaudi_hw_sob_group - H/W SOB group info. 259e65e175bSOded Gabbay * @hdev: habanalabs device structure. 260e65e175bSOded Gabbay * @kref: refcount of this SOB group. group will reset once refcount is zero. 261e65e175bSOded Gabbay * @base_sob_id: base sob id of this SOB group. 262e65e175bSOded Gabbay * @queue_id: id of the queue that waits on this sob group 263e65e175bSOded Gabbay */ 264e65e175bSOded Gabbay struct gaudi_hw_sob_group { 265e65e175bSOded Gabbay struct hl_device *hdev; 266e65e175bSOded Gabbay struct kref kref; 267e65e175bSOded Gabbay u32 base_sob_id; 268e65e175bSOded Gabbay u32 queue_id; 269e65e175bSOded Gabbay }; 270e65e175bSOded Gabbay 271e65e175bSOded Gabbay #define NUM_SOB_GROUPS (HL_RSVD_SOBS * QMAN_STREAMS) 272e65e175bSOded Gabbay /** 273e65e175bSOded Gabbay * struct gaudi_collective_properties - 274e65e175bSOded Gabbay * holds all SOB groups and queues info reserved for the collective 275e65e175bSOded Gabbay * @hw_sob_group: H/W SOB groups. 276e65e175bSOded Gabbay * @next_sob_group_val: the next value to use for the currently used SOB group. 277e65e175bSOded Gabbay * @curr_sob_group_idx: the index of the currently used SOB group. 278e65e175bSOded Gabbay * @mstr_sob_mask: pre-defined masks for collective master monitors 279e65e175bSOded Gabbay */ 280e65e175bSOded Gabbay struct gaudi_collective_properties { 281e65e175bSOded Gabbay struct gaudi_hw_sob_group hw_sob_group[NUM_SOB_GROUPS]; 282e65e175bSOded Gabbay u16 next_sob_group_val[QMAN_STREAMS]; 283e65e175bSOded Gabbay u8 curr_sob_group_idx[QMAN_STREAMS]; 284e65e175bSOded Gabbay u8 mstr_sob_mask[HL_COLLECTIVE_RSVD_MSTR_MONS]; 285e65e175bSOded Gabbay }; 286e65e175bSOded Gabbay 287e65e175bSOded Gabbay /** 288e65e175bSOded Gabbay * struct gaudi_internal_qman_info - Internal QMAN information. 289e65e175bSOded Gabbay * @pq_kernel_addr: Kernel address of the PQ memory area in the host. 290e65e175bSOded Gabbay * @pq_dma_addr: DMA address of the PQ memory area in the host. 291e65e175bSOded Gabbay * @pq_size: Size of allocated host memory for PQ. 292e65e175bSOded Gabbay */ 293e65e175bSOded Gabbay struct gaudi_internal_qman_info { 294e65e175bSOded Gabbay void *pq_kernel_addr; 295e65e175bSOded Gabbay dma_addr_t pq_dma_addr; 296e65e175bSOded Gabbay size_t pq_size; 297e65e175bSOded Gabbay }; 298e65e175bSOded Gabbay 299e65e175bSOded Gabbay /** 300e65e175bSOded Gabbay * struct gaudi_device - ASIC specific manage structure. 301e65e175bSOded Gabbay * @cpucp_info_get: get information on device from CPU-CP 302e65e175bSOded Gabbay * @hw_queues_lock: protects the H/W queues from concurrent access. 303e65e175bSOded Gabbay * @internal_qmans: Internal QMANs information. The array size is larger than 304e65e175bSOded Gabbay * the actual number of internal queues because they are not in 305e65e175bSOded Gabbay * consecutive order. 306e65e175bSOded Gabbay * @hbm_bar_cur_addr: current address of HBM PCI bar. 307e65e175bSOded Gabbay * @events: array that holds all event id's 308e65e175bSOded Gabbay * @events_stat: array that holds histogram of all received events. 309e65e175bSOded Gabbay * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset 310e65e175bSOded Gabbay * @hw_cap_initialized: This field contains a bit per H/W engine. When that 311e65e175bSOded Gabbay * engine is initialized, that bit is set by the driver to 312e65e175bSOded Gabbay * signal we can use this engine in later code paths. 313e65e175bSOded Gabbay * Each bit is cleared upon reset of its corresponding H/W 314e65e175bSOded Gabbay * engine. 315e65e175bSOded Gabbay * @mmu_cache_inv_pi: PI for MMU cache invalidation flow. The H/W expects an 316e65e175bSOded Gabbay * 8-bit value so use u8. 317e65e175bSOded Gabbay */ 318e65e175bSOded Gabbay struct gaudi_device { 319e65e175bSOded Gabbay int (*cpucp_info_get)(struct hl_device *hdev); 320e65e175bSOded Gabbay 321e65e175bSOded Gabbay /* TODO: remove hw_queues_lock after moving to scheduler code */ 322e65e175bSOded Gabbay spinlock_t hw_queues_lock; 323e65e175bSOded Gabbay 324e65e175bSOded Gabbay struct gaudi_internal_qman_info internal_qmans[GAUDI_QUEUE_ID_SIZE]; 325e65e175bSOded Gabbay 326e65e175bSOded Gabbay struct gaudi_collective_properties collective_props; 327e65e175bSOded Gabbay 328e65e175bSOded Gabbay u64 hbm_bar_cur_addr; 329e65e175bSOded Gabbay 330e65e175bSOded Gabbay u32 events[GAUDI_EVENT_SIZE]; 331e65e175bSOded Gabbay u32 events_stat[GAUDI_EVENT_SIZE]; 332e65e175bSOded Gabbay u32 events_stat_aggregate[GAUDI_EVENT_SIZE]; 333e65e175bSOded Gabbay u32 hw_cap_initialized; 334e65e175bSOded Gabbay u8 mmu_cache_inv_pi; 335e65e175bSOded Gabbay }; 336e65e175bSOded Gabbay 337e65e175bSOded Gabbay void gaudi_init_security(struct hl_device *hdev); 338e65e175bSOded Gabbay void gaudi_ack_protection_bits_errors(struct hl_device *hdev); 339e65e175bSOded Gabbay int gaudi_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data); 340e65e175bSOded Gabbay void gaudi_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx); 341e65e175bSOded Gabbay void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid); 342e65e175bSOded Gabbay 343e65e175bSOded Gabbay #endif /* GAUDIP_H_ */ 344