1 // SPDX-License-Identifier: GPL-2.0 2 3 /* 4 * Copyright 2016-2022 HabanaLabs, Ltd. 5 * All Rights Reserved. 6 */ 7 8 #include "habanalabs.h" 9 10 #include <linux/slab.h> 11 12 /** 13 * struct hl_eqe_work - This structure is used to schedule work of EQ 14 * entry and cpucp_reset event 15 * 16 * @eq_work: workqueue object to run when EQ entry is received 17 * @hdev: pointer to device structure 18 * @eq_entry: copy of the EQ entry 19 */ 20 struct hl_eqe_work { 21 struct work_struct eq_work; 22 struct hl_device *hdev; 23 struct hl_eq_entry eq_entry; 24 }; 25 26 /** 27 * hl_cq_inc_ptr - increment ci or pi of cq 28 * 29 * @ptr: the current ci or pi value of the completion queue 30 * 31 * Increment ptr by 1. If it reaches the number of completion queue 32 * entries, set it to 0 33 */ 34 inline u32 hl_cq_inc_ptr(u32 ptr) 35 { 36 ptr++; 37 if (unlikely(ptr == HL_CQ_LENGTH)) 38 ptr = 0; 39 return ptr; 40 } 41 42 /** 43 * hl_eq_inc_ptr - increment ci of eq 44 * 45 * @ptr: the current ci value of the event queue 46 * 47 * Increment ptr by 1. If it reaches the number of event queue 48 * entries, set it to 0 49 */ 50 static inline u32 hl_eq_inc_ptr(u32 ptr) 51 { 52 ptr++; 53 if (unlikely(ptr == HL_EQ_LENGTH)) 54 ptr = 0; 55 return ptr; 56 } 57 58 static void irq_handle_eqe(struct work_struct *work) 59 { 60 struct hl_eqe_work *eqe_work = container_of(work, struct hl_eqe_work, 61 eq_work); 62 struct hl_device *hdev = eqe_work->hdev; 63 64 hdev->asic_funcs->handle_eqe(hdev, &eqe_work->eq_entry); 65 66 kfree(eqe_work); 67 } 68 69 /** 70 * job_finish - queue job finish work 71 * 72 * @hdev: pointer to device structure 73 * @cs_seq: command submission sequence 74 * @cq: completion queue 75 * @timestamp: interrupt timestamp 76 * 77 */ 78 static void job_finish(struct hl_device *hdev, u32 cs_seq, struct hl_cq *cq, ktime_t timestamp) 79 { 80 struct hl_hw_queue *queue; 81 struct hl_cs_job *job; 82 83 queue = &hdev->kernel_queues[cq->hw_queue_id]; 84 job = queue->shadow_queue[hl_pi_2_offset(cs_seq)]; 85 job->timestamp = timestamp; 86 queue_work(hdev->cq_wq[cq->cq_idx], &job->finish_work); 87 88 atomic_inc(&queue->ci); 89 } 90 91 /** 92 * cs_finish - queue all cs jobs finish work 93 * 94 * @hdev: pointer to device structure 95 * @cs_seq: command submission sequence 96 * @timestamp: interrupt timestamp 97 * 98 */ 99 static void cs_finish(struct hl_device *hdev, u16 cs_seq, ktime_t timestamp) 100 { 101 struct asic_fixed_properties *prop = &hdev->asic_prop; 102 struct hl_hw_queue *queue; 103 struct hl_cs *cs; 104 struct hl_cs_job *job; 105 106 cs = hdev->shadow_cs_queue[cs_seq & (prop->max_pending_cs - 1)]; 107 if (!cs) { 108 dev_warn(hdev->dev, 109 "No pointer to CS in shadow array at index %d\n", 110 cs_seq); 111 return; 112 } 113 114 list_for_each_entry(job, &cs->job_list, cs_node) { 115 queue = &hdev->kernel_queues[job->hw_queue_id]; 116 atomic_inc(&queue->ci); 117 } 118 119 cs->completion_timestamp = timestamp; 120 queue_work(hdev->cs_cmplt_wq, &cs->finish_work); 121 } 122 123 /** 124 * hl_irq_handler_cq - irq handler for completion queue 125 * 126 * @irq: irq number 127 * @arg: pointer to completion queue structure 128 * 129 */ 130 irqreturn_t hl_irq_handler_cq(int irq, void *arg) 131 { 132 struct hl_cq *cq = arg; 133 struct hl_device *hdev = cq->hdev; 134 bool shadow_index_valid, entry_ready; 135 u16 shadow_index; 136 struct hl_cq_entry *cq_entry, *cq_base; 137 ktime_t timestamp = ktime_get(); 138 139 if (hdev->disabled) { 140 dev_dbg(hdev->dev, 141 "Device disabled but received IRQ %d for CQ %d\n", 142 irq, cq->hw_queue_id); 143 return IRQ_HANDLED; 144 } 145 146 cq_base = cq->kernel_address; 147 148 while (1) { 149 cq_entry = (struct hl_cq_entry *) &cq_base[cq->ci]; 150 151 entry_ready = !!FIELD_GET(CQ_ENTRY_READY_MASK, 152 le32_to_cpu(cq_entry->data)); 153 if (!entry_ready) 154 break; 155 156 /* Make sure we read CQ entry contents after we've 157 * checked the ownership bit. 158 */ 159 dma_rmb(); 160 161 shadow_index_valid = 162 !!FIELD_GET(CQ_ENTRY_SHADOW_INDEX_VALID_MASK, 163 le32_to_cpu(cq_entry->data)); 164 165 shadow_index = FIELD_GET(CQ_ENTRY_SHADOW_INDEX_MASK, 166 le32_to_cpu(cq_entry->data)); 167 168 /* 169 * CQ interrupt handler has 2 modes of operation: 170 * 1. Interrupt per CS completion: (Single CQ for all queues) 171 * CQ entry represents a completed CS 172 * 173 * 2. Interrupt per CS job completion in queue: (CQ per queue) 174 * CQ entry represents a completed job in a certain queue 175 */ 176 if (shadow_index_valid && !hdev->disabled) { 177 if (hdev->asic_prop.completion_mode == 178 HL_COMPLETION_MODE_CS) 179 cs_finish(hdev, shadow_index, timestamp); 180 else 181 job_finish(hdev, shadow_index, cq, timestamp); 182 } 183 184 /* Clear CQ entry ready bit */ 185 cq_entry->data = cpu_to_le32(le32_to_cpu(cq_entry->data) & 186 ~CQ_ENTRY_READY_MASK); 187 188 cq->ci = hl_cq_inc_ptr(cq->ci); 189 190 /* Increment free slots */ 191 atomic_inc(&cq->free_slots_cnt); 192 } 193 194 return IRQ_HANDLED; 195 } 196 197 /* 198 * hl_ts_free_objects - handler of the free objects workqueue. 199 * This function should put refcount to objects that the registration node 200 * took refcount to them. 201 * @work: workqueue object pointer 202 */ 203 static void hl_ts_free_objects(struct work_struct *work) 204 { 205 struct timestamp_reg_work_obj *job = 206 container_of(work, struct timestamp_reg_work_obj, free_obj); 207 struct timestamp_reg_free_node *free_obj, *temp_free_obj; 208 struct list_head *free_list_head = job->free_obj_head; 209 struct hl_device *hdev = job->hdev; 210 211 list_for_each_entry_safe(free_obj, temp_free_obj, free_list_head, free_objects_node) { 212 dev_dbg(hdev->dev, "About to put refcount to buf (%p) cq_cb(%p)\n", 213 free_obj->buf, 214 free_obj->cq_cb); 215 216 hl_mmap_mem_buf_put(free_obj->buf); 217 hl_cb_put(free_obj->cq_cb); 218 kfree(free_obj); 219 } 220 221 kfree(free_list_head); 222 kfree(job); 223 } 224 225 /* 226 * This function called with spin_lock of wait_list_lock taken 227 * This function will set timestamp and delete the registration node from the 228 * wait_list_lock. 229 * and since we're protected with spin_lock here, so we cannot just put the refcount 230 * for the objects here, since the release function may be called and it's also a long 231 * logic (which might sleep also) that cannot be handled in irq context. 232 * so here we'll be filling a list with nodes of "put" jobs and then will send this 233 * list to a dedicated workqueue to do the actual put. 234 */ 235 static int handle_registration_node(struct hl_device *hdev, struct hl_user_pending_interrupt *pend, 236 struct list_head **free_list, ktime_t now, 237 u32 interrupt_id) 238 { 239 struct timestamp_reg_free_node *free_node; 240 u64 timestamp; 241 242 if (!(*free_list)) { 243 /* Alloc/Init the timestamp registration free objects list */ 244 *free_list = kmalloc(sizeof(struct list_head), GFP_ATOMIC); 245 if (!(*free_list)) 246 return -ENOMEM; 247 248 INIT_LIST_HEAD(*free_list); 249 } 250 251 free_node = kmalloc(sizeof(*free_node), GFP_ATOMIC); 252 if (!free_node) 253 return -ENOMEM; 254 255 timestamp = ktime_to_ns(now); 256 257 *pend->ts_reg_info.timestamp_kernel_addr = timestamp; 258 259 dev_dbg(hdev->dev, "Irq handle: Timestamp record (%p) ts cb address (%p), interrupt_id: %u\n", 260 pend, pend->ts_reg_info.timestamp_kernel_addr, interrupt_id); 261 262 /* Mark kernel CB node as free */ 263 pend->ts_reg_info.in_use = false; 264 list_del(&pend->wait_list_node); 265 266 /* Putting the refcount for ts_buff and cq_cb objects will be handled 267 * in workqueue context, just add job to free_list. 268 */ 269 free_node->buf = pend->ts_reg_info.buf; 270 free_node->cq_cb = pend->ts_reg_info.cq_cb; 271 list_add(&free_node->free_objects_node, *free_list); 272 273 return 0; 274 } 275 276 static void handle_user_interrupt(struct hl_device *hdev, struct hl_user_interrupt *intr) 277 { 278 struct hl_user_pending_interrupt *pend, *temp_pend; 279 struct list_head *ts_reg_free_list_head = NULL; 280 struct timestamp_reg_work_obj *job; 281 bool reg_node_handle_fail = false; 282 int rc; 283 284 /* For registration nodes: 285 * As part of handling the registration nodes, we should put refcount to 286 * some objects. the problem is that we cannot do that under spinlock 287 * or in irq handler context at all (since release functions are long and 288 * might sleep), so we will need to handle that part in workqueue context. 289 * To avoid handling kmalloc failure which compels us rolling back actions 290 * and move nodes hanged on the free list back to the interrupt wait list 291 * we always alloc the job of the WQ at the beginning. 292 */ 293 job = kmalloc(sizeof(*job), GFP_ATOMIC); 294 if (!job) 295 return; 296 297 spin_lock(&intr->wait_list_lock); 298 299 list_for_each_entry_safe(pend, temp_pend, &intr->wait_list_head, wait_list_node) { 300 if ((pend->cq_kernel_addr && *(pend->cq_kernel_addr) >= pend->cq_target_value) || 301 !pend->cq_kernel_addr) { 302 if (pend->ts_reg_info.buf) { 303 if (!reg_node_handle_fail) { 304 rc = handle_registration_node(hdev, pend, 305 &ts_reg_free_list_head, intr->timestamp, 306 intr->interrupt_id); 307 if (rc) 308 reg_node_handle_fail = true; 309 } 310 } else { 311 /* Handle wait target value node */ 312 pend->fence.timestamp = intr->timestamp; 313 complete_all(&pend->fence.completion); 314 } 315 } 316 } 317 spin_unlock(&intr->wait_list_lock); 318 319 if (ts_reg_free_list_head) { 320 INIT_WORK(&job->free_obj, hl_ts_free_objects); 321 job->free_obj_head = ts_reg_free_list_head; 322 job->hdev = hdev; 323 queue_work(hdev->ts_free_obj_wq, &job->free_obj); 324 } else { 325 kfree(job); 326 } 327 } 328 329 static void handle_tpc_interrupt(struct hl_device *hdev) 330 { 331 u64 event_mask; 332 u32 flags; 333 334 event_mask = HL_NOTIFIER_EVENT_TPC_ASSERT | 335 HL_NOTIFIER_EVENT_USER_ENGINE_ERR | 336 HL_NOTIFIER_EVENT_DEVICE_RESET; 337 338 flags = HL_DRV_RESET_DELAY; 339 340 dev_err_ratelimited(hdev->dev, "Received TPC assert\n"); 341 hl_device_cond_reset(hdev, flags, event_mask); 342 } 343 344 static void handle_unexpected_user_interrupt(struct hl_device *hdev) 345 { 346 dev_err_ratelimited(hdev->dev, "Received unexpected user error interrupt\n"); 347 } 348 349 /** 350 * hl_irq_handler_user_interrupt - irq handler for user interrupts 351 * 352 * @irq: irq number 353 * @arg: pointer to user interrupt structure 354 * 355 */ 356 irqreturn_t hl_irq_handler_user_interrupt(int irq, void *arg) 357 { 358 struct hl_user_interrupt *user_int = arg; 359 360 user_int->timestamp = ktime_get(); 361 362 return IRQ_WAKE_THREAD; 363 } 364 365 /** 366 * hl_irq_user_interrupt_thread_handler - irq thread handler for user interrupts. 367 * This function is invoked by threaded irq mechanism 368 * 369 * @irq: irq number 370 * @arg: pointer to user interrupt structure 371 * 372 */ 373 irqreturn_t hl_irq_user_interrupt_thread_handler(int irq, void *arg) 374 { 375 struct hl_user_interrupt *user_int = arg; 376 struct hl_device *hdev = user_int->hdev; 377 378 switch (user_int->type) { 379 case HL_USR_INTERRUPT_CQ: 380 handle_user_interrupt(hdev, &hdev->common_user_cq_interrupt); 381 382 /* Handle user cq interrupt registered on this specific irq */ 383 handle_user_interrupt(hdev, user_int); 384 break; 385 case HL_USR_INTERRUPT_DECODER: 386 handle_user_interrupt(hdev, &hdev->common_decoder_interrupt); 387 388 /* Handle decoder interrupt registered on this specific irq */ 389 handle_user_interrupt(hdev, user_int); 390 break; 391 case HL_USR_INTERRUPT_TPC: 392 handle_tpc_interrupt(hdev); 393 break; 394 case HL_USR_INTERRUPT_UNEXPECTED: 395 handle_unexpected_user_interrupt(hdev); 396 break; 397 default: 398 break; 399 } 400 401 return IRQ_HANDLED; 402 } 403 404 /** 405 * hl_irq_handler_eq - irq handler for event queue 406 * 407 * @irq: irq number 408 * @arg: pointer to event queue structure 409 * 410 */ 411 irqreturn_t hl_irq_handler_eq(int irq, void *arg) 412 { 413 struct hl_eq *eq = arg; 414 struct hl_device *hdev = eq->hdev; 415 struct hl_eq_entry *eq_entry; 416 struct hl_eq_entry *eq_base; 417 struct hl_eqe_work *handle_eqe_work; 418 bool entry_ready; 419 u32 cur_eqe, ctl; 420 u16 cur_eqe_index, event_type; 421 422 eq_base = eq->kernel_address; 423 424 while (1) { 425 cur_eqe = le32_to_cpu(eq_base[eq->ci].hdr.ctl); 426 entry_ready = !!FIELD_GET(EQ_CTL_READY_MASK, cur_eqe); 427 428 if (!entry_ready) 429 break; 430 431 cur_eqe_index = FIELD_GET(EQ_CTL_INDEX_MASK, cur_eqe); 432 if ((hdev->event_queue.check_eqe_index) && 433 (((eq->prev_eqe_index + 1) & EQ_CTL_INDEX_MASK) != cur_eqe_index)) { 434 dev_err(hdev->dev, 435 "EQE %#x in queue is ready but index does not match %d!=%d", 436 cur_eqe, 437 ((eq->prev_eqe_index + 1) & EQ_CTL_INDEX_MASK), 438 cur_eqe_index); 439 break; 440 } 441 442 eq->prev_eqe_index++; 443 444 eq_entry = &eq_base[eq->ci]; 445 446 /* 447 * Make sure we read EQ entry contents after we've 448 * checked the ownership bit. 449 */ 450 dma_rmb(); 451 452 if (hdev->disabled && !hdev->reset_info.in_compute_reset) { 453 ctl = le32_to_cpu(eq_entry->hdr.ctl); 454 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK) >> EQ_CTL_EVENT_TYPE_SHIFT); 455 dev_warn(hdev->dev, 456 "Device disabled but received an EQ event (%u)\n", event_type); 457 goto skip_irq; 458 } 459 460 handle_eqe_work = kmalloc(sizeof(*handle_eqe_work), GFP_ATOMIC); 461 if (handle_eqe_work) { 462 INIT_WORK(&handle_eqe_work->eq_work, irq_handle_eqe); 463 handle_eqe_work->hdev = hdev; 464 465 memcpy(&handle_eqe_work->eq_entry, eq_entry, 466 sizeof(*eq_entry)); 467 468 queue_work(hdev->eq_wq, &handle_eqe_work->eq_work); 469 } 470 skip_irq: 471 /* Clear EQ entry ready bit */ 472 eq_entry->hdr.ctl = 473 cpu_to_le32(le32_to_cpu(eq_entry->hdr.ctl) & 474 ~EQ_CTL_READY_MASK); 475 476 eq->ci = hl_eq_inc_ptr(eq->ci); 477 478 hdev->asic_funcs->update_eq_ci(hdev, eq->ci); 479 } 480 481 return IRQ_HANDLED; 482 } 483 484 /** 485 * hl_irq_handler_dec_abnrm - Decoder error interrupt handler 486 * @irq: IRQ number 487 * @arg: pointer to decoder structure. 488 */ 489 irqreturn_t hl_irq_handler_dec_abnrm(int irq, void *arg) 490 { 491 struct hl_dec *dec = arg; 492 493 schedule_work(&dec->abnrm_intr_work); 494 495 return IRQ_HANDLED; 496 } 497 498 /** 499 * hl_cq_init - main initialization function for an cq object 500 * 501 * @hdev: pointer to device structure 502 * @q: pointer to cq structure 503 * @hw_queue_id: The H/W queue ID this completion queue belongs to 504 * HL_INVALID_QUEUE if cq is not attached to any specific queue 505 * 506 * Allocate dma-able memory for the completion queue and initialize fields 507 * Returns 0 on success 508 */ 509 int hl_cq_init(struct hl_device *hdev, struct hl_cq *q, u32 hw_queue_id) 510 { 511 void *p; 512 513 p = hl_asic_dma_alloc_coherent(hdev, HL_CQ_SIZE_IN_BYTES, &q->bus_address, 514 GFP_KERNEL | __GFP_ZERO); 515 if (!p) 516 return -ENOMEM; 517 518 q->hdev = hdev; 519 q->kernel_address = p; 520 q->hw_queue_id = hw_queue_id; 521 q->ci = 0; 522 q->pi = 0; 523 524 atomic_set(&q->free_slots_cnt, HL_CQ_LENGTH); 525 526 return 0; 527 } 528 529 /** 530 * hl_cq_fini - destroy completion queue 531 * 532 * @hdev: pointer to device structure 533 * @q: pointer to cq structure 534 * 535 * Free the completion queue memory 536 */ 537 void hl_cq_fini(struct hl_device *hdev, struct hl_cq *q) 538 { 539 hl_asic_dma_free_coherent(hdev, HL_CQ_SIZE_IN_BYTES, q->kernel_address, q->bus_address); 540 } 541 542 void hl_cq_reset(struct hl_device *hdev, struct hl_cq *q) 543 { 544 q->ci = 0; 545 q->pi = 0; 546 547 atomic_set(&q->free_slots_cnt, HL_CQ_LENGTH); 548 549 /* 550 * It's not enough to just reset the PI/CI because the H/W may have 551 * written valid completion entries before it was halted and therefore 552 * we need to clean the actual queues so we won't process old entries 553 * when the device is operational again 554 */ 555 556 memset(q->kernel_address, 0, HL_CQ_SIZE_IN_BYTES); 557 } 558 559 /** 560 * hl_eq_init - main initialization function for an event queue object 561 * 562 * @hdev: pointer to device structure 563 * @q: pointer to eq structure 564 * 565 * Allocate dma-able memory for the event queue and initialize fields 566 * Returns 0 on success 567 */ 568 int hl_eq_init(struct hl_device *hdev, struct hl_eq *q) 569 { 570 void *p; 571 572 p = hl_cpu_accessible_dma_pool_alloc(hdev, HL_EQ_SIZE_IN_BYTES, &q->bus_address); 573 if (!p) 574 return -ENOMEM; 575 576 q->hdev = hdev; 577 q->kernel_address = p; 578 q->ci = 0; 579 q->prev_eqe_index = 0; 580 581 return 0; 582 } 583 584 /** 585 * hl_eq_fini - destroy event queue 586 * 587 * @hdev: pointer to device structure 588 * @q: pointer to eq structure 589 * 590 * Free the event queue memory 591 */ 592 void hl_eq_fini(struct hl_device *hdev, struct hl_eq *q) 593 { 594 flush_workqueue(hdev->eq_wq); 595 596 hl_cpu_accessible_dma_pool_free(hdev, HL_EQ_SIZE_IN_BYTES, q->kernel_address); 597 } 598 599 void hl_eq_reset(struct hl_device *hdev, struct hl_eq *q) 600 { 601 q->ci = 0; 602 q->prev_eqe_index = 0; 603 604 /* 605 * It's not enough to just reset the PI/CI because the H/W may have 606 * written valid completion entries before it was halted and therefore 607 * we need to clean the actual queues so we won't process old entries 608 * when the device is operational again 609 */ 610 611 memset(q->kernel_address, 0, HL_EQ_SIZE_IN_BYTES); 612 } 613