1 /* SPDX-License-Identifier: GPL-2.0-only or MIT */ 2 /* Copyright 2025 Arm, Ltd. */ 3 4 #ifndef __ETHOSU_DEVICE_H__ 5 #define __ETHOSU_DEVICE_H__ 6 7 #include <linux/bitfield.h> 8 #include <linux/bits.h> 9 #include <linux/mutex.h> 10 #include <linux/types.h> 11 12 #include <drm/drm_device.h> 13 #include <drm/gpu_scheduler.h> 14 15 #include <drm/ethosu_accel.h> 16 17 struct clk; 18 struct gen_pool; 19 20 #define NPU_REG_ID 0x0000 21 #define NPU_REG_STATUS 0x0004 22 #define NPU_REG_CMD 0x0008 23 #define NPU_REG_RESET 0x000c 24 #define NPU_REG_QBASE 0x0010 25 #define NPU_REG_QBASE_HI 0x0014 26 #define NPU_REG_QREAD 0x0018 27 #define NPU_REG_QCONFIG 0x001c 28 #define NPU_REG_QSIZE 0x0020 29 #define NPU_REG_PROT 0x0024 30 #define NPU_REG_CONFIG 0x0028 31 #define NPU_REG_REGIONCFG 0x003c 32 #define NPU_REG_AXILIMIT0 0x0040 // U65 33 #define NPU_REG_AXILIMIT1 0x0044 // U65 34 #define NPU_REG_AXILIMIT2 0x0048 // U65 35 #define NPU_REG_AXILIMIT3 0x004c // U65 36 #define NPU_REG_MEM_ATTR0 0x0040 // U85 37 #define NPU_REG_MEM_ATTR1 0x0044 // U85 38 #define NPU_REG_MEM_ATTR2 0x0048 // U85 39 #define NPU_REG_MEM_ATTR3 0x004c // U85 40 #define NPU_REG_AXI_SRAM 0x0050 // U85 41 #define NPU_REG_AXI_EXT 0x0054 // U85 42 43 #define NPU_REG_BASEP(x) (0x0080 + (x) * 8) 44 #define NPU_REG_BASEP_HI(x) (0x0084 + (x) * 8) 45 #define NPU_BASEP_REGION_MAX 8 46 47 #define NPU_REG_PMCR 0x0180 48 #define NPU_REG_PMCNTENSET 0x0184 49 #define NPU_REG_PMCNTENCLR 0x0188 50 #define NPU_REG_PMCCNTR_LO 0x01A0 51 #define NPU_REG_PMCCNTR_HI 0x01A4 52 #define NPU_REG_PMCCNTR_CFG 0x01A8 53 #define NPU_REG_PMU_EVCNTR(x) (0x0300 + (x) * 4) 54 #define NPU_REG_PMU_EVTYPER(x) (0x0380 + (x) * 4) 55 56 #define ID_ARCH_MAJOR_MASK GENMASK(31, 28) 57 #define ID_ARCH_MINOR_MASK GENMASK(27, 20) 58 #define ID_ARCH_PATCH_MASK GENMASK(19, 16) 59 #define ID_VER_MAJOR_MASK GENMASK(11, 8) 60 #define ID_VER_MINOR_MASK GENMASK(7, 4) 61 62 #define CONFIG_MACS_PER_CC_MASK GENMASK(3, 0) 63 #define CONFIG_CMD_STREAM_VER_MASK GENMASK(7, 4) 64 65 #define STATUS_STATE_RUNNING BIT(0) 66 #define STATUS_IRQ_RAISED BIT(1) 67 #define STATUS_BUS_STATUS BIT(2) 68 #define STATUS_RESET_STATUS BIT(3) 69 #define STATUS_CMD_PARSE_ERR BIT(4) 70 #define STATUS_CMD_END_REACHED BIT(5) 71 72 #define CMD_CLEAR_IRQ BIT(1) 73 #define CMD_TRANSITION_TO_RUN BIT(0) 74 75 #define RESET_PENDING_CSL BIT(1) 76 #define RESET_PENDING_CPL BIT(0) 77 78 #define PROT_ACTIVE_CSL BIT(1) 79 80 #define PMCR_NUM_EVENT_CNT_MASK GENMASK(15, 11) 81 #define PMCR_CYCLE_CNT_RST BIT(2) 82 #define PMCR_EVENT_CNT_RST BIT(1) 83 #define PMCR_CNT_EN BIT(0) 84 85 #define PMU_EV_TYPE_NONE 0 86 #define PMU_EV_TYPE_CYCLES 0x11 87 #define PMU_EV_TYPE_IDLE 0x20 88 89 enum ethosu_cmds { 90 NPU_OP_CONV = 0x2, 91 NPU_OP_DEPTHWISE = 0x3, 92 NPU_OP_POOL = 0x5, 93 NPU_OP_ELEMENTWISE = 0x6, 94 NPU_OP_RESIZE = 0x7, // U85 only 95 NPU_OP_DMA_START = 0x10, 96 NPU_SET_IFM_PAD_TOP = 0x100, 97 NPU_SET_IFM_PAD_LEFT = 0x101, 98 NPU_SET_IFM_PAD_RIGHT = 0x102, 99 NPU_SET_IFM_PAD_BOTTOM = 0x103, 100 NPU_SET_IFM_DEPTH_M1 = 0x104, 101 NPU_SET_IFM_PRECISION = 0x105, 102 NPU_SET_IFM_BROADCAST = 0x108, 103 NPU_SET_IFM_WIDTH0_M1 = 0x10a, 104 NPU_SET_IFM_HEIGHT0_M1 = 0x10b, 105 NPU_SET_IFM_HEIGHT1_M1 = 0x10c, 106 NPU_SET_IFM_REGION = 0x10f, 107 NPU_SET_OFM_WIDTH_M1 = 0x111, 108 NPU_SET_OFM_HEIGHT_M1 = 0x112, 109 NPU_SET_OFM_DEPTH_M1 = 0x113, 110 NPU_SET_OFM_PRECISION = 0x114, 111 NPU_SET_OFM_WIDTH0_M1 = 0x11a, 112 NPU_SET_OFM_HEIGHT0_M1 = 0x11b, 113 NPU_SET_OFM_HEIGHT1_M1 = 0x11c, 114 NPU_SET_OFM_REGION = 0x11f, 115 NPU_SET_KERNEL_WIDTH_M1 = 0x120, 116 NPU_SET_KERNEL_HEIGHT_M1 = 0x121, 117 NPU_SET_KERNEL_STRIDE = 0x122, 118 NPU_SET_WEIGHT_REGION = 0x128, 119 NPU_SET_SCALE_REGION = 0x129, 120 NPU_SET_DMA0_SRC_REGION = 0x130, 121 NPU_SET_DMA0_DST_REGION = 0x131, 122 NPU_SET_DMA0_SIZE0 = 0x132, 123 NPU_SET_DMA0_SIZE1 = 0x133, 124 NPU_SET_IFM2_BROADCAST = 0x180, 125 NPU_SET_IFM2_PRECISION = 0x185, 126 NPU_SET_IFM2_WIDTH0_M1 = 0x18a, 127 NPU_SET_IFM2_HEIGHT0_M1 = 0x18b, 128 NPU_SET_IFM2_HEIGHT1_M1 = 0x18c, 129 NPU_SET_IFM2_REGION = 0x18f, 130 NPU_SET_IFM_BASE0 = 0x4000, 131 NPU_SET_IFM_BASE1 = 0x4001, 132 NPU_SET_IFM_BASE2 = 0x4002, 133 NPU_SET_IFM_BASE3 = 0x4003, 134 NPU_SET_IFM_STRIDE_X = 0x4004, 135 NPU_SET_IFM_STRIDE_Y = 0x4005, 136 NPU_SET_IFM_STRIDE_C = 0x4006, 137 NPU_SET_OFM_BASE0 = 0x4010, 138 NPU_SET_OFM_BASE1 = 0x4011, 139 NPU_SET_OFM_BASE2 = 0x4012, 140 NPU_SET_OFM_BASE3 = 0x4013, 141 NPU_SET_OFM_STRIDE_X = 0x4014, 142 NPU_SET_OFM_STRIDE_Y = 0x4015, 143 NPU_SET_OFM_STRIDE_C = 0x4016, 144 NPU_SET_WEIGHT_BASE = 0x4020, 145 NPU_SET_WEIGHT_LENGTH = 0x4021, 146 NPU_SET_SCALE_BASE = 0x4022, 147 NPU_SET_SCALE_LENGTH = 0x4023, 148 NPU_SET_DMA0_SRC = 0x4030, 149 NPU_SET_DMA0_DST = 0x4031, 150 NPU_SET_DMA0_LEN = 0x4032, 151 NPU_SET_DMA0_SRC_STRIDE0 = 0x4033, 152 NPU_SET_DMA0_SRC_STRIDE1 = 0x4034, 153 NPU_SET_DMA0_DST_STRIDE0 = 0x4035, 154 NPU_SET_DMA0_DST_STRIDE1 = 0x4036, 155 NPU_SET_IFM2_BASE0 = 0x4080, 156 NPU_SET_IFM2_BASE1 = 0x4081, 157 NPU_SET_IFM2_BASE2 = 0x4082, 158 NPU_SET_IFM2_BASE3 = 0x4083, 159 NPU_SET_IFM2_STRIDE_X = 0x4084, 160 NPU_SET_IFM2_STRIDE_Y = 0x4085, 161 NPU_SET_IFM2_STRIDE_C = 0x4086, 162 NPU_SET_WEIGHT1_BASE = 0x4090, 163 NPU_SET_WEIGHT1_LENGTH = 0x4091, 164 NPU_SET_SCALE1_BASE = 0x4092, 165 NPU_SET_WEIGHT2_BASE = 0x4092, 166 NPU_SET_SCALE1_LENGTH = 0x4093, 167 NPU_SET_WEIGHT2_LENGTH = 0x4093, 168 NPU_SET_WEIGHT3_BASE = 0x4094, 169 NPU_SET_WEIGHT3_LENGTH = 0x4095, 170 }; 171 172 #define ETHOSU_SRAM_REGION 2 /* Matching Vela compiler */ 173 174 struct ethosu_perfmon; 175 176 /** 177 * struct ethosu_device - Ethosu device 178 */ 179 struct ethosu_device { 180 /** @base: Base drm_device. */ 181 struct drm_device base; 182 183 /** @iomem: CPU mapping of the registers. */ 184 void __iomem *regs; 185 void __iomem *pmu_regs; 186 187 void __iomem *sram; 188 struct gen_pool *srampool; 189 dma_addr_t sramphys; 190 191 struct clk_bulk_data *clks; 192 int num_clks; 193 int irq; 194 195 struct drm_ethosu_npu_info npu_info; 196 197 struct ethosu_job *in_flight_job; 198 199 /* For dma_fence */ 200 spinlock_t fence_lock; 201 202 struct drm_gpu_scheduler sched; 203 /* For ethosu_job_do_push() */ 204 struct mutex sched_lock; 205 u64 fence_context; 206 u64 emit_seqno; 207 208 /* Tracks the performance monitor state. */ 209 struct { 210 /* Protects @active. */ 211 struct mutex lock; 212 213 /* Perfmon currently programmed in HW (or NULL if none). */ 214 struct ethosu_perfmon *active; 215 } perfmon_state; 216 217 struct ethosu_perfmon *global_perfmon; 218 }; 219 220 #define to_ethosu_device(drm_dev) \ 221 ((struct ethosu_device *)container_of(drm_dev, struct ethosu_device, base)) 222 223 static inline bool ethosu_is_u65(const struct ethosu_device *ethosudev) 224 { 225 return FIELD_GET(ID_ARCH_MAJOR_MASK, ethosudev->npu_info.id) == 1; 226 } 227 228 #endif 229