1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #include <drm/amdxdna_accel.h> 7 #include <drm/drm_device.h> 8 #include <drm/gpu_scheduler.h> 9 #include <linux/amd-pmf-io.h> 10 #include <linux/bits.h> 11 #include <linux/sizes.h> 12 13 #include "aie2_pci.h" 14 #include "amdxdna_mailbox.h" 15 #include "amdxdna_pci_drv.h" 16 17 /* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */ 18 #define MPNPU_PWAITMODE 0x301003C 19 #define MPNPU_PUB_SEC_INTR 0x3010060 20 #define MPNPU_PUB_PWRMGMT_INTR 0x3010064 21 #define MPNPU_PUB_SCRATCH0 0x301006C 22 #define MPNPU_PUB_SCRATCH1 0x3010070 23 #define MPNPU_PUB_SCRATCH2 0x3010074 24 #define MPNPU_PUB_SCRATCH3 0x3010078 25 #define MPNPU_PUB_SCRATCH4 0x301007C 26 #define MPNPU_PUB_SCRATCH5 0x3010080 27 #define MPNPU_PUB_SCRATCH6 0x3010084 28 #define MPNPU_PUB_SCRATCH7 0x3010088 29 #define MPNPU_PUB_SCRATCH8 0x301008C 30 #define MPNPU_PUB_SCRATCH9 0x3010090 31 #define MPNPU_PUB_SCRATCH10 0x3010094 32 #define MPNPU_PUB_SCRATCH11 0x3010098 33 #define MPNPU_PUB_SCRATCH12 0x301009C 34 #define MPNPU_PUB_SCRATCH13 0x30100A0 35 #define MPNPU_PUB_SCRATCH14 0x30100A4 36 #define MPNPU_PUB_SCRATCH15 0x30100A8 37 #define MP0_C2PMSG_73 0x3810A24 38 #define MP0_C2PMSG_123 0x3810AEC 39 40 #define MP1_C2PMSG_0 0x3B10900 41 #define MP1_C2PMSG_60 0x3B109F0 42 #define MP1_C2PMSG_61 0x3B109F4 43 44 #define MPNPU_SRAM_X2I_MAILBOX_0 0x3600000 45 #define MPNPU_SRAM_X2I_MAILBOX_15 0x361E000 46 #define MPNPU_SRAM_X2I_MAILBOX_31 0x363E000 47 #define MPNPU_SRAM_I2X_MAILBOX_31 0x363F000 48 49 #define MMNPU_APERTURE0_BASE 0x3000000 50 #define MMNPU_APERTURE1_BASE 0x3600000 51 #define MMNPU_APERTURE3_BASE 0x3810000 52 #define MMNPU_APERTURE4_BASE 0x3B10000 53 54 /* PCIe BAR Index for NPU4 */ 55 #define NPU4_REG_BAR_INDEX 0 56 #define NPU4_MBOX_BAR_INDEX 0 57 #define NPU4_PSP_BAR_INDEX 4 58 #define NPU4_SMU_BAR_INDEX 5 59 #define NPU4_SRAM_BAR_INDEX 2 60 /* Associated BARs and Apertures */ 61 #define NPU4_REG_BAR_BASE MMNPU_APERTURE0_BASE 62 #define NPU4_MBOX_BAR_BASE MMNPU_APERTURE0_BASE 63 #define NPU4_PSP_BAR_BASE MMNPU_APERTURE3_BASE 64 #define NPU4_SMU_BAR_BASE MMNPU_APERTURE4_BASE 65 #define NPU4_SRAM_BAR_BASE MMNPU_APERTURE1_BASE 66 67 #define NPU4_DPM_TOPS(ndev, hclk) (4096 * (ndev)->total_col * (hclk) / 1000000) 68 69 const struct rt_config npu4_default_rt_cfg[] = { 70 { 5, 1, AIE2_RT_CFG_INIT }, /* PDI APP LOAD MODE */ 71 { 10, 1, AIE2_RT_CFG_INIT }, /* DEBUG BUF */ 72 { 14, 0, AIE2_RT_CFG_INIT, BIT_U64(AIE2_PREEMPT) }, /* Frame boundary preemption */ 73 { 1, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */ 74 { 2, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */ 75 { 3, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */ 76 { 4, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */ 77 { 13, 0, AIE2_RT_CFG_FORCE_PREEMPT }, 78 { 14, 0, AIE2_RT_CFG_FRAME_BOUNDARY_PREEMPT }, 79 { 0 }, 80 }; 81 82 const struct dpm_clk_freq npu4_dpm_clk_table[] = { 83 {396, 792}, 84 {600, 1056}, 85 {792, 1152}, 86 {975, 1267}, 87 {975, 1267}, 88 {1056, 1408}, 89 {1152, 1584}, 90 {1267, 1800}, 91 { 0 } 92 }; 93 94 const struct amdxdna_fw_feature_tbl npu4_fw_feature_table[] = { 95 { .major = 6, .min_minor = 12 }, 96 { .features = BIT_U64(AIE2_PREEMPT), .major = 6, .min_minor = 12 }, 97 { .features = BIT_U64(AIE2_TEMPORAL_ONLY), .major = 6, .min_minor = 12 }, 98 { .features = BIT_U64(AIE2_NPU_COMMAND), .major = 6, .min_minor = 15 }, 99 { .features = BIT_U64(AIE2_UPDATE_PROPERTY), .major = 6, .min_minor = 15 }, 100 { .features = BIT_U64(AIE2_APP_HEALTH), .major = 6, .min_minor = 18 }, 101 { .features = BIT_U64(AIE2_ADD_HOST_BUFFER), .major = 6, .min_minor = 18 }, 102 { .features = BIT_U64(AIE2_GET_DEV_REVISION), .major = 6, .min_minor = 24 }, 103 { .features = AIE2_ALL_FEATURES, .major = 7 }, 104 { 0 } 105 }; 106 107 static int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) 108 { 109 int ret; 110 111 ret = aie_smu_set_dpm(ndev->aie.smu_hdl, dpm_level); 112 if (ret) 113 return ret; 114 115 ndev->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk; 116 ndev->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk; 117 ndev->max_tops = NPU4_DPM_TOPS(ndev, ndev->priv->dpm_clk_tbl[ndev->max_dpm_level].hclk); 118 ndev->curr_tops = NPU4_DPM_TOPS(ndev, ndev->hclk_freq); 119 120 XDNA_DBG(ndev->aie.xdna, "MP-NPU clock %d, H clock %d\n", 121 ndev->npuclk_freq, ndev->hclk_freq); 122 123 return 0; 124 } 125 126 static int npu4_update_counters(struct amdxdna_dev_hdl *ndev) 127 { 128 struct amd_pmf_npu_metrics npu_metrics; 129 int ret; 130 131 ret = AIE2_GET_PMF_NPU_METRICS(&npu_metrics); 132 if (ret) 133 return ret; 134 135 ndev->npuclk_freq = npu_metrics.mpnpuclk_freq; 136 ndev->hclk_freq = npu_metrics.npuclk_freq; 137 ndev->curr_tops = NPU4_DPM_TOPS(ndev, ndev->hclk_freq); 138 139 return 0; 140 } 141 142 const struct aie2_hw_ops npu4_hw_ops = { 143 .set_dpm = npu4_set_dpm, 144 .update_counters = npu4_update_counters, 145 }; 146 147 const struct amdxdna_rev_vbnv npu4_rev_vbnv_tbl[] = { 148 { AIE2_DEV_REVISION_STXA, "NPU Strix" }, 149 { AIE2_DEV_REVISION_STXB, "NPU Strix" }, 150 { AIE2_DEV_REVISION_KRK1, "NPU Krackan 1" }, 151 { AIE2_DEV_REVISION_KRK2, "NPU Krackan 2" }, 152 { AIE2_DEV_REVISION_HALO, "NPU Strix Halo" }, 153 { AIE2_DEV_REVISION_GPT1, "NPU Gorgon Point 1" }, 154 { AIE2_DEV_REVISION_GPT2, "NPU Gorgon Point 2" }, 155 { AIE2_DEV_REVISION_GPT3, "NPU Gorgon Point 3" }, 156 { 0 } 157 }; 158 159 static const struct amdxdna_dev_priv npu4_dev_priv = { 160 .fw_path = "amdnpu/17f0_10/", 161 .rt_config = npu4_default_rt_cfg, 162 .dpm_clk_tbl = npu4_dpm_clk_table, 163 .col_align = COL_ALIGN_NATURE, 164 .col_opc = 4096, 165 .mbox_dev_addr = NPU4_MBOX_BAR_BASE, 166 .mbox_size = 0, /* Use BAR size */ 167 .sram_dev_addr = NPU4_SRAM_BAR_BASE, 168 .hwctx_limit = 16, 169 .sram_offs = { 170 DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU4_SRAM, MPNPU_SRAM_X2I_MAILBOX_0), 171 DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU4_SRAM, MPNPU_SRAM_X2I_MAILBOX_15), 172 }, 173 .psp_regs_off = { 174 DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU4_PSP, MP0_C2PMSG_123), 175 DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU4_REG, MPNPU_PUB_SCRATCH3), 176 DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU4_REG, MPNPU_PUB_SCRATCH4), 177 DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU4_REG, MPNPU_PUB_SCRATCH9), 178 DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU4_PSP, MP0_C2PMSG_73), 179 DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU4_PSP, MP0_C2PMSG_123), 180 DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU4_REG, MPNPU_PUB_SCRATCH3), 181 DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU4_REG, MPNPU_PWAITMODE), 182 }, 183 .smu_regs_off = { 184 DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU4_SMU, MP1_C2PMSG_0), 185 DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU4_SMU, MP1_C2PMSG_60), 186 DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU4_SMU, MMNPU_APERTURE4_BASE), 187 DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU4_SMU, MP1_C2PMSG_61), 188 DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU4_SMU, MP1_C2PMSG_60), 189 }, 190 .hw_ops = &npu4_hw_ops 191 }; 192 193 const struct amdxdna_dev_info dev_npu4_info = { 194 .reg_bar = NPU4_REG_BAR_INDEX, 195 .mbox_bar = NPU4_MBOX_BAR_INDEX, 196 .sram_bar = NPU4_SRAM_BAR_INDEX, 197 .psp_bar = NPU4_PSP_BAR_INDEX, 198 .smu_bar = NPU4_SMU_BAR_INDEX, 199 .first_col = 0, 200 .dev_mem_buf_shift = 15, /* 32 KiB aligned */ 201 .dev_mem_base = AIE2_DEVM_BASE, 202 .dev_mem_size = AIE2_DEVM_SIZE, 203 .default_vbnv = "RyzenAI-npu4", 204 .dev_heap_max_size = AIE2_DEVM_MAX_SIZE, 205 .device_type = AMDXDNA_DEV_TYPE_KMQ, 206 .rev_vbnv_tbl = npu4_rev_vbnv_tbl, 207 .dev_priv = &npu4_dev_priv, 208 .fw_feature_tbl = npu4_fw_feature_table, 209 .ops = &aie2_ops, /* NPU4 can share NPU1's callback */ 210 }; 211