1b87f920bSLizhi Hou /* SPDX-License-Identifier: GPL-2.0 */ 2b87f920bSLizhi Hou /* 3b87f920bSLizhi Hou * Copyright (C) 2023-2024, Advanced Micro Devices, Inc. 4b87f920bSLizhi Hou */ 5b87f920bSLizhi Hou 6b87f920bSLizhi Hou #ifndef _AMDXDNA_MAILBOX_HELPER_H 7b87f920bSLizhi Hou #define _AMDXDNA_MAILBOX_HELPER_H 8b87f920bSLizhi Hou 9b87f920bSLizhi Hou #define TX_TIMEOUT 2000 /* milliseconds */ 10b87f920bSLizhi Hou #define RX_TIMEOUT 5000 /* milliseconds */ 11b87f920bSLizhi Hou 12b87f920bSLizhi Hou struct amdxdna_dev; 13b87f920bSLizhi Hou 14b87f920bSLizhi Hou struct xdna_notify { 15b87f920bSLizhi Hou struct completion comp; 16b87f920bSLizhi Hou u32 *data; 17b87f920bSLizhi Hou size_t size; 18b87f920bSLizhi Hou int error; 19b87f920bSLizhi Hou }; 20b87f920bSLizhi Hou 21b87f920bSLizhi Hou #define DECLARE_XDNA_MSG_COMMON(name, op, status) \ 22b87f920bSLizhi Hou struct name##_req req = { 0 }; \ 23b87f920bSLizhi Hou struct name##_resp resp = { status }; \ 24b87f920bSLizhi Hou struct xdna_notify hdl = { \ 25b87f920bSLizhi Hou .error = 0, \ 26b87f920bSLizhi Hou .data = (u32 *)&resp, \ 27b87f920bSLizhi Hou .size = sizeof(resp), \ 28b87f920bSLizhi Hou .comp = COMPLETION_INITIALIZER_ONSTACK(hdl.comp), \ 29b87f920bSLizhi Hou }; \ 30b87f920bSLizhi Hou struct xdna_mailbox_msg msg = { \ 31b87f920bSLizhi Hou .send_data = (u8 *)&req, \ 32b87f920bSLizhi Hou .send_size = sizeof(req), \ 33b87f920bSLizhi Hou .handle = &hdl, \ 34b87f920bSLizhi Hou .opcode = op, \ 35b87f920bSLizhi Hou .notify_cb = xdna_msg_cb, \ 36b87f920bSLizhi Hou } 37b87f920bSLizhi Hou 38*41257629SLizhi Hou int xdna_msg_cb(void *handle, void __iomem *data, size_t size); 39b87f920bSLizhi Hou int xdna_send_msg_wait(struct amdxdna_dev *xdna, struct mailbox_channel *chann, 40b87f920bSLizhi Hou struct xdna_mailbox_msg *msg); 41b87f920bSLizhi Hou 42b87f920bSLizhi Hou #endif /* _AMDXDNA_MAILBOX_HELPER_H */ 43