1*b291e4f1SLizhi Hou /* SPDX-License-Identifier: GPL-2.0 */ 2*b291e4f1SLizhi Hou /* 3*b291e4f1SLizhi Hou * Copyright (C) 2025, Advanced Micro Devices, Inc. 4*b291e4f1SLizhi Hou */ 5*b291e4f1SLizhi Hou 6*b291e4f1SLizhi Hou #ifndef _AMDXDNA_ERROR_H_ 7*b291e4f1SLizhi Hou #define _AMDXDNA_ERROR_H_ 8*b291e4f1SLizhi Hou 9*b291e4f1SLizhi Hou #include <linux/bitfield.h> 10*b291e4f1SLizhi Hou #include <linux/bits.h> 11*b291e4f1SLizhi Hou 12*b291e4f1SLizhi Hou #define AMDXDNA_ERR_DRV_AIE 4 13*b291e4f1SLizhi Hou #define AMDXDNA_ERR_SEV_CRITICAL 3 14*b291e4f1SLizhi Hou #define AMDXDNA_ERR_CLASS_AIE 2 15*b291e4f1SLizhi Hou 16*b291e4f1SLizhi Hou #define AMDXDNA_ERR_NUM_MASK GENMASK_U64(15, 0) 17*b291e4f1SLizhi Hou #define AMDXDNA_ERR_DRV_MASK GENMASK_U64(23, 16) 18*b291e4f1SLizhi Hou #define AMDXDNA_ERR_SEV_MASK GENMASK_U64(31, 24) 19*b291e4f1SLizhi Hou #define AMDXDNA_ERR_MOD_MASK GENMASK_U64(39, 32) 20*b291e4f1SLizhi Hou #define AMDXDNA_ERR_CLASS_MASK GENMASK_U64(47, 40) 21*b291e4f1SLizhi Hou 22*b291e4f1SLizhi Hou enum amdxdna_error_num { 23*b291e4f1SLizhi Hou AMDXDNA_ERROR_NUM_AIE_SATURATION = 3, 24*b291e4f1SLizhi Hou AMDXDNA_ERROR_NUM_AIE_FP, 25*b291e4f1SLizhi Hou AMDXDNA_ERROR_NUM_AIE_STREAM, 26*b291e4f1SLizhi Hou AMDXDNA_ERROR_NUM_AIE_ACCESS, 27*b291e4f1SLizhi Hou AMDXDNA_ERROR_NUM_AIE_BUS, 28*b291e4f1SLizhi Hou AMDXDNA_ERROR_NUM_AIE_INSTRUCTION, 29*b291e4f1SLizhi Hou AMDXDNA_ERROR_NUM_AIE_ECC, 30*b291e4f1SLizhi Hou AMDXDNA_ERROR_NUM_AIE_LOCK, 31*b291e4f1SLizhi Hou AMDXDNA_ERROR_NUM_AIE_DMA, 32*b291e4f1SLizhi Hou AMDXDNA_ERROR_NUM_AIE_MEM_PARITY, 33*b291e4f1SLizhi Hou AMDXDNA_ERROR_NUM_UNKNOWN = 15, 34*b291e4f1SLizhi Hou }; 35*b291e4f1SLizhi Hou 36*b291e4f1SLizhi Hou enum amdxdna_error_module { 37*b291e4f1SLizhi Hou AMDXDNA_ERROR_MODULE_AIE_CORE = 3, 38*b291e4f1SLizhi Hou AMDXDNA_ERROR_MODULE_AIE_MEMORY, 39*b291e4f1SLizhi Hou AMDXDNA_ERROR_MODULE_AIE_SHIM, 40*b291e4f1SLizhi Hou AMDXDNA_ERROR_MODULE_AIE_NOC, 41*b291e4f1SLizhi Hou AMDXDNA_ERROR_MODULE_AIE_PL, 42*b291e4f1SLizhi Hou AMDXDNA_ERROR_MODULE_UNKNOWN = 8, 43*b291e4f1SLizhi Hou }; 44*b291e4f1SLizhi Hou 45*b291e4f1SLizhi Hou #define AMDXDNA_ERROR_ENCODE(err_num, err_mod) \ 46*b291e4f1SLizhi Hou (FIELD_PREP(AMDXDNA_ERR_NUM_MASK, err_num) | \ 47*b291e4f1SLizhi Hou FIELD_PREP_CONST(AMDXDNA_ERR_DRV_MASK, AMDXDNA_ERR_DRV_AIE) | \ 48*b291e4f1SLizhi Hou FIELD_PREP_CONST(AMDXDNA_ERR_SEV_MASK, AMDXDNA_ERR_SEV_CRITICAL) | \ 49*b291e4f1SLizhi Hou FIELD_PREP(AMDXDNA_ERR_MOD_MASK, err_mod) | \ 50*b291e4f1SLizhi Hou FIELD_PREP_CONST(AMDXDNA_ERR_CLASS_MASK, AMDXDNA_ERR_CLASS_AIE)) 51*b291e4f1SLizhi Hou 52*b291e4f1SLizhi Hou #define AMDXDNA_EXTRA_ERR_COL_MASK GENMASK_U64(7, 0) 53*b291e4f1SLizhi Hou #define AMDXDNA_EXTRA_ERR_ROW_MASK GENMASK_U64(15, 8) 54*b291e4f1SLizhi Hou 55*b291e4f1SLizhi Hou #define AMDXDNA_EXTRA_ERR_ENCODE(row, col) \ 56*b291e4f1SLizhi Hou (FIELD_PREP(AMDXDNA_EXTRA_ERR_COL_MASK, col) | \ 57*b291e4f1SLizhi Hou FIELD_PREP(AMDXDNA_EXTRA_ERR_ROW_MASK, row)) 58*b291e4f1SLizhi Hou 59*b291e4f1SLizhi Hou #endif /* _AMDXDNA_ERROR_H_ */ 60