1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #ifndef _AMDXDNA_CTX_H_ 7 #define _AMDXDNA_CTX_H_ 8 9 #include <linux/bitfield.h> 10 11 #include "amdxdna_gem.h" 12 13 struct amdxdna_hwctx_priv; 14 15 enum ert_cmd_opcode { 16 ERT_START_CU = 0, 17 ERT_CMD_CHAIN = 19, 18 ERT_START_NPU = 20, 19 ERT_INVALID_CMD = ~0U, 20 }; 21 22 enum ert_cmd_state { 23 ERT_CMD_STATE_INVALID, 24 ERT_CMD_STATE_NEW, 25 ERT_CMD_STATE_QUEUED, 26 ERT_CMD_STATE_RUNNING, 27 ERT_CMD_STATE_COMPLETED, 28 ERT_CMD_STATE_ERROR, 29 ERT_CMD_STATE_ABORT, 30 ERT_CMD_STATE_SUBMITTED, 31 ERT_CMD_STATE_TIMEOUT, 32 ERT_CMD_STATE_NORESPONSE, 33 }; 34 35 /* 36 * Interpretation of the beginning of data payload for ERT_START_NPU in 37 * amdxdna_cmd. The rest of the payload in amdxdna_cmd is regular kernel args. 38 */ 39 struct amdxdna_cmd_start_npu { 40 u64 buffer; /* instruction buffer address */ 41 u32 buffer_size; /* size of buffer in bytes */ 42 u32 prop_count; /* properties count */ 43 u32 prop_args[]; /* properties and regular kernel arguments */ 44 }; 45 46 /* 47 * Interpretation of the beginning of data payload for ERT_CMD_CHAIN in 48 * amdxdna_cmd. The rest of the payload in amdxdna_cmd is cmd BO handles. 49 */ 50 struct amdxdna_cmd_chain { 51 u32 command_count; 52 u32 submit_index; 53 u32 error_index; 54 u32 reserved[3]; 55 u64 data[] __counted_by(command_count); 56 }; 57 58 /* Exec buffer command header format */ 59 #define AMDXDNA_CMD_STATE GENMASK(3, 0) 60 #define AMDXDNA_CMD_EXTRA_CU_MASK GENMASK(11, 10) 61 #define AMDXDNA_CMD_COUNT GENMASK(22, 12) 62 #define AMDXDNA_CMD_OPCODE GENMASK(27, 23) 63 struct amdxdna_cmd { 64 u32 header; 65 u32 data[]; 66 }; 67 68 #define INVALID_CU_IDX (~0U) 69 70 struct amdxdna_hwctx { 71 struct amdxdna_client *client; 72 struct amdxdna_hwctx_priv *priv; 73 char *name; 74 75 u32 id; 76 u32 max_opc; 77 u32 num_tiles; 78 u32 mem_size; 79 u32 fw_ctx_id; 80 u32 col_list_len; 81 u32 *col_list; 82 u32 start_col; 83 u32 num_col; 84 #define HWCTX_STAT_INIT 0 85 #define HWCTX_STAT_READY 1 86 #define HWCTX_STAT_STOP 2 87 u32 status; 88 u32 old_status; 89 90 struct amdxdna_qos_info qos; 91 struct amdxdna_hwctx_param_config_cu *cus; 92 u32 syncobj_hdl; 93 94 atomic64_t job_submit_cnt; 95 atomic64_t job_free_cnt ____cacheline_aligned_in_smp; 96 }; 97 98 #define drm_job_to_xdna_job(j) \ 99 container_of(j, struct amdxdna_sched_job, base) 100 101 enum amdxdna_job_opcode { 102 SYNC_DEBUG_BO, 103 ATTACH_DEBUG_BO, 104 DETACH_DEBUG_BO, 105 }; 106 107 struct amdxdna_drv_cmd { 108 enum amdxdna_job_opcode opcode; 109 u32 result; 110 }; 111 112 struct amdxdna_sched_job { 113 struct drm_sched_job base; 114 struct kref refcnt; 115 struct amdxdna_hwctx *hwctx; 116 struct mm_struct *mm; 117 /* The fence to notice DRM scheduler that job is done by hardware */ 118 struct dma_fence *fence; 119 /* user can wait on this fence */ 120 struct dma_fence *out_fence; 121 bool job_done; 122 bool job_timeout; 123 u64 seq; 124 struct amdxdna_drv_cmd *drv_cmd; 125 struct amdxdna_gem_obj *cmd_bo; 126 size_t bo_cnt; 127 struct drm_gem_object *bos[] __counted_by(bo_cnt); 128 }; 129 130 static inline u32 131 amdxdna_cmd_get_op(struct amdxdna_gem_obj *abo) 132 { 133 struct amdxdna_cmd *cmd = abo->mem.kva; 134 135 return FIELD_GET(AMDXDNA_CMD_OPCODE, cmd->header); 136 } 137 138 static inline void 139 amdxdna_cmd_set_state(struct amdxdna_gem_obj *abo, enum ert_cmd_state s) 140 { 141 struct amdxdna_cmd *cmd = abo->mem.kva; 142 143 cmd->header &= ~AMDXDNA_CMD_STATE; 144 cmd->header |= FIELD_PREP(AMDXDNA_CMD_STATE, s); 145 } 146 147 static inline enum ert_cmd_state 148 amdxdna_cmd_get_state(struct amdxdna_gem_obj *abo) 149 { 150 struct amdxdna_cmd *cmd = abo->mem.kva; 151 152 return FIELD_GET(AMDXDNA_CMD_STATE, cmd->header); 153 } 154 155 void *amdxdna_cmd_get_payload(struct amdxdna_gem_obj *abo, u32 *size); 156 u32 amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo); 157 158 void amdxdna_sched_job_cleanup(struct amdxdna_sched_job *job); 159 void amdxdna_hwctx_remove_all(struct amdxdna_client *client); 160 int amdxdna_hwctx_walk(struct amdxdna_client *client, void *arg, 161 int (*walk)(struct amdxdna_hwctx *hwctx, void *arg)); 162 int amdxdna_hwctx_sync_debug_bo(struct amdxdna_client *client, u32 debug_bo_hdl); 163 164 int amdxdna_cmd_submit(struct amdxdna_client *client, 165 struct amdxdna_drv_cmd *drv_cmd, u32 cmd_bo_hdls, 166 u32 *arg_bo_hdls, u32 arg_bo_cnt, 167 u32 hwctx_hdl, u64 *seq); 168 169 int amdxdna_cmd_wait(struct amdxdna_client *client, u32 hwctx_hdl, 170 u64 seq, u32 timeout); 171 172 int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 173 int amdxdna_drm_config_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 174 int amdxdna_drm_destroy_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 175 int amdxdna_drm_submit_cmd_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 176 177 #endif /* _AMDXDNA_CTX_H_ */ 178