1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #ifndef _AMDXDNA_CTX_H_ 7 #define _AMDXDNA_CTX_H_ 8 9 #include <linux/bitfield.h> 10 11 #include "amdxdna_gem.h" 12 13 struct amdxdna_hwctx_priv; 14 15 enum ert_cmd_opcode { 16 ERT_START_CU = 0, 17 ERT_START_DPU = 18, 18 ERT_CMD_CHAIN = 19, 19 ERT_START_NPU = 20, 20 ERT_START_NPU_PREEMPT = 21, 21 ERT_START_NPU_PREEMPT_ELF = 22, 22 ERT_INVALID_CMD = ~0U, 23 }; 24 25 enum ert_cmd_state { 26 ERT_CMD_STATE_INVALID, 27 ERT_CMD_STATE_NEW, 28 ERT_CMD_STATE_QUEUED, 29 ERT_CMD_STATE_RUNNING, 30 ERT_CMD_STATE_COMPLETED, 31 ERT_CMD_STATE_ERROR, 32 ERT_CMD_STATE_ABORT, 33 ERT_CMD_STATE_SUBMITTED, 34 ERT_CMD_STATE_TIMEOUT, 35 ERT_CMD_STATE_NORESPONSE, 36 }; 37 38 /* 39 * Interpretation of the beginning of data payload for ERT_START_NPU in 40 * amdxdna_cmd. The rest of the payload in amdxdna_cmd is regular kernel args. 41 */ 42 struct amdxdna_cmd_start_npu { 43 u64 buffer; /* instruction buffer address */ 44 u32 buffer_size; /* size of buffer in bytes */ 45 u32 prop_count; /* properties count */ 46 u32 prop_args[]; /* properties and regular kernel arguments */ 47 }; 48 49 /* 50 * Interpretation of the beginning of data payload for ERT_CMD_CHAIN in 51 * amdxdna_cmd. The rest of the payload in amdxdna_cmd is cmd BO handles. 52 */ 53 struct amdxdna_cmd_chain { 54 u32 command_count; 55 u32 submit_index; 56 u32 error_index; 57 u32 reserved[3]; 58 u64 data[] __counted_by(command_count); 59 }; 60 61 /* 62 * Interpretation of the beginning of data payload for ERT_START_NPU_PREEMPT in 63 * amdxdna_cmd. The rest of the payload in amdxdna_cmd is regular kernel args. 64 */ 65 struct amdxdna_cmd_preempt_data { 66 u64 inst_buf; /* instruction buffer address */ 67 u64 save_buf; /* save buffer address */ 68 u64 restore_buf; /* restore buffer address */ 69 u32 inst_size; /* size of instruction buffer in bytes */ 70 u32 save_size; /* size of save buffer in bytes */ 71 u32 restore_size; /* size of restore buffer in bytes */ 72 u32 inst_prop_cnt; /* properties count */ 73 u32 prop_args[]; /* properties and regular kernel arguments */ 74 }; 75 76 #define AMDXDNA_CMD_CTX_HEALTH_V1 1 77 #define AMDXDNA_CMD_CTX_HEALTH_AIE2 0 78 struct amdxdna_ctx_health { 79 u32 version; 80 u32 npu_gen; 81 }; 82 83 /* Exec buffer command header format */ 84 #define AMDXDNA_CMD_STATE GENMASK(3, 0) 85 #define AMDXDNA_CMD_EXTRA_CU_MASK GENMASK(11, 10) 86 #define AMDXDNA_CMD_COUNT GENMASK(22, 12) 87 #define AMDXDNA_CMD_OPCODE GENMASK(27, 23) 88 struct amdxdna_cmd { 89 u32 header; 90 u32 data[]; 91 }; 92 93 #define INVALID_CU_IDX (~0U) 94 95 struct amdxdna_hwctx { 96 struct amdxdna_client *client; 97 struct amdxdna_hwctx_priv *priv; 98 char *name; 99 100 u32 id; 101 u32 max_opc; 102 u32 num_tiles; 103 u32 mem_size; 104 u32 fw_ctx_id; 105 u32 col_list_len; 106 u32 *col_list; 107 u32 start_col; 108 u32 num_col; 109 u32 umq_bo_hdl; 110 u32 doorbell_offset; 111 u32 num_unused_col; 112 u32 last_attached_heap; 113 114 struct amdxdna_qos_info qos; 115 struct amdxdna_hwctx_param_config_cu *cus; 116 u32 syncobj_hdl; 117 118 atomic64_t job_submit_cnt; 119 atomic64_t job_free_cnt ____cacheline_aligned_in_smp; 120 }; 121 122 #define drm_job_to_xdna_job(j) \ 123 container_of(j, struct amdxdna_sched_job, base) 124 125 enum amdxdna_job_opcode { 126 DEFAULT_IO, 127 SYNC_DEBUG_BO, 128 ATTACH_DEBUG_BO, 129 DETACH_DEBUG_BO, 130 }; 131 132 struct amdxdna_drv_cmd { 133 enum amdxdna_job_opcode opcode; 134 u32 result; 135 struct kref refcnt; 136 }; 137 138 struct app_health_report; 139 union amdxdna_job_priv { 140 struct app_health_report *aie2_health; 141 }; 142 143 struct amdxdna_sched_job { 144 struct drm_sched_job base; 145 struct kref refcnt; 146 struct amdxdna_hwctx *hwctx; 147 struct mm_struct *mm; 148 /* The fence to notice DRM scheduler that job is done by hardware */ 149 struct dma_fence *fence; 150 /* user can wait on this fence */ 151 struct dma_fence *out_fence; 152 bool job_done; 153 bool job_timeout; 154 u64 seq; 155 struct amdxdna_drv_cmd *drv_cmd; 156 struct amdxdna_gem_obj *cmd_bo; 157 union amdxdna_job_priv priv; 158 size_t bo_cnt; 159 struct drm_gem_object *bos[] __counted_by(bo_cnt); 160 }; 161 162 #define aie2_job_health priv.aie2_health 163 164 static inline u32 165 amdxdna_cmd_get_op(struct amdxdna_gem_obj *abo) 166 { 167 struct amdxdna_cmd *cmd = amdxdna_gem_vmap(abo); 168 169 if (!cmd) 170 return ERT_INVALID_CMD; 171 172 return FIELD_GET(AMDXDNA_CMD_OPCODE, cmd->header); 173 } 174 175 static inline void 176 amdxdna_cmd_set_state(struct amdxdna_gem_obj *abo, enum ert_cmd_state s) 177 { 178 struct amdxdna_cmd *cmd = amdxdna_gem_vmap(abo); 179 180 if (!cmd) 181 return; 182 183 cmd->header &= ~AMDXDNA_CMD_STATE; 184 cmd->header |= FIELD_PREP(AMDXDNA_CMD_STATE, s); 185 } 186 187 static inline enum ert_cmd_state 188 amdxdna_cmd_get_state(struct amdxdna_gem_obj *abo) 189 { 190 struct amdxdna_cmd *cmd = amdxdna_gem_vmap(abo); 191 192 if (!cmd) 193 return ERT_CMD_STATE_INVALID; 194 195 return FIELD_GET(AMDXDNA_CMD_STATE, cmd->header); 196 } 197 198 void *amdxdna_cmd_get_payload(struct amdxdna_gem_obj *abo, u32 *size); 199 u32 amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo); 200 int amdxdna_cmd_set_error(struct amdxdna_gem_obj *abo, 201 struct amdxdna_sched_job *job, u32 cmd_idx, 202 enum ert_cmd_state error_state, 203 void *err_data, size_t size); 204 205 void amdxdna_sched_job_cleanup(struct amdxdna_sched_job *job); 206 void amdxdna_hwctx_remove_all(struct amdxdna_client *client); 207 int amdxdna_hwctx_walk(struct amdxdna_client *client, void *arg, 208 int (*walk)(struct amdxdna_hwctx *hwctx, void *arg)); 209 int amdxdna_hwctx_sync_debug_bo(struct amdxdna_client *client, u32 debug_bo_hdl); 210 int amdxdna_update_heap(struct amdxdna_client *client, struct amdxdna_hwctx *hwctx); 211 212 int amdxdna_cmd_submit(struct amdxdna_client *client, 213 struct amdxdna_drv_cmd *drv_cmd, u32 cmd_bo_hdls, 214 u32 *arg_bo_hdls, u32 arg_bo_cnt, 215 u32 hwctx_hdl, u64 *seq); 216 217 int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 218 int amdxdna_drm_config_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 219 int amdxdna_drm_destroy_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 220 int amdxdna_drm_submit_cmd_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 221 int amdxdna_drm_wait_cmd_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 222 223 #endif /* _AMDXDNA_CTX_H_ */ 224