1*be462c97SLizhi Hou /* SPDX-License-Identifier: GPL-2.0 */ 2*be462c97SLizhi Hou /* 3*be462c97SLizhi Hou * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. 4*be462c97SLizhi Hou */ 5*be462c97SLizhi Hou 6*be462c97SLizhi Hou #ifndef _AMDXDNA_CTX_H_ 7*be462c97SLizhi Hou #define _AMDXDNA_CTX_H_ 8*be462c97SLizhi Hou 9*be462c97SLizhi Hou struct amdxdna_hwctx { 10*be462c97SLizhi Hou struct amdxdna_client *client; 11*be462c97SLizhi Hou struct amdxdna_hwctx_priv *priv; 12*be462c97SLizhi Hou char *name; 13*be462c97SLizhi Hou 14*be462c97SLizhi Hou u32 id; 15*be462c97SLizhi Hou u32 max_opc; 16*be462c97SLizhi Hou u32 num_tiles; 17*be462c97SLizhi Hou u32 mem_size; 18*be462c97SLizhi Hou u32 fw_ctx_id; 19*be462c97SLizhi Hou u32 col_list_len; 20*be462c97SLizhi Hou u32 *col_list; 21*be462c97SLizhi Hou u32 start_col; 22*be462c97SLizhi Hou u32 num_col; 23*be462c97SLizhi Hou #define HWCTX_STAT_INIT 0 24*be462c97SLizhi Hou #define HWCTX_STAT_READY 1 25*be462c97SLizhi Hou #define HWCTX_STAT_STOP 2 26*be462c97SLizhi Hou u32 status; 27*be462c97SLizhi Hou u32 old_status; 28*be462c97SLizhi Hou 29*be462c97SLizhi Hou struct amdxdna_qos_info qos; 30*be462c97SLizhi Hou struct amdxdna_hwctx_param_config_cu *cus; 31*be462c97SLizhi Hou u32 syncobj_hdl; 32*be462c97SLizhi Hou }; 33*be462c97SLizhi Hou 34*be462c97SLizhi Hou void amdxdna_hwctx_remove_all(struct amdxdna_client *client); 35*be462c97SLizhi Hou int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 36*be462c97SLizhi Hou int amdxdna_drm_config_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 37*be462c97SLizhi Hou int amdxdna_drm_destroy_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 38*be462c97SLizhi Hou 39*be462c97SLizhi Hou #endif /* _AMDXDNA_CTX_H_ */ 40